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Some code cleanup.

This commit is contained in:
Wolfgang Denk 2007-03-04 01:36:05 +01:00 committed by Wolfgang Denk
parent b24444f1b3
commit 647d3c3eed
8 changed files with 78 additions and 94 deletions
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2
board/mpc7448hpc2/mpc7448hpc2.c
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@ -47,7 +47,7 @@ int display_mem_map (void);
void after_reloc (ulong dest_addr) void after_reloc (ulong dest_addr)
{ {
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
/* /*
* Jump to the main U-Boot board init code * Jump to the main U-Boot board init code
*/ */

24
board/mpc7448hpc2/tsi108_init.c
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@ -179,7 +179,7 @@ int board_early_init_r (void)
ulong temp, i; ulong temp, i;
ulong reg_val; ulong reg_val;
volatile ulong *reg_ptr; volatile ulong *reg_ptr;
reg_ptr = reg_ptr =
(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900); (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
@ -300,7 +300,7 @@ int board_early_init_r (void)
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1, out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
0x7C0F2000); 0x7C0F2000);
__asm__ __volatile__ ("sync"); __asm__ __volatile__ ("sync");
/* /*
* Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode. * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
* value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable) * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
@ -312,7 +312,7 @@ int board_early_init_r (void)
/* Make sure that OCN_BAR2 decoder is set (to allow following /* Make sure that OCN_BAR2 decoder is set (to allow following
* immediate read from SDRAM) * immediate read from SDRAM)
*/ */
temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1); temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
__asm__ __volatile__ ("sync"); __asm__ __volatile__ ("sync");
@ -327,11 +327,11 @@ int board_early_init_r (void)
* and enable all HLP banks and not just HLP 0 as is being done for * and enable all HLP banks and not just HLP 0 as is being done for
* Taiga Rev. 2. * Taiga Rev. 2.
*/ */
env_init (); env_init ();
#ifndef DISABLE_PBM #ifndef DISABLE_PBM
/* /*
* For IBM processors we have to set Address-Only commands generated * For IBM processors we have to set Address-Only commands generated
* by PBM that are different from ones set after reset. * by PBM that are different from ones set after reset.
@ -475,10 +475,10 @@ int board_early_init_r (void)
for (i = 0; i < 32; i++) { for (i = 0; i < 32; i++) {
*reg_ptr++ = reg_val; /* P2O_BAR3_LUTx */ *reg_ptr++ = reg_val; /* P2O_BAR3_LUTx */
/* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */ /* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
*reg_ptr++ = 0; *reg_ptr++ = 0;
/* offset = 16MB, address translation is enabled to allow byte swapping */ /* offset = 16MB, address translation is enabled to allow byte swapping */
reg_val += 0x01000000; reg_val += 0x01000000;
} }
@ -507,7 +507,7 @@ int board_early_init_r (void)
#endif /* !DISABLE_PBM */ #endif /* !DISABLE_PBM */
#ifdef ENABLE_PCI_CSR_BAR #ifdef ENABLE_PCI_CSR_BAR
/* open if required access to Tsi108 CSRs from the PCI/X bus */ /* open if required access to Tsi108 CSRs from the PCI/X bus */
/* enable BAR0 on the PCI/X bus */ /* enable BAR0 on the PCI/X bus */
reg_val = in32(CFG_TSI108_CSR_BASE + reg_val = in32(CFG_TSI108_CSR_BASE +
@ -528,7 +528,7 @@ int board_early_init_r (void)
/* /*
* Finally enable PCI/X Bus Master and Memory Space access * Finally enable PCI/X Bus Master and Memory Space access
*/ */
reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR); reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
reg_val |= 0x06; reg_val |= 0x06;
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val); out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
@ -555,7 +555,7 @@ int board_early_init_r (void)
* Ensure that Machine Check exception is enabled * Ensure that Machine Check exception is enabled
* We need it to support PCI Bus probing (configuration reads) * We need it to support PCI Bus probing (configuration reads)
*/ */
reg_val = mfmsr (); reg_val = mfmsr ();
mtmsr(reg_val | MSR_ME); mtmsr(reg_val | MSR_ME);
@ -631,7 +631,7 @@ int misc_init_r (void)
* thing done with regards to enabling diabling the cache. * thing done with regards to enabling diabling the cache.
* So this seems like a good place to print all this information * So this seems like a good place to print all this information
*/ */
printf ("CACHE: "); printf ("CACHE: ");
switch (get_cpu_type()) { switch (get_cpu_type()) {
case CPU_7447A: case CPU_7447A:

4
cpu/74xx_7xx/cpu.c
View File

@ -308,9 +308,9 @@ ft_cpu_setup (void *blob, bd_t *bd)
u32 *p; u32 *p;
ulong clock; ulong clock;
int len; int len;
clock = bd->bi_busfreq; clock = bd->bi_busfreq;
p = ft_get_prop (blob, "/cpus/" OF_CPU "/bus-frequency", &len); p = ft_get_prop (blob, "/cpus/" OF_CPU "/bus-frequency", &len);
if (p != NULL) if (p != NULL)
*p = cpu_to_be32 (clock); *p = cpu_to_be32 (clock);

10
cpu/ppc4xx/44x_spd_ddr2.c
View File

@ -168,8 +168,8 @@ static void program_codt(unsigned long *dimm_populated,
static void program_mode(unsigned long *dimm_populated, static void program_mode(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr, unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks, unsigned long num_dimm_banks,
ddr_cas_id_t *selected_cas, ddr_cas_id_t *selected_cas,
int *write_recovery); int *write_recovery);
static void program_tr(unsigned long *dimm_populated, static void program_tr(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr, unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks); unsigned long num_dimm_banks);
@ -185,7 +185,7 @@ static void program_copt1(unsigned long *dimm_populated,
static void program_initplr(unsigned long *dimm_populated, static void program_initplr(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr, unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks, unsigned long num_dimm_banks,
ddr_cas_id_t selected_cas, ddr_cas_id_t selected_cas,
int write_recovery); int write_recovery);
static unsigned long is_ecc_enabled(void); static unsigned long is_ecc_enabled(void);
static void program_ecc(unsigned long *dimm_populated, static void program_ecc(unsigned long *dimm_populated,
@ -1110,7 +1110,7 @@ static void program_codt(unsigned long *dimm_populated,
modt3 = 0x00000000; modt3 = 0x00000000;
} }
} }
} else { } else {
codt |= SDRAM_CODT_DQS_2_5_V_DDR1; codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
modt0 = 0x00000000; modt0 = 0x00000000;
modt1 = 0x00000000; modt1 = 0x00000000;
@ -1149,7 +1149,7 @@ static void program_codt(unsigned long *dimm_populated,
static void program_initplr(unsigned long *dimm_populated, static void program_initplr(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr, unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks, unsigned long num_dimm_banks,
ddr_cas_id_t selected_cas, ddr_cas_id_t selected_cas,
int write_recovery) int write_recovery)
{ {
u32 cas = 0; u32 cas = 0;

72
cpu/ppc4xx/start.S
View File

@ -1858,11 +1858,11 @@ pll_wait:
#endif /* CONFIG_405EP */ #endif /* CONFIG_405EP */
#if defined(CONFIG_440) #if defined(CONFIG_440)
#define function_prolog(func_name) .text; \ #define function_prolog(func_name) .text; \
.align 2; \ .align 2; \
.globl func_name; \ .globl func_name; \
func_name: func_name:
#define function_epilog(func_name) .type func_name,@function; \ #define function_epilog(func_name) .type func_name,@function; \
.size func_name,.-func_name .size func_name,.-func_name
/*----------------------------------------------------------------------------+ /*----------------------------------------------------------------------------+
@ -1916,43 +1916,43 @@ pll_wait:
/*----------------------------------------------------------------------------+ /*----------------------------------------------------------------------------+
| dcbz_area. | dcbz_area.
+----------------------------------------------------------------------------*/ +----------------------------------------------------------------------------*/
function_prolog(dcbz_area) function_prolog(dcbz_area)
rlwinm. r5,r4,0,27,31 rlwinm. r5,r4,0,27,31
rlwinm r5,r4,27,5,31 rlwinm r5,r4,27,5,31
beq ..d_ra2 beq ..d_ra2
addi r5,r5,0x0001 addi r5,r5,0x0001
..d_ra2:mtctr r5 ..d_ra2:mtctr r5
..d_ag2:dcbz r0,r3 ..d_ag2:dcbz r0,r3
addi r3,r3,32 addi r3,r3,32
bdnz ..d_ag2 bdnz ..d_ag2
sync sync
blr blr
function_epilog(dcbz_area) function_epilog(dcbz_area)
/*----------------------------------------------------------------------------+ /*----------------------------------------------------------------------------+
| dflush. Assume 32K at vector address is cachable. | dflush. Assume 32K at vector address is cachable.
+----------------------------------------------------------------------------*/ +----------------------------------------------------------------------------*/
function_prolog(dflush) function_prolog(dflush)
mfmsr r9 mfmsr r9
rlwinm r8,r9,0,15,13 rlwinm r8,r9,0,15,13
rlwinm r8,r8,0,17,15 rlwinm r8,r8,0,17,15
mtmsr r8 mtmsr r8
addi r3,r0,0x0000 addi r3,r0,0x0000
mtspr dvlim,r3 mtspr dvlim,r3
mfspr r3,ivpr mfspr r3,ivpr
addi r4,r0,1024 addi r4,r0,1024
mtctr r4 mtctr r4
..dflush_loop: ..dflush_loop:
lwz r6,0x0(r3) lwz r6,0x0(r3)
addi r3,r3,32 addi r3,r3,32
bdnz ..dflush_loop bdnz ..dflush_loop
addi r3,r3,-32 addi r3,r3,-32
mtctr r4 mtctr r4
..ag: dcbf r0,r3 ..ag: dcbf r0,r3
addi r3,r3,-32 addi r3,r3,-32
bdnz ..ag bdnz ..ag
sync sync
mtmsr r9 mtmsr r9
blr blr
function_epilog(dflush) function_epilog(dflush)
#endif /* CONFIG_440 */ #endif /* CONFIG_440 */

25
doc/README.mpc7448hpc2
View File

@ -92,7 +92,7 @@ SW2[1-6]: CPU core frequency
CPU Core Frequency (MHz) CPU Core Frequency (MHz)
Bus Frequency Bus Frequency
123456 100 133 167 200 Ratio 123456 100 133 167 200 Ratio
------ ------
SW2=101100 500 667 833 1000 5x SW2=101100 500 667 833 1000 5x
SW2=100100 550 733 917 1100 5.5x SW2=100100 550 733 917 1100 5.5x
@ -109,43 +109,43 @@ hardware specifications for more information.
SW2[7-8]: Bus Protocol and CPU Reset Option SW2[7-8]: Bus Protocol and CPU Reset Option
7 7
- -
SW2=0 System bus uses MPX bus protocol SW2=0 System bus uses MPX bus protocol
SW2=1 System bus uses 60x bus protocol SW2=1 System bus uses 60x bus protocol
8 8
- -
SW2=0 TSI108 can cause CPU reset SW2=0 TSI108 can cause CPU reset
SW2=1 TSI108 can not cause CPU reset SW2=1 TSI108 can not cause CPU reset
SW3[1-8] system options SW3[1-8] system options
123 123
--- ---
SW3=xxx Connected to GPIO[0:2] on TSI108 SW3=xxx Connected to GPIO[0:2] on TSI108
4 4
- -
SW3=0 CPU boots from low half of flash SW3=0 CPU boots from low half of flash
SW3=1 CPU boots from high half of flash SW3=1 CPU boots from high half of flash
5 5
- -
SW3=0 SATA and slot2 connected to PCI bus SW3=0 SATA and slot2 connected to PCI bus
SW3=1 Only slot1 connected to PCI bus SW3=1 Only slot1 connected to PCI bus
6 6
- -
SW3=0 USB connected to PCI bus SW3=0 USB connected to PCI bus
SW3=1 USB disconnected from PCI bus SW3=1 USB disconnected from PCI bus
7 7
- -
SW3=0 Flash is write protected SW3=0 Flash is write protected
SW3=1 Flash is NOT write protected SW3=1 Flash is NOT write protected
8 8
- -
SW3=0 CPU will boot from flash SW3=0 CPU will boot from flash
SW3=1 CPU will boot from PromJet SW3=1 CPU will boot from PromJet
@ -166,20 +166,19 @@ SW4[4-6]: DDR2 SDRAM frequency
Bus Frequency (MHz) Bus Frequency (MHz)
--- ---
SW4=000 external clock SW4=000 external clock
SW4=011 system clock SW4=011 system clock
SW4=100 133 SW4=100 133
SW4=101 166 SW4=101 166
SW4=110 200 SW4=110 200
others reserved others reserved
SW4[7-8]: PCI/PCI-X frequency control SW4[7-8]: PCI/PCI-X frequency control
7 7
- -
SW4=0 PCI/PCI-X bus operates normally SW4=0 PCI/PCI-X bus operates normally
SW4=1 PCI bus forced to PCI-33 mode SW4=1 PCI bus forced to PCI-33 mode
8 8
- -
SW4=0 PCI-X mode at 133 MHz allowed SW4=0 PCI-X mode at 133 MHz allowed
SW4=1 PCI-X mode limited to 100 MHz SW4=1 PCI-X mode limited to 100 MHz

33
drivers/tsi108_i2c.c
View File

@ -82,15 +82,10 @@ static int i2c_read_byte (
/* Wait until operation completed */ /* Wait until operation completed */
do { do {
/* Read I2C operation status */ /* Read I2C operation status */
temp = temp = *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2);
*(u32 *) (CFG_TSI108_CSR_BASE + chan_offset +
I2C_CNTRL2);
if (0 == if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_START))) {
(temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_START))) if (0 == (temp &
{
if (0 ==
(temp &
(I2C_CNTRL2_I2C_CFGERR | (I2C_CNTRL2_I2C_CFGERR |
I2C_CNTRL2_I2C_TO_ERR)) I2C_CNTRL2_I2C_TO_ERR))
) { ) {
@ -152,9 +147,7 @@ int i2c_read (uchar chip_addr, uint byte_addr, int alen,
/* Check for valid I2C address */ /* Check for valid I2C address */
if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) { if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) {
while (len--) { while (len--) {
op_status = op_status = i2c_read_byte(i2c_if, chip_addr, byte_addr++, buffer++);
i2c_read_byte(i2c_if, chip_addr, byte_addr++,
buffer++);
if (TSI108_I2C_SUCCESS != op_status) { if (TSI108_I2C_SUCCESS != op_status) {
DPRINT (("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len)); DPRINT (("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len));
@ -182,10 +175,7 @@ static int i2c_write_byte (uchar chip_addr,/* I2C device address on the bus */
/* Check if I2C operation is in progress */ /* Check if I2C operation is in progress */
temp = *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2); temp = *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
if (0 == if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) {
(temp &
(I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START)))
{
/* Place data into the I2C Tx Register */ /* Place data into the I2C Tx Register */
*(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
I2C_TX_DATA) = (u32) * buffer; I2C_TX_DATA) = (u32) * buffer;
@ -200,7 +190,7 @@ static int i2c_write_byte (uchar chip_addr,/* I2C device address on the bus */
/* Issue the write command (at this moment all other parameters /* Issue the write command (at this moment all other parameters
* are 0 (size = 1 byte, lane = 0) * are 0 (size = 1 byte, lane = 0)
*/ */
*(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
I2C_CNTRL2) = (I2C_CNTRL2_START); I2C_CNTRL2) = (I2C_CNTRL2_START);
@ -209,15 +199,10 @@ static int i2c_write_byte (uchar chip_addr,/* I2C device address on the bus */
/* Wait until operation completed */ /* Wait until operation completed */
do { do {
/* Read I2C operation status */ /* Read I2C operation status */
temp = temp = *(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
*(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
I2C_CNTRL2);
if (0 == if (0 == (temp & (I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) {
(temp & (I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) if (0 == (temp &
{
if (0 ==
(temp &
(I2C_CNTRL2_I2C_CFGERR | (I2C_CNTRL2_I2C_CFGERR |
I2C_CNTRL2_I2C_TO_ERR))) { I2C_CNTRL2_I2C_TO_ERR))) {
op_status = TSI108_I2C_SUCCESS; op_status = TSI108_I2C_SUCCESS;

2
include/configs/mpc7448hpc2.h
View File

@ -285,7 +285,7 @@
/* PCI view of System Memory */ /* PCI view of System Memory */
#define CFG_PCI_MEMORY_BUS 0x00000000 #define CFG_PCI_MEMORY_BUS 0x00000000
#define CFG_PCI_MEMORY_PHYS 0x00000000 #define CFG_PCI_MEMORY_PHYS 0x00000000
#define CFG_PCI_MEMORY_SIZE 0x80000000 #define CFG_PCI_MEMORY_SIZE 0x80000000
/* PCI Memory Space */ /* PCI Memory Space */
#define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS) #define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS)