powerpc/t1040qds: Initialize EPHY2 clock to RGMII only
Setting FPGA register brdcfg9 EPHY2 bits to '0' to initialize EPHY2 clock to RGMII mode. Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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591dd19230
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@ -355,7 +355,9 @@ static void set_brdcfg9_for_gtx_clk(void)
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{
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{
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u8 brdcfg9;
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u8 brdcfg9;
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brdcfg9 = QIXIS_READ(brdcfg[9]);
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brdcfg9 = QIXIS_READ(brdcfg[9]);
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brdcfg9 |= (1 << 5);
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/* Initializing EPHY2 clock to RGMII mode */
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brdcfg9 &= ~(BRDCFG9_EPHY2_MASK);
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brdcfg9 |= (BRDCFG9_EPHY2_VAL);
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QIXIS_WRITE(brdcfg[9], brdcfg9);
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QIXIS_WRITE(brdcfg[9], brdcfg9);
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}
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}
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@ -17,6 +17,10 @@
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#define BRDCFG5_IMX_MASK 0xC0
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#define BRDCFG5_IMX_MASK 0xC0
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#define BRDCFG5_IMX_DIU 0x80
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#define BRDCFG5_IMX_DIU 0x80
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/* BRDCFG9[2] controls EPHY2 Clock */
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#define BRDCFG9_EPHY2_MASK 0x20
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#define BRDCFG9_EPHY2_VAL 0x00
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/* BRDCFG15[3] controls LCD Panel Powerdown*/
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/* BRDCFG15[3] controls LCD Panel Powerdown*/
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#define BRDCFG15_LCDPD_MASK 0x10
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#define BRDCFG15_LCDPD_MASK 0x10
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#define BRDCFG15_LCDPD_ENABLED 0x00
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#define BRDCFG15_LCDPD_ENABLED 0x00
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