OMAP3: Add SPL support to omap3_evm
Add Hynix 200MHz timing information to <asm/arch-omap3/mem.h>. This also changes CONFIG_SYS_TEXT_BASE to 0x80100000. Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
Tom Rini
Albert ARIBAUD
parent
75c57a3570
commit
673283f3fc
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@ -123,6 +123,32 @@ enum {
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V_MCFG_BANKALLOCATION_RBC | \
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V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR
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/* Hynix part of AM/DM37xEVM (200MHz optimized) */
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#define HYNIX_TDAL_200 6
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#define HYNIX_TDPL_200 3
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#define HYNIX_TRRD_200 2
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#define HYNIX_TRCD_200 4
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#define HYNIX_TRP_200 3
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#define HYNIX_TRAS_200 8
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#define HYNIX_TRC_200 11
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#define HYNIX_TRFC_200 18
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#define HYNIX_V_ACTIMA_200 \
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ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \
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HYNIX_TRAS_200, HYNIX_TRP_200, \
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HYNIX_TRCD_200, HYNIX_TRRD_200, \
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HYNIX_TDPL_200, HYNIX_TDAL_200)
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#define HYNIX_TWTR_200 2
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#define HYNIX_TCKE_200 1
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#define HYNIX_TXP_200 1
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#define HYNIX_XSR_200 28
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#define HYNIX_V_ACTIMB_200 \
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ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \
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HYNIX_TXP_200, HYNIX_XSR_200)
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#define HYNIX_RASWIDTH_200 0x3
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#define HYNIX_V_MCFG_200(size) MCFG((size), HYNIX_RASWIDTH_200)
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/* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
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#define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */
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/* 15/6 + 18/6 = 5.5 -> 6 */
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@ -1,33 +0,0 @@
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#
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# (C) Copyright 2006 - 2008
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# Texas Instruments, <www.ti.com>
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#
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# EVM uses OMAP3 (ARM-CortexA8) cpu
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# see http://www.ti.com/ for more information on Texas Instruments
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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# Physical Address:
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# 8000'0000 (bank0)
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# A000/0000 (bank1)
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# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
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# (mem base + reserved)
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# For use with external or internal boots.
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CONFIG_SYS_TEXT_BASE = 0x80008000
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@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2004-2008
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* (C) Copyright 2004-2011
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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@ -37,6 +37,7 @@
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <asm/mach-types.h>
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#include <linux/mtd/nand.h>
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#include "evm.h"
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#define OMAP3EVM_GPIO_ETH_RST_GEN1 64
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@ -119,6 +120,42 @@ int board_init(void)
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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/*
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* Routine: get_board_mem_timings
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* Description: If we use SPL then there is no x-loader nor config header
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* so we have to setup the DDR timings ourself on the first bank. This
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* provides the timing values back to the function that configures
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* the memory.
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*/
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void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
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u32 *mr)
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{
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int pop_mfr, pop_id;
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/*
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* We need to identify what PoP memory is on the board so that
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* we know what timings to use. To map the ID values please see
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* nand_ids.c
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*/
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identify_nand_chip(&pop_mfr, &pop_id);
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if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
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/* 256MB DDR */
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*mcfg = HYNIX_V_MCFG_200(256 << 20);
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*ctrla = HYNIX_V_ACTIMA_200;
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*ctrlb = HYNIX_V_ACTIMB_200;
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} else {
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/* 128MB DDR */
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*mcfg = MICRON_V_MCFG_165(128 << 20);
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*ctrla = MICRON_V_ACTIMA_165;
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*ctrlb = MICRON_V_ACTIMB_165;
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}
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*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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*mr = MICRON_V_MR_165;
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}
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#endif
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/*
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* Routine: misc_init_r
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* Description: Init ethernet (done here so udelay works)
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@ -238,7 +275,7 @@ int board_eth_init(bd_t *bis)
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}
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#endif /* CONFIG_CMD_NET */
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#ifdef CONFIG_GENERIC_MMC
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#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
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int board_mmc_init(bd_t *bis)
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{
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omap_mmc_init(0);
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@ -83,8 +83,21 @@
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_OMAP_HSMMC
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#define CONFIG_DOS_PARTITION
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/* SPL */
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SPL_FAT_SUPPORT
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
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#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
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#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
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#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
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/* Partition tables */
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/* Only need DOS partition support for SPL, currently */
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_EFI_PARTITION
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#endif
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#define CONFIG_DOS_PARTITION
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/* USB
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*
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@ -95,6 +108,26 @@
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#define CONFIG_MUSB_HCD
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/* #define CONFIG_MUSB_UDC */
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/* NAND SPL */
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#define CONFIG_SPL_NAND_SIMPLE
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
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CONFIG_SYS_NAND_ECCSIZE)
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#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
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CONFIG_SYS_NAND_ECCSTEPS)
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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/* -----------------------------------------------------------------------------
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* Include common board configuration
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* -----------------------------------------------------------------------------
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@ -26,7 +26,6 @@
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#define CONFIG_SDRC /* The chip has SDRC controller */
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#define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */
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#define CONFIG_OMAP3_MICRON_DDR /* with MICRON DDR part */
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#define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */
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#undef CONFIG_USE_IRQ /* no support for IRQs */
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@ -65,7 +64,6 @@
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*/
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#define CONFIG_NR_DRAM_BANKS 2
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#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
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#define PHYS_SDRAM_1_SIZE (32 << 20)
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#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
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/* Limits for memtest */
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@ -282,4 +280,32 @@
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#define CONFIG_SYS_CACHELINE_SIZE 64
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/* Defines for SPL */
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#define CONFIG_SPL
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#define CONFIG_SPL_TEXT_BASE 0x40200800
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#define CONFIG_SPL_MAX_SIZE (45 * 1024) /* 45 KB */
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#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
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#define CONFIG_SPL_BSS_START_ADDR 0x80000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBDISK_SUPPORT
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#define CONFIG_SPL_I2C_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_POWER_SUPPORT
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#define CONFIG_SPL_OMAP3_ID_NAND
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#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
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/*
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* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
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* 64 bytes before this address should be set aside for u-boot.img's
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* header. That is 0x800FFFC0--0x80100000 should not be used for any
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* other needs.
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*/
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#define CONFIG_SYS_TEXT_BASE 0x80100000
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#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#endif /* __OMAP3_EVM_COMMON_H */
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@ -88,4 +88,14 @@
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"root=/dev/mmcblk0p2 rw " \
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"rootfstype=ext3 rootwait"
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/*
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* SPL
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*/
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SPL_FAT_SUPPORT
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
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#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
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#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
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#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
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#endif /* __OMAP3_EVM_QUICK_MMC_H */
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@ -76,4 +76,26 @@
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"root=/dev/mtdblock4 rw " \
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"rootfstype=jffs2 "
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/*
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* SPL
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*/
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#define CONFIG_SPL_NAND_SIMPLE
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
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CONFIG_SYS_NAND_ECCSIZE)
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#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
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CONFIG_SYS_NAND_ECCSTEPS)
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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#endif /* __OMAP3_EVM_QUICK_NAND_H */
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