arm: Remove unmaintained davinci boards

These boards have not been converted to generic board by the deadline.
Remove dm355evm, dm355leopard, dm365evm, dm6467evm, dvevm, ea20, schmoogie,
sffsdr, sonata.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2015-08-30 19:18:59 -06:00 committed by Tom Rini
parent 7495e41ba6
commit 6761946fb7
62 changed files with 3 additions and 2884 deletions

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@ -18,36 +18,12 @@ config TARGET_DA850EVM
bool "DA850 EVM board"
select SUPPORT_SPL
config TARGET_OMAPL138_LCDK
bool "OMAPL138 LCDK"
select SUPPORT_SPL
config TARGET_DAVINCI_DM355EVM
bool "DM355 EVM board"
config TARGET_DAVINCI_DM355LEOPARD
bool "DM355 Leopard board"
config TARGET_DAVINCI_DM365EVM
bool "DM365 EVM board"
config TARGET_DAVINCI_DM6467EVM
bool "DM6467 EVM board"
config TARGET_DAVINCI_DVEVM
bool "DVEVM board"
config TARGET_EA20
bool "EA20 board"
config TARGET_DAVINCI_SCHMOOGIE
bool "Schmoogie board"
config TARGET_DAVINCI_SFFSDR
bool "SFFSDR board"
config TARGET_DAVINCI_SONATA
bool "Sonata board"
config TARGET_OMAPL138_LCDK
bool "OMAPL138 LCDK"
select SUPPORT_SPL
config TARGET_CALIMAIN
bool "Calimain board"
@ -60,15 +36,7 @@ config SYS_SOC
source "board/enbw/enbw_cmc/Kconfig"
source "board/Barix/ipam390/Kconfig"
source "board/davinci/da8xxevm/Kconfig"
source "board/davinci/dm355evm/Kconfig"
source "board/davinci/dm355leopard/Kconfig"
source "board/davinci/dm365evm/Kconfig"
source "board/davinci/dm6467evm/Kconfig"
source "board/davinci/dvevm/Kconfig"
source "board/davinci/ea20/Kconfig"
source "board/davinci/schmoogie/Kconfig"
source "board/davinci/sffsdr/Kconfig"
source "board/davinci/sonata/Kconfig"
source "board/omicron/calimain/Kconfig"
endif

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@ -1,12 +0,0 @@
if TARGET_DAVINCI_DM355EVM
config SYS_BOARD
default "dm355evm"
config SYS_VENDOR
default "davinci"
config SYS_CONFIG_NAME
default "davinci_dm355evm"
endif

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@ -1,6 +0,0 @@
DM355EVM BOARD
#M: Sandeep Paulraj <s-paulraj@ti.com>
S: Orphan (since 2014-08)
F: board/davinci/dm355evm/
F: include/configs/davinci_dm355evm.h
F: configs/davinci_dm355evm_defconfig

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@ -1,10 +0,0 @@
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := dm355evm.o

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@ -1,11 +0,0 @@
#
# Spectrum Digital DM355 EVM board
# dm355evm board has 1 bank of 128 MB DDR RAM
# Physical Address: 8000'0000 to 8800'0000
#
# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
#
#Provide at least 16MB spacing between us and the Linux Kernel image
CONFIG_SYS_TEXT_BASE = 0x81080000

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@ -1,144 +0,0 @@
/*
* Copyright (C) 2009 David Brownell
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <nand.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/davinci_misc.h>
#include <net.h>
#include <netdev.h>
#ifdef CONFIG_DAVINCI_MMC
#include <mmc.h>
#include <asm/arch/sdmmc_defs.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/*
* With the DM355 EVM, u-boot is *always* a third stage loader,
* unless a JTAG debugger handles the first two stages:
*
* - 1st stage is ROM Boot Loader (RBL), which searches for a
* second stage loader in one of three places based on SW7:
* NAND (with MMC/SD fallback), MMC/SD, or UART.
*
* - 2nd stage is User Boot Loader (UBL), using at most 30KB
* of on-chip SRAM, responsible for lowlevel init, and for
* loading the third stage loader into DRAM.
*
* - 3rd stage, that's us!
*/
int board_init(void)
{
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM355_EVM;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
/* We expect the UBL to have handled "lowlevel init", which
* involves setting up at least:
* - clocks
* + PLL1 (for ARM and peripherals) and PLL2 (for DDR)
* + clock divisors for those PLLs
* + LPSC_DDR module enabled
* + LPSC_TIMER0 module (still) enabled
* - EMIF
* + DDR init and timings
* + AEMIF timings (for NAND and DM9000)
* - pinmux
*
* Some of that is repeated here, mostly as a precaution.
*/
/* AEMIF: Some "address" lines are available as GPIOs. A3..A13
* could be too if we used A12 as a GPIO during NAND chipselect
* (and Linux did too), letting us control the LED on A7/GPIO61.
*/
REG(PINMUX2) = 0x0c08;
/* UART0 may still be in SyncReset if we didn't boot from UART */
davinci_enable_uart0();
/* EDMA may be in SyncReset too; turn it on, Linux won't (yet) */
lpsc_on(DAVINCI_LPSC_TPCC);
lpsc_on(DAVINCI_LPSC_TPTC0);
lpsc_on(DAVINCI_LPSC_TPTC1);
return 0;
}
#ifdef CONFIG_DRIVER_DM9000
int board_eth_init(bd_t *bis)
{
return dm9000_initialize(bis);
}
#endif
#ifdef CONFIG_NAND_DAVINCI
static void nand_dm355evm_select_chip(struct mtd_info *mtd, int chip)
{
struct nand_chip *this = mtd->priv;
unsigned long wbase = (unsigned long) this->IO_ADDR_W;
unsigned long rbase = (unsigned long) this->IO_ADDR_R;
if (chip == 1) {
__set_bit(14, &wbase);
__set_bit(14, &rbase);
} else {
__clear_bit(14, &wbase);
__clear_bit(14, &rbase);
}
this->IO_ADDR_W = (void *)wbase;
this->IO_ADDR_R = (void *)rbase;
}
int board_nand_init(struct nand_chip *nand)
{
davinci_nand_init(nand);
nand->select_chip = nand_dm355evm_select_chip;
return 0;
}
#endif
#ifdef CONFIG_DAVINCI_MMC
static struct davinci_mmc mmc_sd0 = {
.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
.input_clk = 108000000,
.host_caps = MMC_MODE_4BIT,
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
.version = MMC_CTLR_VERSION_1,
};
#ifdef CONFIG_DAVINCI_MMC_SD1
static struct davinci_mmc mmc_sd1 = {
.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
.input_clk = 108000000,
.host_caps = MMC_MODE_4BIT,
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
.version = MMC_CTLR_VERSION_1,
};
#endif
int board_mmc_init(bd_t *bis)
{
int err;
/* Add slot-0 to mmc subsystem */
err = davinci_mmc_init(bis, &mmc_sd0);
if (err)
return err;
#ifdef CONFIG_DAVINCI_MMC_SD1
/* Add slot-1 to mmc subsystem */
err = davinci_mmc_init(bis, &mmc_sd1);
#endif
return err;
}
#endif

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@ -1,12 +0,0 @@
if TARGET_DAVINCI_DM355LEOPARD
config SYS_BOARD
default "dm355leopard"
config SYS_VENDOR
default "davinci"
config SYS_CONFIG_NAME
default "davinci_dm355leopard"
endif

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@ -1,6 +0,0 @@
DM355LEOPARD BOARD
#M: Sandeep Paulraj <s-paulraj@ti.com>
S: Orphan (since 2014-08)
F: board/davinci/dm355leopard/
F: include/configs/davinci_dm355leopard.h
F: configs/davinci_dm355leopard_defconfig

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@ -1,10 +0,0 @@
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := dm355leopard.o

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@ -1,6 +0,0 @@
# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
#
#Provide at least 16MB spacing between us and the Linux Kernel image
CONFIG_SYS_TEXT_BASE = 0x81080000

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@ -1,86 +0,0 @@
/*
* Copyright (C) 2009 Texas Instruments Incorporated
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <nand.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/gpio.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/davinci_misc.h>
#include <net.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
struct davinci_gpio *gpio01_base =
(struct davinci_gpio *)DAVINCI_GPIO_BANK01;
struct davinci_gpio *gpio23_base =
(struct davinci_gpio *)DAVINCI_GPIO_BANK23;
struct davinci_gpio *gpio67_base =
(struct davinci_gpio *)DAVINCI_GPIO_BANK67;
gd->bd->bi_arch_number = MACH_TYPE_DM355_LEOPARD;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
/* GIO 9 & 10 are used for IO */
writel((readl(PINMUX3) & 0XF8FFFFFF), PINMUX3);
/* Interrupt set GIO 9 */
writel((readl(DAVINCI_GPIO_BINTEN) | 0x1), DAVINCI_GPIO_BINTEN);
/* set GIO 9 input */
writel((readl(&gpio01_base->dir) | (1 << 9)), &gpio01_base->dir);
/* Both edge trigger GIO 9 */
writel((readl(&gpio01_base->set_rising) | (1 << 9)),
&gpio01_base->set_rising);
writel((readl(&gpio01_base->dir) & ~(1 << 5)), &gpio01_base->dir);
/* output low */
writel((readl(&gpio01_base->set_data) & ~(1 << 5)),
&gpio01_base->set_data);
/* set GIO 10 output */
writel((readl(&gpio01_base->dir) & ~(1 << 10)), &gpio01_base->dir);
/* output high */
writel((readl(&gpio01_base->set_data) | (1 << 10)),
&gpio01_base->set_data);
/* set GIO 32 output */
writel((readl(&gpio23_base->dir) & ~(1 << 0)), &gpio23_base->dir);
/* output High */
writel((readl(&gpio23_base->set_data) | (1 << 0)),
&gpio23_base->set_data);
/* Enable UART1 MUX Lines */
writel((readl(PINMUX0) & ~3), PINMUX0);
writel((readl(&gpio67_base->dir) & ~(1 << 6)), &gpio67_base->dir);
writel((readl(&gpio67_base->set_data) | (1 << 6)),
&gpio67_base->set_data);
return 0;
}
#ifdef CONFIG_DRIVER_DM9000
int board_eth_init(bd_t *bis)
{
return dm9000_initialize(bis);
}
#endif
#ifdef CONFIG_NAND_DAVINCI
int board_nand_init(struct nand_chip *nand)
{
davinci_nand_init(nand);
return 0;
}
#endif

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@ -1,12 +0,0 @@
if TARGET_DAVINCI_DM365EVM
config SYS_BOARD
default "dm365evm"
config SYS_VENDOR
default "davinci"
config SYS_CONFIG_NAME
default "davinci_dm365evm"
endif

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@ -1,6 +0,0 @@
DM365EVM BOARD
#M: Sandeep Paulraj <s-paulraj@ti.com>
S: Orphan (since 2014-08)
F: board/davinci/dm365evm/
F: include/configs/davinci_dm365evm.h
F: configs/davinci_dm365evm_defconfig

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@ -1,10 +0,0 @@
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := dm365evm.o

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@ -1,11 +0,0 @@
#
# Spectrum Digital DM365 EVM board
# DM365 EVM board has 1 bank of 128 MB DDR RAM
# Physical Address: 8000'0000 to 8800'0000
#
# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
#
#Provide at least 16MB spacing between us and the Linux Kernel image
CONFIG_SYS_TEXT_BASE = 0x81080000

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@ -1,139 +0,0 @@
/*
* Copyright (C) 2009 Texas Instruments Incorporated
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <nand.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/gpio.h>
#include <netdev.h>
#include <asm/arch/davinci_misc.h>
#ifdef CONFIG_DAVINCI_MMC
#include <mmc.h>
#include <asm/arch/sdmmc_defs.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM365_EVM;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}
#ifdef CONFIG_DRIVER_TI_EMAC
int board_eth_init(bd_t *bis)
{
uint8_t eeprom_enetaddr[6];
int i;
struct davinci_gpio *gpio1_base =
(struct davinci_gpio *)DAVINCI_GPIO_BANK01;
/* Configure PINMUX 3 to enable EMAC pins */
writel((readl(PINMUX3) | 0x1affff), PINMUX3);
/* Configure GPIO20 as output */
writel((readl(&gpio1_base->dir) & ~(1 << 20)), &gpio1_base->dir);
/* Toggle GPIO 20 */
for (i = 0; i < 20; i++) {
/* GPIO 20 low */
writel((readl(&gpio1_base->out_data) & ~(1 << 20)),
&gpio1_base->out_data);
udelay(1000);
/* GPIO 20 high */
writel((readl(&gpio1_base->out_data) | (1 << 20)),
&gpio1_base->out_data);
}
/* Configure I2C pins so that EEPROM can be read */
writel((readl(PINMUX3) | 0x01400000), PINMUX3);
/* Read Ethernet MAC address from EEPROM */
if (dvevm_read_mac_address(eeprom_enetaddr))
davinci_sync_env_enetaddr(eeprom_enetaddr);
davinci_emac_initialize();
return 0;
}
#endif
#ifdef CONFIG_NAND_DAVINCI
static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip)
{
struct nand_chip *this = mtd->priv;
unsigned long wbase = (unsigned long) this->IO_ADDR_W;
unsigned long rbase = (unsigned long) this->IO_ADDR_R;
if (chip == 1) {
__set_bit(14, &wbase);
__set_bit(14, &rbase);
} else {
__clear_bit(14, &wbase);
__clear_bit(14, &rbase);
}
this->IO_ADDR_W = (void *)wbase;
this->IO_ADDR_R = (void *)rbase;
}
int board_nand_init(struct nand_chip *nand)
{
davinci_nand_init(nand);
nand->select_chip = nand_dm365evm_select_chip;
return 0;
}
#endif
#ifdef CONFIG_DAVINCI_MMC
static struct davinci_mmc mmc_sd0 = {
.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
.input_clk = 121500000,
.host_caps = MMC_MODE_4BIT,
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
.version = MMC_CTLR_VERSION_2,
};
#ifdef CONFIG_DAVINCI_MMC_SD1
static struct davinci_mmc mmc_sd1 = {
.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
.input_clk = 121500000,
.host_caps = MMC_MODE_4BIT,
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
.version = MMC_CTLR_VERSION_2,
};
#endif
int board_mmc_init(bd_t *bis)
{
int err;
/* Add slot-0 to mmc subsystem */
err = davinci_mmc_init(bis, &mmc_sd0);
if (err)
return err;
#ifdef CONFIG_DAVINCI_MMC_SD1
#define PUPDCTL1 0x01c4007c
/* PINMUX(4)-DAT0-3/CMD; PINMUX(0)-CLK */
writel((readl(PINMUX4) | 0x55400000), PINMUX4);
writel((readl(PINMUX0) | 0x00010000), PINMUX0);
/* Configure MMC/SD pins as pullup */
writel((readl(PUPDCTL1) & ~0x07c0), PUPDCTL1);
/* Add slot-1 to mmc subsystem */
err = davinci_mmc_init(bis, &mmc_sd1);
#endif
return err;
}
#endif

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@ -1,12 +0,0 @@
if TARGET_DAVINCI_DM6467EVM
config SYS_BOARD
default "dm6467evm"
config SYS_VENDOR
default "davinci"
config SYS_CONFIG_NAME
default "davinci_dm6467evm"
endif

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@ -1,7 +0,0 @@
DM6467EVM BOARD
#M: Sandeep Paulraj <s-paulraj@ti.com>
S: Orphan (since 2014-08)
F: board/davinci/dm6467evm/
F: include/configs/davinci_dm6467evm.h
F: configs/davinci_dm6467evm_defconfig
F: configs/davinci_dm6467Tevm_defconfig

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@ -1,10 +0,0 @@
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := dm6467evm.o

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@ -1,2 +0,0 @@
#Provide at least 16MB spacing between us and the Linux Kernel image
CONFIG_SYS_TEXT_BASE = 0x81080000

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@ -1,76 +0,0 @@
/*
* Copyright (C) 2009 Texas Instruments Incorporated
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <nand.h>
#include <asm/arch/hardware.h>
#include <asm/ti-common/davinci_nand.h>
DECLARE_GLOBAL_DATA_PTR;
#define REV_DM6467EVM 0
#define REV_DM6467TEVM 1
/*
* get_board_rev() - setup to pass kernel board revision information
* Returns:
* bit[0-3] System clock frequency
* 0000b - 27 MHz
* 0001b - 33 MHz
*/
u32 get_board_rev(void)
{
#ifdef CONFIG_DAVINCI_DM6467TEVM
return REV_DM6467TEVM;
#else
return REV_DM6467EVM;
#endif
}
int board_init(void)
{
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM6467_EVM;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
lpsc_on(DAVINCI_DM646X_LPSC_TIMER0);
lpsc_on(DAVINCI_DM646X_LPSC_UART0);
lpsc_on(DAVINCI_DM646X_LPSC_I2C);
lpsc_on(DAVINCI_DM646X_LPSC_EMAC);
/* Enable GIO3.3V cells used for EMAC */
REG(VDD3P3V_PWDN) = 0x80000c0;
/* Select UART function on UART0 */
REG(PINMUX0) &= ~(0x0000003f << 18);
REG(PINMUX1) &= ~(0x00000003);
return 0;
}
#if defined(CONFIG_DRIVER_TI_EMAC)
int board_eth_init(bd_t *bis)
{
if (!davinci_emac_initialize()) {
printf("Error: Ethernet init failed!\n");
return -1;
}
return 0;
}
#endif /* CONFIG_DRIVER_TI_EMAC */
#ifdef CONFIG_NAND_DAVINCI
int board_nand_init(struct nand_chip *nand)
{
davinci_nand_init(nand);
return 0;
}
#endif

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@ -1,12 +0,0 @@
if TARGET_DAVINCI_DVEVM
config SYS_BOARD
default "dvevm"
config SYS_VENDOR
default "davinci"
config SYS_CONFIG_NAME
default "davinci_dvevm"
endif

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@ -1,6 +0,0 @@
DVEVM BOARD
#M: -
S: Maintained
F: board/davinci/dvevm/
F: include/configs/davinci_dvevm.h
F: configs/davinci_dvevm_defconfig

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@ -1,11 +0,0 @@
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := dvevm.o
obj-y += board_init.o

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@ -1,16 +0,0 @@
/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Board-specific low level initialization code. Called at the very end
* of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
* initialization required.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
.globl dv_board_init
dv_board_init:
mov pc, lr

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@ -1,39 +0,0 @@
#
# (C) Copyright 2002
# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
#
# (C) Copyright 2003
# Texas Instruments, <www.ti.com>
# Swaminathan <swami.iyer@ti.com>
#
# Davinci EVM board (ARM925EJS) cpu
# see http://www.ti.com/ for more information on Texas Instruments
#
# Davinci EVM has 1 bank of 256 MB DDR RAM
# Physical Address:
# 8000'0000 to 9000'0000
#
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
#
# Visioneering Corp. Sonata board (ARM926EJS) cpu
#
# Sonata board has 1 bank of 128 MB DDR RAM
# Physical Address:
# 8000'0000 to 8800'0000
#
# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
#
# Schmoogie board has 1 bank of 128 MB DDR RAM
# Physical Address:
# 8000'0000 to 8800'0000
#
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
#
# we load ourself to 8108 '0000
#
#
#Provide at least 16MB spacing between us and the Linux Kernel image
CONFIG_SYS_TEXT_BASE = 0x81080000

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@ -1,91 +0,0 @@
/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Parts are shamelessly stolen from various TI sources, original copyright
* follows:
* -----------------------------------------------------------------
*
* Copyright (C) 2004 Texas Instruments.
*
* ----------------------------------------------------------------------------
* SPDX-License-Identifier: GPL-2.0+
* ----------------------------------------------------------------------------
*/
#include <common.h>
#include <i2c.h>
#include <asm/arch/hardware.h>
#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM;
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
/* Configure AEMIF pins (although this should be configured at boot time
* with pull-up/pull-down resistors) */
REG(PINMUX0) = 0x00000c1f;
davinci_errata_workarounds();
/* Power on required peripherals */
lpsc_on(DAVINCI_LPSC_GPIO);
lpsc_on(DAVINCI_LPSC_USB);
#if !defined(CONFIG_SYS_USE_DSPLINK)
/* Powerup the DSP */
dsp_on();
#endif /* CONFIG_SYS_USE_DSPLINK */
davinci_enable_uart0();
davinci_enable_emac();
davinci_enable_i2c();
lpsc_on(DAVINCI_LPSC_TIMER1);
timer_init();
return(0);
}
int misc_init_r(void)
{
uint8_t video_mode;
uint8_t eeprom_enetaddr[6];
/* Read Ethernet MAC address from EEPROM if available. */
if (dvevm_read_mac_address(eeprom_enetaddr))
davinci_sync_env_enetaddr(eeprom_enetaddr);
i2c_read(0x39, 0x00, 1, &video_mode, 1);
setenv("videostd", ((video_mode & 0x80) ? "pal" : "ntsc"));
return(0);
}
#ifdef CONFIG_USB_DAVINCI
/* IO Expander I2C address and USB VBUS enable mask */
#define IOEXP_I2C_ADDR 0x3A
#define IOEXP_VBUSEN_MASK 1
/*
* This function enables USB VBUS by writting to IO expander using I2C.
* Note that the I2C is already initialized at this stage. This
* function is used by davinci specific USB wrapper code.
*/
void enable_vbus(void)
{
uchar data; /* IO Expander data to enable VBUS */
/* Write to IO expander to enable VBUS */
i2c_read(IOEXP_I2C_ADDR, 0, 0, &data, 1);
data &= ~IOEXP_VBUSEN_MASK;
i2c_write(IOEXP_I2C_ADDR, 0, 0, &data, 1);
}
#endif

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@ -1,12 +0,0 @@
if TARGET_DAVINCI_SCHMOOGIE
config SYS_BOARD
default "schmoogie"
config SYS_VENDOR
default "davinci"
config SYS_CONFIG_NAME
default "davinci_schmoogie"
endif

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@ -1,6 +0,0 @@
SCHMOOGIE BOARD
#M: -
S: Maintained
F: board/davinci/schmoogie/
F: include/configs/davinci_schmoogie.h
F: configs/davinci_schmoogie_defconfig

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@ -1,11 +0,0 @@
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := schmoogie.o
obj-y += board_init.o

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@ -1,16 +0,0 @@
/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Board-specific low level initialization code. Called at the very end
* of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
* initialization required.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
.globl dv_board_init
dv_board_init:
mov pc, lr

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@ -1,39 +0,0 @@
#
# (C) Copyright 2002
# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
#
# (C) Copyright 2003
# Texas Instruments, <www.ti.com>
# Swaminathan <swami.iyer@ti.com>
#
# Davinci EVM board (ARM925EJS) cpu
# see http://www.ti.com/ for more information on Texas Instruments
#
# Davinci EVM has 1 bank of 256 MB DDR RAM
# Physical Address:
# 8000'0000 to 9000'0000
#
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
#
# Visioneering Corp. Sonata board (ARM926EJS) cpu
#
# Sonata board has 1 bank of 128 MB DDR RAM
# Physical Address:
# 8000'0000 to 8800'0000
#
# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
#
# Schmoogie board has 1 bank of 128 MB DDR RAM
# Physical Address:
# 8000'0000 to 8800'0000
#
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
#
# we load ourself to 8108 '0000
#
#
#Provide at least 16MB spacing between us and the Linux Kernel image
CONFIG_SYS_TEXT_BASE = 0x81080000

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@ -1,119 +0,0 @@
/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Parts are shamelessly stolen from various TI sources, original copyright
* follows:
* -----------------------------------------------------------------
*
* Copyright (C) 2004 Texas Instruments.
*
* ----------------------------------------------------------------------------
* SPDX-License-Identifier: GPL-2.0+
* ----------------------------------------------------------------------------
*/
#include <common.h>
#include <i2c.h>
#include <asm/arch/hardware.h>
#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
/* Configure AEMIF pins (although this should be configured at boot time
* with pull-up/pull-down resistors) */
REG(PINMUX0) = 0x00000c1f;
davinci_errata_workarounds();
/* Power on required peripherals */
lpsc_on(DAVINCI_LPSC_GPIO);
#if !defined(CONFIG_SYS_USE_DSPLINK)
/* Powerup the DSP */
dsp_on();
#endif /* CONFIG_SYS_USE_DSPLINK */
davinci_enable_uart0();
davinci_enable_emac();
davinci_enable_i2c();
lpsc_on(DAVINCI_LPSC_TIMER1);
timer_init();
return(0);
}
int misc_init_r(void)
{
u_int8_t tmp[20], buf[10];
int i = 0;
/* Set serial number from UID chip */
const u_int8_t crc_tbl[256] = {
0x00, 0x5e, 0xbc, 0xe2, 0x61, 0x3f, 0xdd, 0x83,
0xc2, 0x9c, 0x7e, 0x20, 0xa3, 0xfd, 0x1f, 0x41,
0x9d, 0xc3, 0x21, 0x7f, 0xfc, 0xa2, 0x40, 0x1e,
0x5f, 0x01, 0xe3, 0xbd, 0x3e, 0x60, 0x82, 0xdc,
0x23, 0x7d, 0x9f, 0xc1, 0x42, 0x1c, 0xfe, 0xa0,
0xe1, 0xbf, 0x5d, 0x03, 0x80, 0xde, 0x3c, 0x62,
0xbe, 0xe0, 0x02, 0x5c, 0xdf, 0x81, 0x63, 0x3d,
0x7c, 0x22, 0xc0, 0x9e, 0x1d, 0x43, 0xa1, 0xff,
0x46, 0x18, 0xfa, 0xa4, 0x27, 0x79, 0x9b, 0xc5,
0x84, 0xda, 0x38, 0x66, 0xe5, 0xbb, 0x59, 0x07,
0xdb, 0x85, 0x67, 0x39, 0xba, 0xe4, 0x06, 0x58,
0x19, 0x47, 0xa5, 0xfb, 0x78, 0x26, 0xc4, 0x9a,
0x65, 0x3b, 0xd9, 0x87, 0x04, 0x5a, 0xb8, 0xe6,
0xa7, 0xf9, 0x1b, 0x45, 0xc6, 0x98, 0x7a, 0x24,
0xf8, 0xa6, 0x44, 0x1a, 0x99, 0xc7, 0x25, 0x7b,
0x3a, 0x64, 0x86, 0xd8, 0x5b, 0x05, 0xe7, 0xb9,
0x8c, 0xd2, 0x30, 0x6e, 0xed, 0xb3, 0x51, 0x0f,
0x4e, 0x10, 0xf2, 0xac, 0x2f, 0x71, 0x93, 0xcd,
0x11, 0x4f, 0xad, 0xf3, 0x70, 0x2e, 0xcc, 0x92,
0xd3, 0x8d, 0x6f, 0x31, 0xb2, 0xec, 0x0e, 0x50,
0xaf, 0xf1, 0x13, 0x4d, 0xce, 0x90, 0x72, 0x2c,
0x6d, 0x33, 0xd1, 0x8f, 0x0c, 0x52, 0xb0, 0xee,
0x32, 0x6c, 0x8e, 0xd0, 0x53, 0x0d, 0xef, 0xb1,
0xf0, 0xae, 0x4c, 0x12, 0x91, 0xcf, 0x2d, 0x73,
0xca, 0x94, 0x76, 0x28, 0xab, 0xf5, 0x17, 0x49,
0x08, 0x56, 0xb4, 0xea, 0x69, 0x37, 0xd5, 0x8b,
0x57, 0x09, 0xeb, 0xb5, 0x36, 0x68, 0x8a, 0xd4,
0x95, 0xcb, 0x29, 0x77, 0xf4, 0xaa, 0x48, 0x16,
0xe9, 0xb7, 0x55, 0x0b, 0x88, 0xd6, 0x34, 0x6a,
0x2b, 0x75, 0x97, 0xc9, 0x4a, 0x14, 0xf6, 0xa8,
0x74, 0x2a, 0xc8, 0x96, 0x15, 0x4b, 0xa9, 0xf7,
0xb6, 0xe8, 0x0a, 0x54, 0xd7, 0x89, 0x6b, 0x35
};
/* Set serial number from UID chip */
if (i2c_read(CONFIG_SYS_UID_ADDR, 0, 1, buf, 8)) {
printf("\nUID @ 0x%02x read FAILED!!!\n", CONFIG_SYS_UID_ADDR);
setenv("serial#", "FAILED");
} else {
if (buf[0] != 0x70) {
/* Device Family Code */
printf("\nUID @ 0x%02x read FAILED!!!\n", CONFIG_SYS_UID_ADDR);
setenv("serial#", "FAILED");
}
}
/* Now check CRC */
tmp[0] = 0;
for (i = 0; i < 8; i++)
tmp[0] = crc_tbl[tmp[0] ^ buf[i]];
if (tmp[0] != 0) {
printf("\nUID @ 0x%02x - BAD CRC!!!\n", CONFIG_SYS_UID_ADDR);
setenv("serial#", "FAILED");
} else {
/* CRC OK, set "serial" env variable */
sprintf((char *)&tmp[0], "%02x%02x%02x%02x%02x%02x",
buf[6], buf[5], buf[4], buf[3], buf[2], buf[1]);
setenv("serial#", (char *)&tmp[0]);
}
return(0);
}

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@ -1,12 +0,0 @@
if TARGET_DAVINCI_SFFSDR
config SYS_BOARD
default "sffsdr"
config SYS_VENDOR
default "davinci"
config SYS_CONFIG_NAME
default "davinci_sffsdr"
endif

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@ -1,6 +0,0 @@
SFFSDR BOARD
#M: -
S: Maintained
F: board/davinci/sffsdr/
F: include/configs/davinci_sffsdr.h
F: configs/davinci_sffsdr_defconfig

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@ -1,11 +0,0 @@
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := sffsdr.o
obj-y += board_init.o

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@ -1,16 +0,0 @@
/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Board-specific low level initialization code. Called at the very end
* of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
* initialization required.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
.globl dv_board_init
dv_board_init:
mov pc, lr

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@ -1,23 +0,0 @@
#
# (C) Copyright 2002
# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
#
# Copyright (C) 2008 Lyrtech <www.lyrtech.com>
# Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
#
# Lyrtech SFF SDR board (ARM926EJS) cpu
#
# SFF SDR board has 1 bank of 128 MB DDR RAM
# Physical Address:
# 8000'0000 to 87FF'FFFF
#
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
#
# Integrity kernel is expected to be at 8000'0000, entry 8000'00D0,
# up to 81FF'FFFF (uses up to 32 MB of memory for text, heap, etc).
#
# we load ourself to 8400'0000 to provide at least 32MB spacing
# between us and the Integrity kernel image
CONFIG_SYS_TEXT_BASE = 0x84000000

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@ -1,132 +0,0 @@
/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Copyright (C) 2008 Lyrtech <www.lyrtech.com>
* Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
*
* Parts are shamelessly stolen from various TI sources, original copyright
* follows:
*
* Copyright (C) 2004 Texas Instruments.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <asm/arch/hardware.h>
#include <asm/arch/davinci_misc.h>
#define DAVINCI_A3CR (0x01E00014) /* EMIF-A CS3 config register. */
#define DAVINCI_A3CR_VAL (0x3FFFFFFD) /* EMIF-A CS3 value for FPGA. */
#define INTEGRITY_SYSCFG_OFFSET 0x7E8
#define INTEGRITY_CHECKWORD_OFFSET 0x7F8
#define INTEGRITY_CHECKWORD_VALUE 0x10ADBEEF
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
/* arch number of the board */
gd->bd->bi_arch_number = MACH_TYPE_SFFSDR;
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
davinci_errata_workarounds();
/* Power on required peripherals */
lpsc_on(DAVINCI_LPSC_GPIO);
#if !defined(CONFIG_SYS_USE_DSPLINK)
/* Powerup the DSP */
dsp_on();
#endif /* CONFIG_SYS_USE_DSPLINK */
davinci_enable_uart0();
davinci_enable_emac();
davinci_enable_i2c();
lpsc_on(DAVINCI_LPSC_TIMER1);
timer_init();
return(0);
}
/* Read ethernet MAC address from Integrity data structure inside EEPROM.
* Returns 1 if found, 0 otherwise.
*/
static int sffsdr_read_mac_address(uint8_t *buf)
{
u_int32_t value, mac[2], address;
/* Read Integrity data structure checkword. */
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_CHECKWORD_OFFSET,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
goto err;
if (value != INTEGRITY_CHECKWORD_VALUE)
return 0;
/* Read SYSCFG structure offset. */
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_SYSCFG_OFFSET,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
goto err;
address = 0x800 + (int) value; /* Address of SYSCFG structure. */
/* Read NET CONFIG structure offset. */
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
goto err;
address = 0x800 + (int) value; /* Address of NET CONFIG structure. */
address += 12; /* Address of NET INTERFACE CONFIG structure. */
/* Read NET INTERFACE CONFIG 2 structure offset. */
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
goto err;
address = 0x800 + 16 + (int) value; /* Address of NET INTERFACE
* CONFIG 2 structure. */
/* Read MAC address. */
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &mac[0], 8))
goto err;
buf[0] = mac[0] >> 24;
buf[1] = mac[0] >> 16;
buf[2] = mac[0] >> 8;
buf[3] = mac[0];
buf[4] = mac[1] >> 24;
buf[5] = mac[1] >> 16;
return 1; /* Found */
err:
printf("Read from EEPROM @ 0x%02x failed\n", CONFIG_SYS_I2C_EEPROM_ADDR);
return 0;
}
/* Platform dependent initialisation. */
int misc_init_r(void)
{
uint8_t i2cbuf;
uint8_t eeprom_enetaddr[6];
/* EMIF-A CS3 configuration for FPGA. */
REG(DAVINCI_A3CR) = DAVINCI_A3CR_VAL;
/* Configure I2C switch (PCA9543) to enable channel 0. */
i2cbuf = CONFIG_SYS_I2C_PCA9543_ENABLE_CH0;
if (i2c_write(CONFIG_SYS_I2C_PCA9543_ADDR, 0,
CONFIG_SYS_I2C_PCA9543_ADDR_LEN, &i2cbuf, 1)) {
printf("Write to MUX @ 0x%02x failed\n", CONFIG_SYS_I2C_PCA9543_ADDR);
return 1;
}
/* Read Ethernet MAC address from EEPROM if available. */
if (sffsdr_read_mac_address(eeprom_enetaddr))
davinci_sync_env_enetaddr(eeprom_enetaddr);
return(0);
}

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@ -1,12 +0,0 @@
if TARGET_DAVINCI_SONATA
config SYS_BOARD
default "sonata"
config SYS_VENDOR
default "davinci"
config SYS_CONFIG_NAME
default "davinci_sonata"
endif

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@ -1,6 +0,0 @@
SONATA BOARD
#M: -
S: Maintained
F: board/davinci/sonata/
F: include/configs/davinci_sonata.h
F: configs/davinci_sonata_defconfig

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@ -1,11 +0,0 @@
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := sonata.o
obj-y += board_init.o

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@ -1,87 +0,0 @@
/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Board-specific low level initialization code. Called at the very end
* of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
* initialization required.
*
* For _OLDER_ Sonata boards sets up GPIO4 to control NAND WP line. Newer
* Sonata boards, AFAIK, don't use this so it's just return by default. Ask
* Visioneering if they reinvented the wheel once again to make sure :)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
.globl dv_board_init
dv_board_init:
#ifdef SONATA_BOARD_GPIOWP
/* Set PINMUX0 to enable GPIO4 */
ldr r0, _PINMUX0
ldr r1, GPIO4_EN_MASK
ldr r2, [r0]
and r2, r2, r1
str r2, [r0]
/* Enable GPIO LPSC module */
ldr r0, PTSTAT
gpio_ptstat_loop1:
ldr r2, [r0]
tst r2, $0x00000001
bne gpio_ptstat_loop1
ldr r1, MDCTL_GPIO
ldr r2, [r1]
and r2, r2, $0xfffffff8
orr r2, r2, $0x00000003
str r2, [r1]
orr r2, r2, $0x00000200
str r2, [r1]
ldr r1, PTCMD
mov r2, $0x00000001
str r2, [r1]
gpio_ptstat_loop2:
ldr r2, [r0]
tst r2, $0x00000001
bne gpio_ptstat_loop2
ldr r0, MDSTAT_GPIO
gpio_mdstat_loop:
ldr r2, [r0]
and r2, r2, $0x0000001f
teq r2, $0x00000003
bne gpio_mdstat_loop
/* GPIO4 -> output */
ldr r0, GPIO_DIR01
mov r1, $0x10
ldr r2, [r0]
bic r2, r2, r0
str r2, [r0]
/* Set it to 0 (Write Protect) */
ldr r0, GPIO_CLR_DATA01
str r1, [r0]
#endif
mov pc, lr
#ifdef SONATA_BOARD_GPIOWP
.ltorg
GPIO4_EN_MASK:
.word 0xf77fffff
MDCTL_GPIO:
.word 0x01c41a68
MDSTAT_GPIO:
.word 0x01c41868
GPIO_DIR01:
.word 0x01c67010
GPIO_CLR_DATA01:
.word 0x01c6701c
#endif

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@ -1,39 +0,0 @@
#
# (C) Copyright 2002
# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
#
# (C) Copyright 2003
# Texas Instruments, <www.ti.com>
# Swaminathan <swami.iyer@ti.com>
#
# Davinci EVM board (ARM925EJS) cpu
# see http://www.ti.com/ for more information on Texas Instruments
#
# Davinci EVM has 1 bank of 256 MB DDR RAM
# Physical Address:
# 8000'0000 to 9000'0000
#
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
#
# Visioneering Corp. Sonata board (ARM926EJS) cpu
#
# Sonata board has 1 bank of 128 MB DDR RAM
# Physical Address:
# 8000'0000 to 8800'0000
#
# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
#
# Schmoogie board has 1 bank of 128 MB DDR RAM
# Physical Address:
# 8000'0000 to 8800'0000
#
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
#
# we load ourself to 8108 '0000
#
#
#Provide at least 16MB spacing between us and the Linux Kernel image
CONFIG_SYS_TEXT_BASE = 0x81080000

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@ -1,87 +0,0 @@
/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Parts are shamelessly stolen from various TI sources, original copyright
* follows:
* -----------------------------------------------------------------
*
* Copyright (C) 2004 Texas Instruments.
*
* ----------------------------------------------------------------------------
* SPDX-License-Identifier: GPL-2.0+
* ----------------------------------------------------------------------------
*/
#include <common.h>
#include <nand.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/hardware.h>
#include <asm/arch/davinci_misc.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
/* Configure AEMIF pins (although this should be configured at boot time
* with pull-up/pull-down resistors) */
REG(PINMUX0) = 0x00000c1f;
davinci_errata_workarounds();
/* Power on required peripherals */
lpsc_on(DAVINCI_LPSC_GPIO);
#if !defined(CONFIG_SYS_USE_DSPLINK)
/* Powerup the DSP */
dsp_on();
#endif /* CONFIG_SYS_USE_DSPLINK */
davinci_enable_uart0();
davinci_enable_emac();
davinci_enable_i2c();
lpsc_on(DAVINCI_LPSC_TIMER1);
timer_init();
return(0);
}
int misc_init_r(void)
{
uint8_t eeprom_enetaddr[6];
/* Read Ethernet MAC address from EEPROM if available. */
if (dvevm_read_mac_address(eeprom_enetaddr))
davinci_sync_env_enetaddr(eeprom_enetaddr);
return(0);
}
#ifdef CONFIG_NAND_DAVINCI
/* Set WP on deselect, write enable on select */
static void nand_sonata_select_chip(struct mtd_info *mtd, int chip)
{
#define GPIO_SET_DATA01 0x01c67018
#define GPIO_CLR_DATA01 0x01c6701c
#define GPIO_NAND_WP (1 << 4)
#ifdef SONATA_BOARD_GPIOWP
if (chip < 0) {
REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP;
} else {
REG(GPIO_SET_DATA01) |= GPIO_NAND_WP;
}
#endif
}
int board_nand_init(struct nand_chip *nand)
{
davinci_nand_init(nand);
nand->select_chip = nand_sonata_select_chip;
return 0;
}
#endif /* CONFIG_NAND_DAVINCI */

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@ -1,9 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_DM355EVM=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="DM355 EVM # "

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@ -1,9 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_DM355LEOPARD=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="DM355 LEOPARD # "

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@ -1,9 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_DM365EVM=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="DM36x EVM # "

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@ -1,9 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_DM6467EVM=y
CONFIG_SYS_EXTRA_OPTIONS="DAVINCI_DM6467TEVM,REFCLK_FREQ=33000000"
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set

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CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_DM6467EVM=y
CONFIG_SYS_EXTRA_OPTIONS="REFCLK_FREQ=27000000"
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="DM6467 EVM > "

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@ -1,9 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_DVEVM=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="U-Boot > "

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@ -1,9 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_SCHMOOGIE=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="U-Boot > "

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@ -1,9 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_SFFSDR=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="U-Boot > "

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@ -1,7 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_DAVINCI_SONATA=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_PROMPT="U-Boot > "

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@ -1,195 +0,0 @@
/*
* Copyright (C) 2009 David Brownell
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* Spectrum Digital TMS320DM355 EVM board */
#define DAVINCI_DM355EVM
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/* SoC Configuration */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
#define CONFIG_SOC_DM355
/* Memory Info */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */
/* Serial Driver info: UART0 for console */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM1 0x01c20000
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
/* Ethernet: external DM9000 */
#define CONFIG_DRIVER_DM9000 1
#define CONFIG_DM9000_BASE 0x04014000
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
/* NAND: socketed, two chipselects, normally 2 GBytes */
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_CS 2
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
/* socket has two chipselects, nCE0 gated by address BIT(14) */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 2
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DAVINCI_MMC
#define CONFIG_DAVINCI_MMC_SD1
#define CONFIG_MMC_MBLOCK
/* USB: OTG connector */
/* NYET -- #define CONFIG_USB_DAVINCI */
/* U-Boot command configuration */
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#endif
#ifdef CONFIG_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_MMC
#endif
#ifdef CONFIG_NAND_DAVINCI
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_NAND
#define CONFIG_CMD_UBI
#define CONFIG_RBTREE
#endif
#ifdef CONFIG_USB_DAVINCI
#define CONFIG_USB_MUSB_HCD
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#else
#undef CONFIG_USB_MUSB_HCD
#undef CONFIG_CMD_USB
#undef CONFIG_USB_STORAGE
#endif
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
/* U-Boot general configuration */
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_LONGHELP
#ifdef CONFIG_NAND_DAVINCI
#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x3C0000
#undef CONFIG_ENV_IS_IN_FLASH
#endif
#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
#define CONFIG_CMD_ENV
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
#define CONFIG_ENV_IS_IN_MMC
#undef CONFIG_ENV_IS_IN_FLASH
#endif
#define CONFIG_BOOTDELAY 5
#define CONFIG_BOOTCOMMAND \
"dhcp;bootm"
#define CONFIG_BOOTARGS \
"console=ttyS0,115200n8 " \
"root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
#define CONFIG_CMDLINE_EDITING
#define CONFIG_VERSION_VARIABLE
#define CONFIG_TIMESTAMP
#define CONFIG_NET_RETRY_COUNT 10
/* U-Boot memory configuration */
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
/* Linux interfacing */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
/* NAND configuration ... socketed with two chipselects. It normally comes
* with a 2GByte SLC part with 2KB pages (and 128KB erase blocks); other
* 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC. (MLC
* pretty much demands the 4-bit ECC support.) You can of course swap in
* other parts, including small page ones.
*
* This presents a single read-only partition for all bootloader stuff.
* UBL (1+ block), U-Boot (256KB+), U-Boot environment (one block), and
* some extra space to help cope with bad blocks in that data. Linux
* shouldn't care about its detailed layout, and will probably want to use
* UBI/UBFS for the rest (except maybe on smallpage chips). It's easy to
* override this default partitioning using MTDPARTS and cmdlinepart.
*/
#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
#ifdef CONFIG_SYS_NAND_LARGEPAGE
/* Use same layout for 128K/256K blocks; allow some bad blocks */
#define PART_BOOT "2m(bootloader)ro,"
#else
/* Assume 16K erase blocks; allow a few bad ones. */
#define PART_BOOT "512k(bootloader)ro,"
#endif
#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
#define PART_REST "-(filesystem)"
#define MTDPARTS_DEFAULT \
"mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */

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@ -1,140 +0,0 @@
/*
* Copyright (C) 2009 Texas Instruments Incorporated
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define DAVINCI_DM355LEOPARD
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/* SoC Configuration */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
#define CONFIG_SOC_DM355 /* DM355 based board */
/* Memory Info */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */
/* Serial Driver info: UART0 for console */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM1 0x01c20000
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
/* Ethernet: external DM9000 */
#define CONFIG_DRIVER_DM9000 1
#define CONFIG_DM9000_BASE 0x04000000
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE + 16)
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10
/* NAND */
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_CS 2
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* U-Boot command configuration */
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#endif
#ifdef CONFIG_NAND_DAVINCI
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_NAND
#define CONFIG_CMD_UBI
#define CONFIG_RBTREE
#endif
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
/* U-Boot general configuration */
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_LONGHELP
#ifdef CONFIG_NAND_DAVINCI
#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x3C0000
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE
#endif
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTCOMMAND "dhcp;bootm"
#define CONFIG_BOOTARGS \
"console=ttyS0,115200n8 " \
"root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
#define CONFIG_CMDLINE_EDITING
#define CONFIG_VERSION_VARIABLE
#define CONFIG_TIMESTAMP
#define CONFIG_NET_RETRY_COUNT 10
/* U-Boot memory configuration */
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
/* Linux interfacing */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
#ifdef CONFIG_SYS_NAND_LARGEPAGE
#define PART_BOOT "2m(bootloader)ro,"
#else
/* Assume 16K erase blocks; allow a few bad ones. */
#define PART_BOOT "512k(bootloader)ro,"
#endif
#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
#define PART_REST "-(filesystem)"
#define MTDPARTS_DEFAULT \
"mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */

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/*
* Copyright (C) 2009 Texas Instruments Incorporated
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* Spectrum Digital TMS320DM365 EVM board */
#define DAVINCI_DM365EVM
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/* SoC Configuration */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
#define CONFIG_SOC_DM365
/* Memory Info */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */
/* Serial Driver info: UART0 for console */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM1 0x01c20000
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
/* EEPROM definitions for EEPROM on DM365 EVM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
/* Network Configuration */
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
/* NAND: socketed, two chipselects, normally 2 GBytes */
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_CS 2
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
/* socket has two chipselects, nCE0 gated by address BIT(14) */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 2
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DAVINCI_MMC
#define CONFIG_DAVINCI_MMC_SD1
#define CONFIG_MMC_MBLOCK
#define PINMUX4_USBDRVBUS_BITCLEAR 0x3000
#define PINMUX4_USBDRVBUS_BITSET 0x2000
/* USB Configuration */
#define CONFIG_USB_DAVINCI
#define CONFIG_USB_MUSB_HCD
#ifdef CONFIG_USB_DAVINCI
#define CONFIG_CMD_USB /* include support for usb */
#define CONFIG_CMD_STORAGE /* include support for usb */
#define CONFIG_CMD_FAT /* include support for FAT/storage*/
#define CONFIG_DOS_PARTITION /* include support for FAT/storage*/
#endif
#ifdef CONFIG_USB_MUSB_HCD /* include support for usb host */
#define CONFIG_CMD_USB /* include support for usb cmd */
#define CONFIG_USB_STORAGE /* MSC class support */
#define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */
#define CONFIG_CMD_FAT /* inclue support for FAT/storage */
#define CONFIG_DOS_PARTITION /* inclue support for FAT/storage */
#ifdef CONFIG_USB_KEYBOARD /* HID class support */
#define CONFIG_SYS_USB_EVENT_POLL
#define CONFIG_PREBOOT "usb start"
#endif /* CONFIG_USB_KEYBOARD */
#endif /* CONFIG_USB_MUSB_HCD */
#ifdef CONFIG_USB_MUSB_UDC
#define CONFIG_USB_DEVICE 1
#define CONFIG_USB_TTY 1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
#define CONFIG_USBD_VENDORID 0x0451
#define CONFIG_USBD_PRODUCTID 0x5678
#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
#define CONFIG_USBD_PRODUCT_NAME "DM365VM"
#endif /* CONFIG_USB_MUSB_UDC */
/* U-Boot command configuration */
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#endif
#ifdef CONFIG_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_MMC
#endif
#ifdef CONFIG_NAND_DAVINCI
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_NAND
#define CONFIG_CMD_UBI
#define CONFIG_RBTREE
#endif
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
/* U-Boot general configuration */
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_LONGHELP
#ifdef CONFIG_NAND_DAVINCI
#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x3C0000
#undef CONFIG_ENV_IS_IN_FLASH
#endif
#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
#define CONFIG_CMD_ENV
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
#define CONFIG_ENV_IS_IN_MMC
#undef CONFIG_ENV_IS_IN_FLASH
#endif
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTCOMMAND \
"dhcp;bootm"
#define CONFIG_BOOTARGS \
"console=ttyS0,115200n8 " \
"root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
#define CONFIG_CMDLINE_EDITING
#define CONFIG_VERSION_VARIABLE
#define CONFIG_TIMESTAMP
/* U-Boot memory configuration */
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
/* Linux interfacing */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
/* NAND configuration issocketed with two chipselects just like the DM355 EVM.
* It normally comes with a 2GByte SLC part with 2KB pages
* (and 128KB erase blocks); other
* 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC. (MLC
* pretty much demands the 4-bit ECC support.) You can of course swap in
* other parts, including small page ones.
*/
#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
#ifdef CONFIG_SYS_NAND_LARGEPAGE
/* Use same layout for 128K/256K blocks; allow some bad blocks */
#define PART_BOOT "2m(bootloader)ro,"
#else
/* Assume 16K erase blocks; allow a few bad ones. */
#define PART_BOOT "512k(bootloader)ro,"
#endif
#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
#define PART_REST "-(filesystem)"
#define MTDPARTS_DEFAULT \
"mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */

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/*
* Copyright (C) 2009 Texas Instruments Incorporated
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* Spectrum Digital TMS320DM6467 EVM board */
#define DAVINCI_DM6467EVM
#define CONFIG_SYS_USE_NAND
#define CONFIG_SYS_NAND_SMALLPAGE
#define CONFIG_SKIP_LOWLEVEL_INIT
/* SoC Configuration */
/* Clock rates detection */
#ifndef __ASSEMBLY__
extern unsigned int davinci_arm_clk_get(void);
#endif
/* Arm Clock frequency */
#define CONFIG_SYS_CLK_FREQ davinci_arm_clk_get()
/* Timer Input clock freq */
#define CONFIG_SYS_HZ_CLOCK (CONFIG_SYS_CLK_FREQ/2)
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SOC_DM646X
/* EEPROM definitions for EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
/* Memory Info */
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE (256 << 20) /* DDR size 256MB */
/* Linux interfacing */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SYS_BARGSIZE 1024 /* Bootarg Size */
#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
#define CONFIG_REVISION_TAG
/* Serial Driver info */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 4
#define CONFIG_SYS_NS16550_COM1 0x01c20000
#define CONFIG_SYS_NS16550_CLK 24000000
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
/* I2C Configuration */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10
/* Network & Ethernet Configuration */
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
/* Flash & Environment */
#define CONFIG_SYS_NO_FLASH
#ifdef CONFIG_SYS_USE_NAND
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_MASK_CLE 0x80000
#define CONFIG_SYS_NAND_MASK_ALE 0x40000
#define CONFIG_SYS_NAND_CS 2
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
#define CONFIG_SYS_NAND_BASE_LIST {0x42000000, }
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_ENV_OFFSET 0
#else
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (4 << 10) /* 4 KiB */
#endif
/* U-Boot general configuration */
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_VERSION_VARIABLE
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
#define CONFIG_BOOTCOMMAND "source 0x82080000; dhcp; bootm"
#define CONFIG_BOOTARGS \
"mem=120M console=ttyS0,115200n8 " \
"root=/dev/hda1 rw noinitrd ip=dhcp"
/* U-Boot commands */
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#ifdef CONFIG_SYS_USE_NAND
#define CONFIG_CMD_NAND
#endif
#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#endif
#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */

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@ -1,216 +0,0 @@
/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* Define this to make U-Boot skip low level initialization when loaded
* by initial bootloader. Not required by NAND U-Boot version but IS
* required for a NOR version used to burn the real NOR U-Boot into
* NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
* so it is NOT possible to build a U-Boot with both NAND and NOR routines.
* NOR U-Boot is loaded directly from Flash so it must perform all the
* low level initialization itself. NAND version is loaded by an initial
* bootloader (UBL in TI-ese) that performs such an initialization so it's
* skipped in NAND version. The third DaVinci boot mode loads a bootloader
* via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
* performing low level init prior to loading. All that means we can NOT use
* NAND version to put U-Boot into NOR because it doesn't have NOR support and
* we can NOT use NOR version because it performs low level initialization
* effectively destroying itself in DDR memory. That's why a separate NOR
* version with this define is needed. It is loaded via UART, then one uses
* it to somehow download a proper NOR version built WITHOUT this define to
* RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
* NOR support into the initial bootloader so it won't be needed but DaVinci
* static RAM might be too small for this (I have something like 2Kbytes left
* as of now, without NOR support) so this might've not happened...
*
#define CONFIG_NOR_UART_BOOT
*/
/*=======*/
/* Board */
/*=======*/
#define DV_EVM
#define CONFIG_SYS_NAND_SMALLPAGE
#define CONFIG_SYS_USE_NAND
/*===================*/
/* SoC Configuration */
/*===================*/
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SOC_DM644X
/*====================================================*/
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
/*====================================================*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
/*=============*/
/* Memory Info */
/*=============*/
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */
#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x10000000 /* DDR size 256MB */
#define DDR_8BANKS /* 8-bank DDR2 (256MB) */
/*====================*/
/* Serial Driver info */
/*====================*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
/*===================*/
/* I2C Configuration */
/*===================*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/*==================================*/
/* Network & Ethernet Configuration */
/*==================================*/
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
/*=====================*/
/* Flash & Environment */
/*=====================*/
#ifdef CONFIG_SYS_USE_NAND
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_CS 2
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#ifdef CONFIG_SYS_NAND_SMALLPAGE
#define CONFIG_ENV_SECT_SIZE 512 /* Env sector Size */
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT \
"nand0=davinci_nand.0"
#define MTDPARTS_DEFAULT \
"mtdparts=davinci_nand.0:384k(bootloader)ro,4m(kernel),-(filesystem)"
#else
#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#endif
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
#define CONFIG_SYS_NAND_BASE 0x02000000
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
#elif defined(CONFIG_SYS_USE_NOR)
#ifdef CONFIG_NOR_UART_BOOT
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
#else
#undef CONFIG_SKIP_LOWLEVEL_INIT
#endif
#define CONFIG_ENV_IS_IN_FLASH
#undef CONFIG_SYS_NO_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
#define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */
#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*3)
#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ /* Env sector Size */
#endif
/*==============================*/
/* U-Boot general configuration */
/*==============================*/
#define CONFIG_MISC_INIT_R
#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
#define CONFIG_VERSION_VARIABLE
#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
#define CONFIG_USB_MUSB_HCD
#define CONFIG_USB_DAVINCI
/*===================*/
/* Linux Information */
/*===================*/
#define LINUX_BOOT_PARAM_ADDR 0x80000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTARGS "mem=120M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2050000"
/*=================*/
/* U-Boot commands */
/*=================*/
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_EEPROM
#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#endif
#ifdef CONFIG_SYS_USE_NAND
#define CONFIG_CMD_NAND
#elif defined(CONFIG_SYS_USE_NOR)
#define CONFIG_CMD_JFFS2
#else
#error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!"
#endif
/*==========================*/
/* USB MSC support (if any) */
/*==========================*/
#ifdef CONFIG_USB_DAVINCI
#define CONFIG_CMD_USB
#ifdef CONFIG_USB_MUSB_HCD
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_STORAGE
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#endif
#ifdef CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL
#define CONFIG_PREBOOT "usb start"
#endif
#endif
#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */

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@ -1,136 +0,0 @@
/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*=======*/
/* Board */
/*=======*/
#define SCHMOOGIE
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_USE_NAND
#define MACH_TYPE_SCHMOOGIE 1255
#define CONFIG_MACH_TYPE MACH_TYPE_SCHMOOGIE
/*===================*/
/* SoC Configuration */
/*===================*/
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SOC_DM644X
/*=============*/
/* Memory Info */
/*=============*/
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */
#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
/*====================*/
/* Serial Driver info */
/*====================*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
/*===================*/
/* I2C Configuration */
/*===================*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/*==================================*/
/* Network & Ethernet Configuration */
/*==================================*/
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_OVERWRITE_ETHADDR_ONCE
/*=====================*/
/* Flash & Environment */
/*=====================*/
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_SYS_NO_FLASH
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_CS 2
#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
#define CONFIG_SYS_NAND_BASE 0x02000000
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
/*=====================*/
/* Board related stuff */
/*=====================*/
#define CONFIG_RTC_DS1307 /* RTC chip on SCHMOOGIE */
#define CONFIG_SYS_I2C_RTC_ADDR 0x6f /* RTC chip I2C address */
#define CONFIG_UID_DS28CM00 /* Unique ID on SCHMOOGIE */
#define CONFIG_SYS_UID_ADDR 0x50 /* UID chip I2C address */
/*==============================*/
/* U-Boot general configuration */
/*==============================*/
#define CONFIG_MISC_INIT_R
#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
#define CONFIG_VERSION_VARIABLE
#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
/*===================*/
/* Linux Information */
/*===================*/
#define LINUX_BOOT_PARAM_ADDR 0x80000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot"
/*=================*/
/* U-Boot commands */
/*=================*/
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_DATE
#define CONFIG_CMD_NAND
#undef CONFIG_CMD_EEPROM
#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#endif
#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */

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@ -1,129 +0,0 @@
/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Copyright (C) 2008 Lyrtech <www.lyrtech.com>
* Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* Board */
#define SFFSDR
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_USE_NAND
#define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */
/* SoC Configuration */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SOC_DM644X
/* EEPROM definitions for Atmel 24LC64 EEPROM chip */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
/* Memory Info */
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */
#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
/* Serial Driver info */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
/* I2C Configuration */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/* Network & Ethernet Configuration */
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_OVERWRITE_ETHADDR_ONCE
/* Flash & Environment */
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_SYS_NO_FLASH
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_CS 2
#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
#define CONFIG_SYS_NAND_BASE 0x02000000
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
/* I2C switch definitions for PCA9543 chip */
#define CONFIG_SYS_I2C_PCA9543_ADDR 0x70
#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN 0 /* Single register. */
#define CONFIG_SYS_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */
/* U-Boot general configuration */
#define CONFIG_MISC_INIT_R
#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* Default Linux kernel
* load address. */
#define CONFIG_VERSION_VARIABLE
#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far,
* may be later */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
/* Linux Information */
#define LINUX_BOOT_PARAM_ADDR 0x80000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTARGS \
"mem=56M " \
"console=ttyS0,115200n8 " \
"root=/dev/nfs rw noinitrd ip=dhcp " \
"nfsroot=${serverip}:/nfsroot/sffsdr " \
"eth0=${ethaddr}"
#define CONFIG_BOOTCOMMAND \
"nand read 87A00000 100000 300000;" \
"bootelf 87A00000"
/* U-Boot commands */
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_NAND
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF /* Needed to load Integrity kernel. */
#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#endif
#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */

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@ -1,187 +0,0 @@
/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* Define this to make U-Boot skip low level initialization when loaded
* by initial bootloader. Not required by NAND U-Boot version but IS
* required for a NOR version used to burn the real NOR U-Boot into
* NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
* so it is NOT possible to build a U-Boot with both NAND and NOR routines.
* NOR U-Boot is loaded directly from Flash so it must perform all the
* low level initialization itself. NAND version is loaded by an initial
* bootloader (UBL in TI-ese) that performs such an initialization so it's
* skipped in NAND version. The third DaVinci boot mode loads a bootloader
* via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
* performing low level init prior to loading. All that means we can NOT use
* NAND version to put U-Boot into NOR because it doesn't have NOR support and
* we can NOT use NOR version because it performs low level initialization
* effectively destroying itself in DDR memory. That's why a separate NOR
* version with this define is needed. It is loaded via UART, then one uses
* it to somehow download a proper NOR version built WITHOUT this define to
* RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
* NOR support into the initial bootloader so it won't be needed but DaVinci
* static RAM might be too small for this (I have something like 2Kbytes left
* as of now, without NOR support) so this might've not happened...
*
#define CONFIG_NOR_UART_BOOT
*/
/*=======*/
/* Board */
/*=======*/
#define SONATA_BOARD
#define CONFIG_SYS_NAND_SMALLPAGE
#define CONFIG_SYS_USE_NOR
#define MACH_TYPE_SONATA 1254
#define CONFIG_MACH_TYPE MACH_TYPE_SONATA
/*===================*/
/* SoC Configuration */
/*===================*/
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SOC_DM644X
/*====================================================*/
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
/*====================================================*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
/*=============*/
/* Memory Info */
/*=============*/
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */
#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
/*====================*/
/* Serial Driver info */
/*====================*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
/*===================*/
/* I2C Configuration */
/*===================*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/*==================================*/
/* Network & Ethernet Configuration */
/*==================================*/
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
/*=====================*/
/* Flash & Environment */
/*=====================*/
#ifdef CONFIG_SYS_USE_NAND
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_CS 2
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_OVERWRITE /* instead if obsoleted forceenv() */
#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#define CONFIG_ENV_SECT_SIZE 512 /* Env sector Size */
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
#define CONFIG_SYS_NAND_BASE 0x02000000
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
#elif defined(CONFIG_SYS_USE_NOR)
#ifdef CONFIG_NOR_UART_BOOT
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
#else
#undef CONFIG_SKIP_LOWLEVEL_INIT
#endif
#define CONFIG_ENV_IS_IN_FLASH
#undef CONFIG_SYS_NO_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
#define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* 128KB sect size AMD Flash */
#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*2)
#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SZ
#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ /* Env sector Size */
#endif
/*==============================*/
/* U-Boot general configuration */
/*==============================*/
#define CONFIG_MISC_INIT_R
#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
#define CONFIG_VERSION_VARIABLE
#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
/*===================*/
/* Linux Information */
/*===================*/
#define LINUX_BOOT_PARAM_ADDR 0x80000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2060000"
/*=================*/
/* U-Boot commands */
/*=================*/
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_EEPROM
#ifdef CONFIG_SYS_USE_NAND
#define CONFIG_CMD_NAND
#elif defined(CONFIG_SYS_USE_NOR)
#define CONFIG_CMD_JFFS2
#else
#error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!"
#endif
#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#endif
#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */