arm: Remove balloon3 board
This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
Tom Rini
parent
437bc42e7f
commit
679d4456e9
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@ -662,10 +662,6 @@ config TARGET_LS1021ATWR
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select CPU_V7
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select SUPPORT_SPL
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config TARGET_BALLOON3
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bool "Support balloon3"
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select CPU_PXA
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config TARGET_H2200
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bool "Support h2200"
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select CPU_PXA
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@ -809,7 +805,6 @@ source "board/Marvell/gplugd/Kconfig"
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source "board/armadeus/apf27/Kconfig"
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source "board/armltd/vexpress/Kconfig"
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source "board/armltd/vexpress64/Kconfig"
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source "board/balloon3/Kconfig"
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source "board/bluegiga/apx4devkit/Kconfig"
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source "board/broadcom/bcm28155_ap/Kconfig"
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source "board/broadcom/bcmcygnus/Kconfig"
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@ -197,7 +197,6 @@ extern unsigned int __machine_arch_type;
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#define MACH_TYPE_SMDK2412 1009
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#define MACH_TYPE_SMDK2413 1022
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#define MACH_TYPE_AML_M5900 1024
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#define MACH_TYPE_BALLOON3 1029
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#define MACH_TYPE_ECBAT91 1072
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#define MACH_TYPE_ONEARM 1075
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#define MACH_TYPE_SMDK2443 1084
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@ -3332,18 +3331,6 @@ extern unsigned int __machine_arch_type;
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# define machine_is_aml_m5900() (0)
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#endif
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#ifdef CONFIG_MACH_BALLOON3
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# ifdef machine_arch_type
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# undef machine_arch_type
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# define machine_arch_type __machine_arch_type
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# else
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# define machine_arch_type MACH_TYPE_BALLOON3
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# endif
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# define machine_is_balloon3() (machine_arch_type == MACH_TYPE_BALLOON3)
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#else
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# define machine_is_balloon3() (0)
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#endif
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#ifdef CONFIG_MACH_ECBAT91
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# ifdef machine_arch_type
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# undef machine_arch_type
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@ -1,9 +0,0 @@
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if TARGET_BALLOON3
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config SYS_BOARD
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default "balloon3"
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config SYS_CONFIG_NAME
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default "balloon3"
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endif
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@ -1,6 +0,0 @@
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BALLOON3 BOARD
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M: Marek Vasut <marek.vasut@gmail.com>
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S: Maintained
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F: board/balloon3/
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F: include/configs/balloon3.h
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F: configs/balloon3_defconfig
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@ -1,9 +0,0 @@
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#
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# Balloon3 Support
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#
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# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := balloon3.o
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@ -1,221 +0,0 @@
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/*
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* Balloon3 Support
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*
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/pxa.h>
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#include <serial.h>
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#include <asm/io.h>
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#include <spartan3.h>
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#include <command.h>
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#include <usb.h>
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DECLARE_GLOBAL_DATA_PTR;
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void balloon3_init_fpga(void);
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/*
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* Miscelaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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/* We have RAM, disable cache */
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dcache_disable();
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icache_disable();
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/* arch number of balloon3 */
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gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0xa0000100;
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/* Init the FPGA */
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balloon3_init_fpga();
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return 0;
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}
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int dram_init(void)
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{
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pxa2xx_dram_init();
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
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}
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#ifdef CONFIG_CMD_USB
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int board_usb_init(int index, enum usb_init_type init)
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{
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writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
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~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
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UHCHR);
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writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
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while (readl(UHCHR) & UHCHR_FSBIR)
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;
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writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
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writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
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/* Clear any OTG Pin Hold */
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if (readl(PSSR) & PSSR_OTGPH)
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writel(readl(PSSR) | PSSR_OTGPH, PSSR);
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writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
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writel(readl(UHCRHDA) | 0x100, UHCRHDA);
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/* Set port power control mask bits, only 3 ports. */
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writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
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/* enable port 2 */
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writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
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UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
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return 0;
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}
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int board_usb_cleanup(int index, enum usb_init_type init)
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{
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return 0;
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}
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void usb_board_stop(void)
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{
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writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
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udelay(11);
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writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
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writel(readl(UHCCOMS) | 1, UHCCOMS);
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udelay(10);
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writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
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return;
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}
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#endif
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#if defined(CONFIG_FPGA)
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/* Toggle GPIO103 and GPIO104 -- PROGB and RDnWR */
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int fpga_pgm_fn(int nassert, int nflush, int cookie)
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{
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if (nassert)
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writel(0x80, GPCR3);
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else
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writel(0x80, GPSR3);
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if (nflush)
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writel(0x100, GPCR3);
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else
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writel(0x100, GPSR3);
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return nassert;
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}
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/* Check GPIO83 -- INITB */
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int fpga_init_fn(int cookie)
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{
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return !(readl(GPLR2) & 0x80000);
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}
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/* Check GPIO84 -- BUSY */
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int fpga_busy_fn(int cookie)
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{
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return !(readl(GPLR2) & 0x100000);
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}
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/* Check GPIO111 -- DONE */
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int fpga_done_fn(int cookie)
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{
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return readl(GPLR3) & 0x8000;
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}
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/* Configure GPIO104 as GPIO and deassert it */
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int fpga_pre_config_fn(int cookie)
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{
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writel(readl(GAFR3_L) & ~0x30000, GAFR3_L);
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writel(0x100, GPCR3);
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return 0;
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}
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/* Configure GPIO104 as nSKTSEL */
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int fpga_post_config_fn(int cookie)
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{
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writel(readl(GAFR3_L) | 0x10000, GAFR3_L);
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return 0;
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}
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/* Toggle RDnWR */
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int fpga_wr_fn(int nassert_write, int flush, int cookie)
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{
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udelay(1000);
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if (nassert_write)
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writel(0x100, GPCR3);
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else
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writel(0x100, GPSR3);
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return nassert_write;
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}
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/* Write program to the FPGA */
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int fpga_wdata_fn(uchar data, int flush, int cookie)
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{
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writeb(data, 0x10f00000);
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return 0;
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}
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/* Toggle Clock pin -- NO-OP */
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int fpga_clk_fn(int assert_clk, int flush, int cookie)
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{
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return assert_clk;
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}
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/* Toggle ChipSelect pin -- NO-OP */
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int fpga_cs_fn(int assert_clk, int flush, int cookie)
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{
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return assert_clk;
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}
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xilinx_spartan3_slave_parallel_fns balloon3_fpga_fns = {
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fpga_pre_config_fn,
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fpga_pgm_fn,
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fpga_init_fn,
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NULL, /* err */
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fpga_done_fn,
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fpga_clk_fn,
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fpga_cs_fn,
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fpga_wr_fn,
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NULL, /* rdata */
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fpga_wdata_fn,
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fpga_busy_fn,
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NULL, /* abort */
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fpga_post_config_fn,
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};
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xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
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(void *)&balloon3_fpga_fns, 0);
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/* Initialize the FPGA */
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void balloon3_init_fpga(void)
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{
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fpga_init();
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fpga_add(fpga_xilinx, &fpga);
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}
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#else
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void balloon3_init_fpga(void) {}
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#endif /* CONFIG_FPGA */
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@ -1,6 +0,0 @@
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CONFIG_ARM=y
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CONFIG_TARGET_BALLOON3=y
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_SETEXPR is not set
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# CONFIG_CMD_NET is not set
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# CONFIG_CMD_NFS is not set
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@ -1,242 +0,0 @@
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/*
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* Balloon3 configuration file
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*
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Board Configuration Options
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*/
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#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
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#define CONFIG_BALLOON3 1 /* Balloon3 board */
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SYS_MALLOC_LEN (128*1024)
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_BOOTCOMMAND \
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"fpga load 0x0 0x50000 0x62638; " \
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"if usb reset && fatload usb 0 0xa4000000 uImage; then " \
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"bootm 0xa4000000; " \
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"fi; " \
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"bootm 0xd0000;"
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#define CONFIG_BOOTARGS "console=tty0 console=ttyS2,115200"
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#define CONFIG_TIMESTAMP
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#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_SYS_TEXT_BASE 0x0
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#define CONFIG_LZMA /* LZMA compression support */
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/*
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* Serial Console Configuration
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*/
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#define CONFIG_PXA_SERIAL
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#define CONFIG_STUART 1
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#define CONFIG_CONS_INDEX 2
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#define CONFIG_BAUDRATE 115200
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/*
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* Bootloader Components Configuration
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*/
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#undef CONFIG_CMD_ENV
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#define CONFIG_CMD_USB
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#define CONFIG_CMD_FPGA_LOADMK
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#undef CONFIG_LCD
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/*
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* KGDB
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*/
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#ifdef CONFIG_CMD_KGDB
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#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
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#endif
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/*
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* HUSH Shell Configuration
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*/
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#define CONFIG_SYS_HUSH_PARSER 1
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#define CONFIG_SYS_LONGHELP
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#undef CONFIG_SYS_PROMPT
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT "$ "
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#else
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#endif
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_DEVICE_NULLDEV 1
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/*
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* Clock Configuration
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*/
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#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
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/*
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* DRAM Map
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*/
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#define CONFIG_NR_DRAM_BANKS 3 /* 3 banks of DRAM */
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
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#define PHYS_SDRAM_2 0xb0000000 /* SDRAM Bank #2 */
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#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
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#define PHYS_SDRAM_3 0x80000000 /* SDRAM Bank #3 */
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#define PHYS_SDRAM_3_SIZE 0x08000000 /* 128 MB */
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#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
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#define CONFIG_SYS_DRAM_SIZE 0x18000000 /* 384 MB DRAM */
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#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0xa1000000
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_SP_ADDR \
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(PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048)
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/*
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* NOR FLASH
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*/
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#ifdef CONFIG_CMD_FLASH
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
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#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
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#define CONFIG_SYS_FLASH_WRITE_TOUT 240000
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#define CONFIG_SYS_FLASH_LOCK_TOUT 240000
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#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_ENV_IS_IN_FLASH
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#else
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_ENV_IS_NOWHERE
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#endif
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#define CONFIG_SYS_MONITOR_BASE 0x000000
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#define CONFIG_SYS_MONITOR_LEN 0x40000
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_ADDR 0x40000
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#define CONFIG_ENV_SECT_SIZE 0x10000
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/*
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* GPIO settings
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*/
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#define CONFIG_SYS_GPSR0_VAL 0x307dc7fd
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#define CONFIG_SYS_GPSR1_VAL 0x03cffa4e
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#define CONFIG_SYS_GPSR2_VAL 0x7131c000
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#define CONFIG_SYS_GPSR3_VAL 0x01e1f3ff
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#define CONFIG_SYS_GPCR0_VAL 0x0
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#define CONFIG_SYS_GPCR1_VAL 0x0
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#define CONFIG_SYS_GPCR2_VAL 0x0
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#define CONFIG_SYS_GPCR3_VAL 0x0
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#define CONFIG_SYS_GPDR0_VAL 0xc0f98e02
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#define CONFIG_SYS_GPDR1_VAL 0xfcffa8b7
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#define CONFIG_SYS_GPDR2_VAL 0x22e3ffff
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#define CONFIG_SYS_GPDR3_VAL 0x000201fe
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#define CONFIG_SYS_GAFR0_L_VAL 0x96c00000
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#define CONFIG_SYS_GAFR0_U_VAL 0xa5e5459b
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#define CONFIG_SYS_GAFR1_L_VAL 0x699b759a
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#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a5aa
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#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
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#define CONFIG_SYS_GAFR2_U_VAL 0x01f9a6aa
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#define CONFIG_SYS_GAFR3_L_VAL 0x54510003
|
||||
#define CONFIG_SYS_GAFR3_U_VAL 0x00001599
|
||||
|
||||
#define CONFIG_SYS_PSSR_VAL 0x30
|
||||
|
||||
/*
|
||||
* Clock settings
|
||||
*/
|
||||
#define CONFIG_SYS_CKEN 0xffffffff
|
||||
#define CONFIG_SYS_CCCR 0x00000290
|
||||
|
||||
/*
|
||||
* Memory settings
|
||||
*/
|
||||
#define CONFIG_SYS_MSC0_VAL 0x7ff07ff8
|
||||
#define CONFIG_SYS_MSC1_VAL 0x7ff07ff0
|
||||
#define CONFIG_SYS_MSC2_VAL 0x74a42491
|
||||
#define CONFIG_SYS_MDCNFG_VAL 0x89d309d3
|
||||
#define CONFIG_SYS_MDREFR_VAL 0x001d8018
|
||||
#define CONFIG_SYS_MDMRS_VAL 0x00220022
|
||||
#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
|
||||
#define CONFIG_SYS_SXCNFG_VAL 0x00000000
|
||||
|
||||
/*
|
||||
* PCMCIA and CF Interfaces
|
||||
*/
|
||||
#define CONFIG_SYS_MECR_VAL 0x00000000
|
||||
#define CONFIG_SYS_MCMEM0_VAL 0x00014307
|
||||
#define CONFIG_SYS_MCMEM1_VAL 0x00014307
|
||||
#define CONFIG_SYS_MCATT0_VAL 0x0001c787
|
||||
#define CONFIG_SYS_MCATT1_VAL 0x0001c787
|
||||
#define CONFIG_SYS_MCIO0_VAL 0x0001430f
|
||||
#define CONFIG_SYS_MCIO1_VAL 0x0001430f
|
||||
|
||||
/*
|
||||
* LCD
|
||||
*/
|
||||
#ifdef CONFIG_LCD
|
||||
#define CONFIG_BALLOON3LCD
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_CMD_BMP
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
#define CONFIG_SPLASH_SCREEN_ALIGN
|
||||
#define CONFIG_VIDEO_BMP_GZIP
|
||||
#define CONFIG_VIDEO_BMP_RLE8
|
||||
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_USB_OHCI_NEW
|
||||
#define CONFIG_SYS_USB_OHCI_CPU_INIT
|
||||
#define CONFIG_SYS_USB_OHCI_BOARD_INIT
|
||||
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
|
||||
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
|
||||
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "balloon3"
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_EXT2
|
||||
#endif
|
||||
|
||||
/*
|
||||
* FPGA
|
||||
*/
|
||||
#ifdef CONFIG_CMD_FPGA
|
||||
#define CONFIG_FPGA
|
||||
#define CONFIG_FPGA_XILINX
|
||||
#define CONFIG_FPGA_SPARTAN3
|
||||
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
|
||||
#define CONFIG_SYS_FPGA_WAIT 1000
|
||||
#define CONFIG_MAX_FPGA_DEVICES 1
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue