EXYNOS: support EXYNOS framebuffer and FIMD display drivers.
This patch support EXYNOS FB and FIMD display drivers. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Acked-by: Anatolij Gustschin <agust@denx.de>
This commit is contained in:
Donghwa Lee
Albert ARIBAUD
parent
559a05cc32
commit
6d4339f622
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@ -0,0 +1,446 @@
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/*
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* (C) Copyright 2012 Samsung Electronics
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* Donghwa Lee <dh09.lee@samsung.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* aint with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef __ASM_ARM_ARCH_FB_H_
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#define __ASM_ARM_ARCH_FB_H_
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#ifndef __ASSEMBLY__
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struct exynos4_fb {
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unsigned int vidcon0;
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unsigned int vidcon1;
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unsigned int vidcon2;
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unsigned int vidcon3;
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unsigned int vidtcon0;
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unsigned int vidtcon1;
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unsigned int vidtcon2;
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unsigned int vidtcon3;
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unsigned int wincon0;
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unsigned int wincon1;
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unsigned int wincon2;
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unsigned int wincon3;
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unsigned int wincon4;
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unsigned int winshmap;
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unsigned int res1;
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unsigned int winchmap2;
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unsigned int vidosd0a;
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unsigned int vidosd0b;
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unsigned int vidosd0c;
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unsigned int res2;
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unsigned int vidosd1a;
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unsigned int vidosd1b;
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unsigned int vidosd1c;
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unsigned int vidosd1d;
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unsigned int vidosd2a;
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unsigned int vidosd2b;
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unsigned int vidosd2c;
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unsigned int vidosd2d;
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unsigned int vidosd3a;
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unsigned int vidosd3b;
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unsigned int vidosd3c;
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unsigned int res3;
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unsigned int vidosd4a;
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unsigned int vidosd4b;
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unsigned int vidosd4c;
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unsigned int res4[5];
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unsigned int vidw00add0b0;
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unsigned int vidw00add0b1;
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unsigned int vidw01add0b0;
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unsigned int vidw01add0b1;
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unsigned int vidw02add0b0;
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unsigned int vidw02add0b1;
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unsigned int vidw03add0b0;
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unsigned int vidw03add0b1;
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unsigned int vidw04add0b0;
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unsigned int vidw04add0b1;
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unsigned int res5[2];
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unsigned int vidw00add1b0;
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unsigned int vidw00add1b1;
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unsigned int vidw01add1b0;
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unsigned int vidw01add1b1;
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unsigned int vidw02add1b0;
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unsigned int vidw02add1b1;
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unsigned int vidw03add1b0;
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unsigned int vidw03add1b1;
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unsigned int vidw04add1b0;
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unsigned int vidw04add1b1;
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unsigned int res7[2];
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unsigned int vidw00add2;
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unsigned int vidw01add2;
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unsigned int vidw02add2;
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unsigned int vidw03add2;
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unsigned int vidw04add2;
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unsigned int res8[7];
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unsigned int vidintcon0;
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unsigned int vidintcon1;
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unsigned int res9[1];
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unsigned int w1keycon0;
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unsigned int w1keycon1;
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unsigned int w2keycon0;
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unsigned int w2keycon1;
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unsigned int w3keycon0;
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unsigned int w3keycon1;
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unsigned int w4keycon0;
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unsigned int w4keycon1;
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unsigned int w1keyalpha;
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unsigned int w2keyalpha;
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unsigned int w3keyalpha;
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unsigned int w4keyalpha;
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unsigned int dithmode;
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unsigned int res10[2];
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unsigned int win0map;
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unsigned int win1map;
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unsigned int win2map;
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unsigned int win3map;
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unsigned int win4map;
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unsigned int res11[1];
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unsigned int wpalcon_h;
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unsigned int wpalcon_l;
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unsigned int trigcon;
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unsigned int res12[2];
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unsigned int i80ifcona0;
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unsigned int i80ifcona1;
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unsigned int i80ifconb0;
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unsigned int i80ifconb1;
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unsigned int colorgaincon;
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unsigned int res13[2];
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unsigned int ldi_cmdcon0;
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unsigned int ldi_cmdcon1;
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unsigned int res14[1];
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/* To be updated */
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unsigned char res15[156];
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unsigned int dualrgb;
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};
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#endif
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/*
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* Register offsets
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*/
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#define EXYNOS_WINCON(x) (x * 0x04)
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#define EXYNOS_VIDOSD(x) (x * 0x10)
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#define EXYNOS_BUFFER_OFFSET(x) (x * 0x08)
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#define EXYNOS_BUFFER_SIZE(x) (x * 0x04)
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/*
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* Bit Definitions
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*/
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/* VIDCON0 */
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#define EXYNOS_VIDCON0_DSI_DISABLE (0 << 30)
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#define EXYNOS_VIDCON0_DSI_ENABLE (1 << 30)
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#define EXYNOS_VIDCON0_SCAN_PROGRESSIVE (0 << 29)
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#define EXYNOS_VIDCON0_SCAN_INTERLACE (1 << 29)
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#define EXYNOS_VIDCON0_SCAN_MASK (1 << 29)
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#define EXYNOS_VIDCON0_VIDOUT_RGB (0 << 26)
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#define EXYNOS_VIDCON0_VIDOUT_ITU (1 << 26)
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#define EXYNOS_VIDCON0_VIDOUT_I80LDI0 (2 << 26)
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#define EXYNOS_VIDCON0_VIDOUT_I80LDI1 (3 << 26)
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#define EXYNOS_VIDCON0_VIDOUT_WB_RGB (4 << 26)
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#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI0 (6 << 26)
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#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI1 (7 << 26)
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#define EXYNOS_VIDCON0_VIDOUT_MASK (7 << 26)
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#define EXYNOS_VIDCON0_PNRMODE_RGB_P (0 << 17)
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#define EXYNOS_VIDCON0_PNRMODE_BGR_P (1 << 17)
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#define EXYNOS_VIDCON0_PNRMODE_RGB_S (2 << 17)
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#define EXYNOS_VIDCON0_PNRMODE_BGR_S (3 << 17)
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#define EXYNOS_VIDCON0_PNRMODE_MASK (3 << 17)
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#define EXYNOS_VIDCON0_PNRMODE_SHIFT (17)
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#define EXYNOS_VIDCON0_CLKVALUP_ALWAYS (0 << 16)
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#define EXYNOS_VIDCON0_CLKVALUP_START_FRAME (1 << 16)
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#define EXYNOS_VIDCON0_CLKVALUP_MASK (1 << 16)
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#define EXYNOS_VIDCON0_CLKVAL_F(x) (((x) & 0xff) << 6)
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#define EXYNOS_VIDCON0_VCLKEN_NORMAL (0 << 5)
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#define EXYNOS_VIDCON0_VCLKEN_FREERUN (1 << 5)
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#define EXYNOS_VIDCON0_VCLKEN_MASK (1 << 5)
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#define EXYNOS_VIDCON0_CLKDIR_DIRECTED (0 << 4)
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#define EXYNOS_VIDCON0_CLKDIR_DIVIDED (1 << 4)
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#define EXYNOS_VIDCON0_CLKDIR_MASK (1 << 4)
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#define EXYNOS_VIDCON0_CLKSEL_HCLK (0 << 2)
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#define EXYNOS_VIDCON0_CLKSEL_SCLK (1 << 2)
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#define EXYNOS_VIDCON0_CLKSEL_MASK (1 << 2)
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#define EXYNOS_VIDCON0_ENVID_ENABLE (1 << 1)
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#define EXYNOS_VIDCON0_ENVID_DISABLE (0 << 1)
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#define EXYNOS_VIDCON0_ENVID_F_ENABLE (1 << 0)
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#define EXYNOS_VIDCON0_ENVID_F_DISABLE (0 << 0)
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/* VIDCON1 */
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#define EXYNOS_VIDCON1_IVCLK_FALLING_EDGE (0 << 7)
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#define EXYNOS_VIDCON1_IVCLK_RISING_EDGE (1 << 7)
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#define EXYNOS_VIDCON1_IHSYNC_NORMAL (0 << 6)
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#define EXYNOS_VIDCON1_IHSYNC_INVERT (1 << 6)
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#define EXYNOS_VIDCON1_IVSYNC_NORMAL (0 << 5)
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#define EXYNOS_VIDCON1_IVSYNC_INVERT (1 << 5)
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#define EXYNOS_VIDCON1_IVDEN_NORMAL (0 << 4)
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#define EXYNOS_VIDCON1_IVDEN_INVERT (1 << 4)
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/* VIDCON2 */
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#define EXYNOS_VIDCON2_EN601_DISABLE (0 << 23)
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#define EXYNOS_VIDCON2_EN601_ENABLE (1 << 23)
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#define EXYNOS_VIDCON2_EN601_MASK (1 << 23)
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#define EXYNOS_VIDCON2_WB_DISABLE (0 << 15)
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#define EXYNOS_VIDCON2_WB_ENABLE (1 << 15)
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#define EXYNOS_VIDCON2_WB_MASK (1 << 15)
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#define EXYNOS_VIDCON2_TVFORMATSEL_HW (0 << 14)
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#define EXYNOS_VIDCON2_TVFORMATSEL_SW (1 << 14)
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#define EXYNOS_VIDCON2_TVFORMATSEL_MASK (1 << 14)
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#define EXYNOS_VIDCON2_TVFORMATSEL_YUV422 (1 << 12)
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#define EXYNOS_VIDCON2_TVFORMATSEL_YUV444 (2 << 12)
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#define EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK (3 << 12)
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#define EXYNOS_VIDCON2_ORGYUV_YCBCR (0 << 8)
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#define EXYNOS_VIDCON2_ORGYUV_CBCRY (1 << 8)
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#define EXYNOS_VIDCON2_ORGYUV_MASK (1 << 8)
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#define EXYNOS_VIDCON2_YUVORD_CBCR (0 << 7)
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#define EXYNOS_VIDCON2_YUVORD_CRCB (1 << 7)
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#define EXYNOS_VIDCON2_YUVORD_MASK (1 << 7)
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/* PRTCON */
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#define EXYNOS_PRTCON_UPDATABLE (0 << 11)
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#define EXYNOS_PRTCON_PROTECT (1 << 11)
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/* VIDTCON0 */
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#define EXYNOS_VIDTCON0_VBPDE(x) (((x) & 0xff) << 24)
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#define EXYNOS_VIDTCON0_VBPD(x) (((x) & 0xff) << 16)
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#define EXYNOS_VIDTCON0_VFPD(x) (((x) & 0xff) << 8)
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#define EXYNOS_VIDTCON0_VSPW(x) (((x) & 0xff) << 0)
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/* VIDTCON1 */
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#define EXYNOS_VIDTCON1_VFPDE(x) (((x) & 0xff) << 24)
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#define EXYNOS_VIDTCON1_HBPD(x) (((x) & 0xff) << 16)
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#define EXYNOS_VIDTCON1_HFPD(x) (((x) & 0xff) << 8)
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#define EXYNOS_VIDTCON1_HSPW(x) (((x) & 0xff) << 0)
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/* VIDTCON2 */
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#define EXYNOS_VIDTCON2_LINEVAL(x) (((x) & 0x7ff) << 11)
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#define EXYNOS_VIDTCON2_HOZVAL(x) (((x) & 0x7ff) << 0)
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/* Window 0~4 Control - WINCONx */
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#define EXYNOS_WINCON_DATAPATH_DMA (0 << 22)
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#define EXYNOS_WINCON_DATAPATH_LOCAL (1 << 22)
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#define EXYNOS_WINCON_DATAPATH_MASK (1 << 22)
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#define EXYNOS_WINCON_BUFSEL_0 (0 << 20)
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#define EXYNOS_WINCON_BUFSEL_1 (1 << 20)
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#define EXYNOS_WINCON_BUFSEL_MASK (1 << 20)
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#define EXYNOS_WINCON_BUFSEL_SHIFT (20)
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#define EXYNOS_WINCON_BUFAUTO_DISABLE (0 << 19)
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#define EXYNOS_WINCON_BUFAUTO_ENABLE (1 << 19)
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#define EXYNOS_WINCON_BUFAUTO_MASK (1 << 19)
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#define EXYNOS_WINCON_BITSWP_DISABLE (0 << 18)
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#define EXYNOS_WINCON_BITSWP_ENABLE (1 << 18)
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#define EXYNOS_WINCON_BITSWP_SHIFT (18)
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#define EXYNOS_WINCON_BYTESWP_DISABLE (0 << 17)
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#define EXYNOS_WINCON_BYTESWP_ENABLE (1 << 17)
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#define EXYNOS_WINCON_BYTESWP_SHIFT (17)
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#define EXYNOS_WINCON_HAWSWP_DISABLE (0 << 16)
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#define EXYNOS_WINCON_HAWSWP_ENABLE (1 << 16)
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#define EXYNOS_WINCON_HAWSWP_SHIFT (16)
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#define EXYNOS_WINCON_WSWP_DISABLE (0 << 15)
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#define EXYNOS_WINCON_WSWP_ENABLE (1 << 15)
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#define EXYNOS_WINCON_WSWP_SHIFT (15)
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#define EXYNOS_WINCON_INRGB_RGB (0 << 13)
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#define EXYNOS_WINCON_INRGB_YUV (1 << 13)
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#define EXYNOS_WINCON_INRGB_MASK (1 << 13)
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#define EXYNOS_WINCON_BURSTLEN_16WORD (0 << 9)
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#define EXYNOS_WINCON_BURSTLEN_8WORD (1 << 9)
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#define EXYNOS_WINCON_BURSTLEN_4WORD (2 << 9)
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#define EXYNOS_WINCON_BURSTLEN_MASK (3 << 9)
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#define EXYNOS_WINCON_ALPHA_MULTI_DISABLE (0 << 7)
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#define EXYNOS_WINCON_ALPHA_MULTI_ENABLE (1 << 7)
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#define EXYNOS_WINCON_BLD_PLANE (0 << 6)
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#define EXYNOS_WINCON_BLD_PIXEL (1 << 6)
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#define EXYNOS_WINCON_BLD_MASK (1 << 6)
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#define EXYNOS_WINCON_BPPMODE_1BPP (0 << 2)
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#define EXYNOS_WINCON_BPPMODE_2BPP (1 << 2)
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#define EXYNOS_WINCON_BPPMODE_4BPP (2 << 2)
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#define EXYNOS_WINCON_BPPMODE_8BPP_PAL (3 << 2)
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#define EXYNOS_WINCON_BPPMODE_8BPP (4 << 2)
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#define EXYNOS_WINCON_BPPMODE_16BPP_565 (5 << 2)
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#define EXYNOS_WINCON_BPPMODE_16BPP_A555 (6 << 2)
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#define EXYNOS_WINCON_BPPMODE_18BPP_666 (8 << 2)
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#define EXYNOS_WINCON_BPPMODE_18BPP_A665 (9 << 2)
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#define EXYNOS_WINCON_BPPMODE_24BPP_888 (0xb << 2)
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#define EXYNOS_WINCON_BPPMODE_24BPP_A887 (0xc << 2)
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#define EXYNOS_WINCON_BPPMODE_32BPP (0xd << 2)
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#define EXYNOS_WINCON_BPPMODE_16BPP_A444 (0xe << 2)
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#define EXYNOS_WINCON_BPPMODE_15BPP_555 (0xf << 2)
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#define EXYNOS_WINCON_BPPMODE_MASK (0xf << 2)
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#define EXYNOS_WINCON_BPPMODE_SHIFT (2)
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#define EXYNOS_WINCON_ALPHA0_SEL (0 << 1)
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#define EXYNOS_WINCON_ALPHA1_SEL (1 << 1)
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#define EXYNOS_WINCON_ALPHA_SEL_MASK (1 << 1)
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#define EXYNOS_WINCON_ENWIN_DISABLE (0 << 0)
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#define EXYNOS_WINCON_ENWIN_ENABLE (1 << 0)
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/* WINCON1 special */
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#define EXYNOS_WINCON1_VP_DISABLE (0 << 24)
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#define EXYNOS_WINCON1_VP_ENABLE (1 << 24)
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#define EXYNOS_WINCON1_LOCALSEL_FIMC1 (0 << 23)
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#define EXYNOS_WINCON1_LOCALSEL_VP (1 << 23)
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#define EXYNOS_WINCON1_LOCALSEL_MASK (1 << 23)
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/* WINSHMAP */
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#define EXYNOS_WINSHMAP_PROTECT(x) (((x) & 0x1f) << 10)
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#define EXYNOS_WINSHMAP_CH_ENABLE(x) (1 << (x))
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#define EXYNOS_WINSHMAP_CH_DISABLE(x) (1 << (x))
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#define EXYNOS_WINSHMAP_LOCAL_ENABLE(x) (0x20 << (x))
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#define EXYNOS_WINSHMAP_LOCAL_DISABLE(x) (0x20 << (x))
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/* VIDOSDxA, VIDOSDxB */
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#define EXYNOS_VIDOSD_LEFT_X(x) (((x) & 0x7ff) << 11)
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#define EXYNOS_VIDOSD_TOP_Y(x) (((x) & 0x7ff) << 0)
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#define EXYNOS_VIDOSD_RIGHT_X(x) (((x) & 0x7ff) << 11)
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#define EXYNOS_VIDOSD_BOTTOM_Y(x) (((x) & 0x7ff) << 0)
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/* VIDOSD0C, VIDOSDxD */
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#define EXYNOS_VIDOSD_SIZE(x) (((x) & 0xffffff) << 0)
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/* VIDOSDxC (1~4) */
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#define EXYNOS_VIDOSD_ALPHA0_R(x) (((x) & 0xf) << 20)
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#define EXYNOS_VIDOSD_ALPHA0_G(x) (((x) & 0xf) << 16)
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#define EXYNOS_VIDOSD_ALPHA0_B(x) (((x) & 0xf) << 12)
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#define EXYNOS_VIDOSD_ALPHA1_R(x) (((x) & 0xf) << 8)
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#define EXYNOS_VIDOSD_ALPHA1_G(x) (((x) & 0xf) << 4)
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#define EXYNOS_VIDOSD_ALPHA1_B(x) (((x) & 0xf) << 0)
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#define EXYNOS_VIDOSD_ALPHA0_SHIFT (12)
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#define EXYNOS_VIDOSD_ALPHA1_SHIFT (0)
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/* Start Address */
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#define EXYNOS_VIDADDR_START_VBANK(x) (((x) & 0xff) << 24)
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#define EXYNOS_VIDADDR_START_VBASEU(x) (((x) & 0xffffff) << 0)
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/* End Address */
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#define EXYNOS_VIDADDR_END_VBASEL(x) (((x) & 0xffffff) << 0)
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/* Buffer Size */
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#define EXYNOS_VIDADDR_OFFSIZE(x) (((x) & 0x1fff) << 13)
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#define EXYNOS_VIDADDR_PAGEWIDTH(x) (((x) & 0x1fff) << 0)
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/* WIN Color Map */
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#define EXYNOS_WINMAP_COLOR(x) ((x) & 0xffffff)
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/* VIDINTCON0 */
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#define EXYNOS_VIDINTCON0_SYSMAINCON_DISABLE (0 << 19)
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#define EXYNOS_VIDINTCON0_SYSMAINCON_ENABLE (1 << 19)
|
||||
#define EXYNOS_VIDINTCON0_SYSSUBCON_DISABLE (0 << 18)
|
||||
#define EXYNOS_VIDINTCON0_SYSSUBCON_ENABLE (1 << 18)
|
||||
#define EXYNOS_VIDINTCON0_SYSIFDONE_DISABLE (0 << 17)
|
||||
#define EXYNOS_VIDINTCON0_SYSIFDONE_ENABLE (1 << 17)
|
||||
#define EXYNOS_VIDINTCON0_FRAMESEL0_BACK (0 << 15)
|
||||
#define EXYNOS_VIDINTCON0_FRAMESEL0_VSYNC (1 << 15)
|
||||
#define EXYNOS_VIDINTCON0_FRAMESEL0_ACTIVE (2 << 15)
|
||||
#define EXYNOS_VIDINTCON0_FRAMESEL0_FRONT (3 << 15)
|
||||
#define EXYNOS_VIDINTCON0_FRAMESEL0_MASK (3 << 15)
|
||||
#define EXYNOS_VIDINTCON0_FRAMESEL1_NONE (0 << 13)
|
||||
#define EXYNOS_VIDINTCON0_FRAMESEL1_BACK (1 << 13)
|
||||
#define EXYNOS_VIDINTCON0_FRAMESEL1_VSYNC (2 << 13)
|
||||
#define EXYNOS_VIDINTCON0_FRAMESEL1_FRONT (3 << 13)
|
||||
#define EXYNOS_VIDINTCON0_INTFRMEN_DISABLE (0 << 12)
|
||||
#define EXYNOS_VIDINTCON0_INTFRMEN_ENABLE (1 << 12)
|
||||
#define EXYNOS_VIDINTCON0_FIFOSEL_WIN4 (1 << 11)
|
||||
#define EXYNOS_VIDINTCON0_FIFOSEL_WIN3 (1 << 10)
|
||||
#define EXYNOS_VIDINTCON0_FIFOSEL_WIN2 (1 << 9)
|
||||
#define EXYNOS_VIDINTCON0_FIFOSEL_WIN1 (1 << 6)
|
||||
#define EXYNOS_VIDINTCON0_FIFOSEL_WIN0 (1 << 5)
|
||||
#define EXYNOS_VIDINTCON0_FIFOSEL_ALL (0x73 << 5)
|
||||
#define EXYNOS_VIDINTCON0_FIFOSEL_MASK (0x73 << 5)
|
||||
#define EXYNOS_VIDINTCON0_FIFOLEVEL_25 (0 << 2)
|
||||
#define EXYNOS_VIDINTCON0_FIFOLEVEL_50 (1 << 2)
|
||||
#define EXYNOS_VIDINTCON0_FIFOLEVEL_75 (2 << 2)
|
||||
#define EXYNOS_VIDINTCON0_FIFOLEVEL_EMPTY (3 << 2)
|
||||
#define EXYNOS_VIDINTCON0_FIFOLEVEL_FULL (4 << 2)
|
||||
#define EXYNOS_VIDINTCON0_FIFOLEVEL_MASK (7 << 2)
|
||||
#define EXYNOS_VIDINTCON0_INTFIFO_DISABLE (0 << 1)
|
||||
#define EXYNOS_VIDINTCON0_INTFIFO_ENABLE (1 << 1)
|
||||
#define EXYNOS_VIDINTCON0_INT_DISABLE (0 << 0)
|
||||
#define EXYNOS_VIDINTCON0_INT_ENABLE (1 << 0)
|
||||
#define EXYNOS_VIDINTCON0_INT_MASK (1 << 0)
|
||||
|
||||
/* VIDINTCON1 */
|
||||
#define EXYNOS_VIDINTCON1_INTVPPEND (1 << 5)
|
||||
#define EXYNOS_VIDINTCON1_INTI80PEND (1 << 2)
|
||||
#define EXYNOS_VIDINTCON1_INTFRMPEND (1 << 1)
|
||||
#define EXYNOS_VIDINTCON1_INTFIFOPEND (1 << 0)
|
||||
|
||||
/* WINMAP */
|
||||
#define EXYNOS_WINMAP_ENABLE (1 << 24)
|
||||
|
||||
/* WxKEYCON0 (1~4) */
|
||||
#define EXYNOS_KEYCON0_KEYBLEN_DISABLE (0 << 26)
|
||||
#define EXYNOS_KEYCON0_KEYBLEN_ENABLE (1 << 26)
|
||||
#define EXYNOS_KEYCON0_KEY_DISABLE (0 << 25)
|
||||
#define EXYNOS_KEYCON0_KEY_ENABLE (1 << 25)
|
||||
#define EXYNOS_KEYCON0_DIRCON_MATCH_FG (0 << 24)
|
||||
#define EXYNOS_KEYCON0_DIRCON_MATCH_BG (1 << 24)
|
||||
#define EXYNOS_KEYCON0_COMPKEY(x) (((x) & 0xffffff) << 0)
|
||||
|
||||
/* WxKEYCON1 (1~4) */
|
||||
#define EXYNOS_KEYCON1_COLVAL(x) (((x) & 0xffffff) << 0)
|
||||
|
||||
/* DUALRGB */
|
||||
#define EXYNOS_DUALRGB_BYPASS_SINGLE (0x00 << 0)
|
||||
#define EXYNOS_DUALRGB_BYPASS_DUAL (0x01 << 0)
|
||||
#define EXYNOS_DUALRGB_MIE_DUAL (0x10 << 0)
|
||||
#define EXYNOS_DUALRGB_MIE_SINGLE (0x11 << 0)
|
||||
#define EXYNOS_DUALRGB_LINESPLIT (0x0 << 2)
|
||||
#define EXYNOS_DUALRGB_FRAMESPLIT (0x1 << 2)
|
||||
#define EXYNOS_DUALRGB_SUB_CNT(x) ((x & 0xfff) << 4)
|
||||
#define EXYNOS_DUALRGB_VDEN_EN_DISABLE (0x0 << 16)
|
||||
#define EXYNOS_DUALRGB_VDEN_EN_ENABLE (0x1 << 16)
|
||||
#define EXYNOS_DUALRGB_MAIN_CNT(x) ((x & 0xfff) << 18)
|
||||
|
||||
/* I80IFCONA0 and I80IFCONA1 */
|
||||
#define EXYNOS_LCD_CS_SETUP(x) (((x) & 0xf) << 16)
|
||||
#define EXYNOS_LCD_WR_SETUP(x) (((x) & 0xf) << 12)
|
||||
#define EXYNOS_LCD_WR_ACT(x) (((x) & 0xf) << 8)
|
||||
#define EXYNOS_LCD_WR_HOLD(x) (((x) & 0xf) << 4)
|
||||
#define EXYNOS_RSPOL_LOW (0 << 2)
|
||||
#define EXYNOS_RSPOL_HIGH (1 << 2)
|
||||
#define EXYNOS_I80IFEN_DISABLE (0 << 0)
|
||||
#define EXYNOS_I80IFEN_ENABLE (1 << 0)
|
||||
|
||||
/* TRIGCON */
|
||||
#define EXYNOS_I80SOFT_TRIG_EN (1 << 0)
|
||||
#define EXYNOS_I80START_TRIG (1 << 1)
|
||||
#define EXYNOS_I80STATUS_TRIG_DONE (1 << 2)
|
||||
|
||||
#endif /* _REGS_FB_H */
|
||||
|
|
@ -28,6 +28,7 @@ LIB := $(obj)libvideo.o
|
|||
COBJS-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
|
||||
COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
|
||||
COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o
|
||||
COBJS-$(CONFIG_EXYNOS_FB) += exynos_fb.o exynos_fimd.o
|
||||
COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
|
||||
COBJS-$(CONFIG_S6E63D6) += s6e63d6.o
|
||||
COBJS-$(CONFIG_SED156X) += sed156x.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,128 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Samsung Electronics
|
||||
*
|
||||
* Author: InKi Dae <inki.dae@samsung.com>
|
||||
* Author: Donghwa Lee <dh09.lee@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <lcd.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/clk.h>
|
||||
#include <asm/arch/mipi_dsim.h>
|
||||
#include <asm/arch/system.h>
|
||||
|
||||
#include "exynos_fb.h"
|
||||
|
||||
int lcd_line_length;
|
||||
int lcd_color_fg;
|
||||
int lcd_color_bg;
|
||||
|
||||
void *lcd_base;
|
||||
void *lcd_console_address;
|
||||
|
||||
short console_col;
|
||||
short console_row;
|
||||
|
||||
static unsigned int panel_width, panel_height;
|
||||
|
||||
/* LCD Panel data */
|
||||
vidinfo_t panel_info;
|
||||
|
||||
static void exynos_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
|
||||
{
|
||||
unsigned long palette_size;
|
||||
unsigned int fb_size;
|
||||
|
||||
fb_size = vid->vl_row * vid->vl_col * (vid->vl_bpix >> 3);
|
||||
|
||||
lcd_base = lcdbase;
|
||||
|
||||
palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
|
||||
|
||||
exynos_fimd_lcd_init_mem((unsigned long)lcd_base,
|
||||
(unsigned long)fb_size, palette_size);
|
||||
}
|
||||
|
||||
static void exynos_lcd_init(vidinfo_t *vid)
|
||||
{
|
||||
exynos_fimd_lcd_init(vid);
|
||||
}
|
||||
|
||||
static void lcd_panel_on(vidinfo_t *vid)
|
||||
{
|
||||
udelay(vid->init_delay);
|
||||
|
||||
if (vid->backlight_reset)
|
||||
vid->backlight_reset();
|
||||
|
||||
if (vid->cfg_gpio)
|
||||
vid->cfg_gpio();
|
||||
|
||||
if (vid->lcd_power_on)
|
||||
vid->lcd_power_on();
|
||||
|
||||
udelay(vid->power_on_delay);
|
||||
|
||||
if (vid->reset_lcd) {
|
||||
vid->reset_lcd();
|
||||
udelay(vid->reset_delay);
|
||||
}
|
||||
|
||||
if (vid->backlight_on)
|
||||
vid->backlight_on(1);
|
||||
|
||||
if (vid->cfg_ldo)
|
||||
vid->cfg_ldo();
|
||||
|
||||
if (vid->enable_ldo)
|
||||
vid->enable_ldo(1);
|
||||
|
||||
if (vid->mipi_enabled)
|
||||
exynos_mipi_dsi_init();
|
||||
}
|
||||
|
||||
void lcd_ctrl_init(void *lcdbase)
|
||||
{
|
||||
set_system_display_ctrl();
|
||||
set_lcd_clk();
|
||||
|
||||
/* initialize parameters which is specific to panel. */
|
||||
init_panel_info(&panel_info);
|
||||
|
||||
panel_width = panel_info.vl_width;
|
||||
panel_height = panel_info.vl_height;
|
||||
|
||||
exynos_lcd_init_mem(lcdbase, &panel_info);
|
||||
|
||||
exynos_lcd_init(&panel_info);
|
||||
}
|
||||
|
||||
void lcd_enable(void)
|
||||
{
|
||||
lcd_panel_on(&panel_info);
|
||||
}
|
||||
|
||||
/* dummy function */
|
||||
void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Samsung Electronics
|
||||
*
|
||||
* Author: InKi Dae <inki.dae@samsung.com>
|
||||
* Author: Donghwa Lee <dh09.lee@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _EXYNOS_FB_H_
|
||||
#define _EXYNOS_FB_H_
|
||||
|
||||
#include <asm/arch/fb.h>
|
||||
|
||||
#define MAX_CLOCK (86 * 1000000)
|
||||
|
||||
enum exynos_fb_rgb_mode_t {
|
||||
MODE_RGB_P = 0,
|
||||
MODE_BGR_P = 1,
|
||||
MODE_RGB_S = 2,
|
||||
MODE_BGR_S = 3,
|
||||
};
|
||||
|
||||
enum exynos_cpu_auto_cmd_rate {
|
||||
DISABLE_AUTO_FRM,
|
||||
PER_TWO_FRM,
|
||||
PER_FOUR_FRM,
|
||||
PER_SIX_FRM,
|
||||
PER_EIGHT_FRM,
|
||||
PER_TEN_FRM,
|
||||
PER_TWELVE_FRM,
|
||||
PER_FOURTEEN_FRM,
|
||||
PER_SIXTEEN_FRM,
|
||||
PER_EIGHTEEN_FRM,
|
||||
PER_TWENTY_FRM,
|
||||
PER_TWENTY_TWO_FRM,
|
||||
PER_TWENTY_FOUR_FRM,
|
||||
PER_TWENTY_SIX_FRM,
|
||||
PER_TWENTY_EIGHT_FRM,
|
||||
PER_THIRTY_FRM,
|
||||
};
|
||||
|
||||
void exynos_fimd_lcd_init_mem(unsigned long screen_base, unsigned long fb_size,
|
||||
unsigned long palette_size);
|
||||
void exynos_fimd_lcd_init(vidinfo_t *vid);
|
||||
unsigned long exynos_fimd_calc_fbsize(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,354 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Samsung Electronics
|
||||
*
|
||||
* Author: InKi Dae <inki.dae@samsung.com>
|
||||
* Author: Donghwa Lee <dh09.lee@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <lcd.h>
|
||||
#include <div64.h>
|
||||
#include <asm/arch/clk.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include "exynos_fb.h"
|
||||
|
||||
static unsigned long *lcd_base_addr;
|
||||
static vidinfo_t *pvid;
|
||||
|
||||
void exynos_fimd_lcd_init_mem(u_long screen_base, u_long fb_size,
|
||||
u_long palette_size)
|
||||
{
|
||||
lcd_base_addr = (unsigned long *)screen_base;
|
||||
}
|
||||
|
||||
static void exynos_fimd_set_dualrgb(unsigned int enabled)
|
||||
{
|
||||
struct exynos4_fb *fimd_ctrl =
|
||||
(struct exynos4_fb *)samsung_get_base_fimd();
|
||||
unsigned int cfg = 0;
|
||||
|
||||
if (enabled) {
|
||||
cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT |
|
||||
EXYNOS_DUALRGB_VDEN_EN_ENABLE;
|
||||
|
||||
/* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
|
||||
cfg |= EXYNOS_DUALRGB_SUB_CNT(pvid->vl_col / 2) |
|
||||
EXYNOS_DUALRGB_MAIN_CNT(0);
|
||||
}
|
||||
|
||||
writel(cfg, &fimd_ctrl->dualrgb);
|
||||
}
|
||||
|
||||
static void exynos_fimd_set_par(unsigned int win_id)
|
||||
{
|
||||
unsigned int cfg = 0;
|
||||
struct exynos4_fb *fimd_ctrl =
|
||||
(struct exynos4_fb *)samsung_get_base_fimd();
|
||||
|
||||
/* set window control */
|
||||
cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
|
||||
EXYNOS_WINCON(win_id));
|
||||
|
||||
cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE |
|
||||
EXYNOS_WINCON_HAWSWP_ENABLE | EXYNOS_WINCON_WSWP_ENABLE |
|
||||
EXYNOS_WINCON_BURSTLEN_MASK | EXYNOS_WINCON_BPPMODE_MASK |
|
||||
EXYNOS_WINCON_INRGB_MASK | EXYNOS_WINCON_DATAPATH_MASK);
|
||||
|
||||
/* DATAPATH is DMA */
|
||||
cfg |= EXYNOS_WINCON_DATAPATH_DMA;
|
||||
|
||||
/* bpp is 32 */
|
||||
cfg |= EXYNOS_WINCON_WSWP_ENABLE;
|
||||
|
||||
/* dma burst is 16 */
|
||||
cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
|
||||
|
||||
/* pixel format is unpacked RGB888 */
|
||||
cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
|
||||
|
||||
writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
|
||||
EXYNOS_WINCON(win_id));
|
||||
|
||||
/* set window position to x=0, y=0*/
|
||||
cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0);
|
||||
writel(cfg, (unsigned int)&fimd_ctrl->vidosd0a +
|
||||
EXYNOS_VIDOSD(win_id));
|
||||
|
||||
cfg = EXYNOS_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
|
||||
EXYNOS_VIDOSD_BOTTOM_Y(pvid->vl_row - 1);
|
||||
writel(cfg, (unsigned int)&fimd_ctrl->vidosd0b +
|
||||
EXYNOS_VIDOSD(win_id));
|
||||
|
||||
/* set window size for window0*/
|
||||
cfg = EXYNOS_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
|
||||
writel(cfg, (unsigned int)&fimd_ctrl->vidosd0c +
|
||||
EXYNOS_VIDOSD(win_id));
|
||||
}
|
||||
|
||||
static void exynos_fimd_set_buffer_address(unsigned int win_id)
|
||||
{
|
||||
unsigned long start_addr, end_addr;
|
||||
struct exynos4_fb *fimd_ctrl =
|
||||
(struct exynos4_fb *)samsung_get_base_fimd();
|
||||
|
||||
start_addr = (unsigned long)lcd_base_addr;
|
||||
end_addr = start_addr + ((pvid->vl_col * (pvid->vl_bpix / 8)) *
|
||||
pvid->vl_row);
|
||||
|
||||
writel(start_addr, (unsigned int)&fimd_ctrl->vidw00add0b0 +
|
||||
EXYNOS_BUFFER_OFFSET(win_id));
|
||||
writel(end_addr, (unsigned int)&fimd_ctrl->vidw00add1b0 +
|
||||
EXYNOS_BUFFER_OFFSET(win_id));
|
||||
}
|
||||
|
||||
static void exynos_fimd_set_clock(vidinfo_t *pvid)
|
||||
{
|
||||
unsigned int cfg = 0, div = 0, remainder, remainder_div;
|
||||
unsigned long pixel_clock;
|
||||
unsigned long long src_clock;
|
||||
struct exynos4_fb *fimd_ctrl =
|
||||
(struct exynos4_fb *)samsung_get_base_fimd();
|
||||
|
||||
if (pvid->dual_lcd_enabled) {
|
||||
pixel_clock = pvid->vl_freq *
|
||||
(pvid->vl_hspw + pvid->vl_hfpd +
|
||||
pvid->vl_hbpd + pvid->vl_col / 2) *
|
||||
(pvid->vl_vspw + pvid->vl_vfpd +
|
||||
pvid->vl_vbpd + pvid->vl_row);
|
||||
} else if (pvid->interface_mode == FIMD_CPU_INTERFACE) {
|
||||
pixel_clock = pvid->vl_freq *
|
||||
pvid->vl_width * pvid->vl_height *
|
||||
(pvid->cs_setup + pvid->wr_setup +
|
||||
pvid->wr_act + pvid->wr_hold + 1);
|
||||
} else {
|
||||
pixel_clock = pvid->vl_freq *
|
||||
(pvid->vl_hspw + pvid->vl_hfpd +
|
||||
pvid->vl_hbpd + pvid->vl_col) *
|
||||
(pvid->vl_vspw + pvid->vl_vfpd +
|
||||
pvid->vl_vbpd + pvid->vl_row);
|
||||
}
|
||||
|
||||
cfg = readl(&fimd_ctrl->vidcon0);
|
||||
cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK |
|
||||
EXYNOS_VIDCON0_CLKVAL_F(0xFF) | EXYNOS_VIDCON0_VCLKEN_MASK |
|
||||
EXYNOS_VIDCON0_CLKDIR_MASK);
|
||||
cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS |
|
||||
EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED);
|
||||
|
||||
if (pixel_clock > MAX_CLOCK)
|
||||
pixel_clock = MAX_CLOCK;
|
||||
|
||||
src_clock = (unsigned long long) get_lcd_clk();
|
||||
|
||||
/* get quotient and remainder. */
|
||||
remainder = do_div(src_clock, pixel_clock);
|
||||
div = src_clock;
|
||||
|
||||
remainder *= 10;
|
||||
remainder_div = remainder / pixel_clock;
|
||||
|
||||
/* round about one places of decimals. */
|
||||
if (remainder_div >= 5)
|
||||
div++;
|
||||
|
||||
/* in case of dual lcd mode. */
|
||||
if (pvid->dual_lcd_enabled)
|
||||
div--;
|
||||
|
||||
cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1);
|
||||
writel(cfg, &fimd_ctrl->vidcon0);
|
||||
}
|
||||
|
||||
void exynos_set_trigger(void)
|
||||
{
|
||||
unsigned int cfg = 0;
|
||||
struct exynos4_fb *fimd_ctrl =
|
||||
(struct exynos4_fb *)samsung_get_base_fimd();
|
||||
|
||||
cfg = readl(&fimd_ctrl->trigcon);
|
||||
|
||||
cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG);
|
||||
|
||||
writel(cfg, &fimd_ctrl->trigcon);
|
||||
}
|
||||
|
||||
int exynos_is_i80_frame_done(void)
|
||||
{
|
||||
unsigned int cfg = 0;
|
||||
int status;
|
||||
struct exynos4_fb *fimd_ctrl =
|
||||
(struct exynos4_fb *)samsung_get_base_fimd();
|
||||
|
||||
cfg = readl(&fimd_ctrl->trigcon);
|
||||
|
||||
/* frame done func is valid only when TRIMODE[0] is set to 1. */
|
||||
status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) ==
|
||||
EXYNOS_I80STATUS_TRIG_DONE;
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static void exynos_fimd_lcd_on(void)
|
||||
{
|
||||
unsigned int cfg = 0;
|
||||
struct exynos4_fb *fimd_ctrl =
|
||||
(struct exynos4_fb *)samsung_get_base_fimd();
|
||||
|
||||
/* display on */
|
||||
cfg = readl(&fimd_ctrl->vidcon0);
|
||||
cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE);
|
||||
writel(cfg, &fimd_ctrl->vidcon0);
|
||||
}
|
||||
|
||||
static void exynos_fimd_window_on(unsigned int win_id)
|
||||
{
|
||||
unsigned int cfg = 0;
|
||||
struct exynos4_fb *fimd_ctrl =
|
||||
(struct exynos4_fb *)samsung_get_base_fimd();
|
||||
|
||||
/* enable window */
|
||||
cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
|
||||
EXYNOS_WINCON(win_id));
|
||||
cfg |= EXYNOS_WINCON_ENWIN_ENABLE;
|
||||
writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
|
||||
EXYNOS_WINCON(win_id));
|
||||
|
||||
cfg = readl(&fimd_ctrl->winshmap);
|
||||
cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id);
|
||||
writel(cfg, &fimd_ctrl->winshmap);
|
||||
}
|
||||
|
||||
void exynos_fimd_lcd_off(void)
|
||||
{
|
||||
unsigned int cfg = 0;
|
||||
struct exynos4_fb *fimd_ctrl =
|
||||
(struct exynos4_fb *)samsung_get_base_fimd();
|
||||
|
||||
cfg = readl(&fimd_ctrl->vidcon0);
|
||||
cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE);
|
||||
writel(cfg, &fimd_ctrl->vidcon0);
|
||||
}
|
||||
|
||||
void exynos_fimd_window_off(unsigned int win_id)
|
||||
{
|
||||
unsigned int cfg = 0;
|
||||
struct exynos4_fb *fimd_ctrl =
|
||||
(struct exynos4_fb *)samsung_get_base_fimd();
|
||||
|
||||
cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
|
||||
EXYNOS_WINCON(win_id));
|
||||
cfg &= EXYNOS_WINCON_ENWIN_DISABLE;
|
||||
writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
|
||||
EXYNOS_WINCON(win_id));
|
||||
|
||||
cfg = readl(&fimd_ctrl->winshmap);
|
||||
cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id);
|
||||
writel(cfg, &fimd_ctrl->winshmap);
|
||||
}
|
||||
|
||||
void exynos_fimd_lcd_init(vidinfo_t *vid)
|
||||
{
|
||||
unsigned int cfg = 0, rgb_mode;
|
||||
struct exynos4_fb *fimd_ctrl =
|
||||
(struct exynos4_fb *)samsung_get_base_fimd();
|
||||
|
||||
/* store panel info to global variable */
|
||||
pvid = vid;
|
||||
|
||||
rgb_mode = MODE_RGB_P;
|
||||
|
||||
if (vid->interface_mode == FIMD_RGB_INTERFACE) {
|
||||
cfg |= EXYNOS_VIDCON0_VIDOUT_RGB;
|
||||
writel(cfg, &fimd_ctrl->vidcon0);
|
||||
|
||||
cfg = readl(&fimd_ctrl->vidcon2);
|
||||
cfg &= ~(EXYNOS_VIDCON2_WB_MASK |
|
||||
EXYNOS_VIDCON2_TVFORMATSEL_MASK |
|
||||
EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK);
|
||||
cfg |= EXYNOS_VIDCON2_WB_DISABLE;
|
||||
writel(cfg, &fimd_ctrl->vidcon2);
|
||||
|
||||
/* set polarity */
|
||||
cfg = 0;
|
||||
if (!pvid->vl_clkp)
|
||||
cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE;
|
||||
if (!pvid->vl_hsp)
|
||||
cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT;
|
||||
if (!pvid->vl_vsp)
|
||||
cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT;
|
||||
if (!pvid->vl_dp)
|
||||
cfg |= EXYNOS_VIDCON1_IVDEN_INVERT;
|
||||
|
||||
writel(cfg, &fimd_ctrl->vidcon1);
|
||||
|
||||
/* set timing */
|
||||
cfg = EXYNOS_VIDTCON0_VFPD(pvid->vl_vfpd - 1);
|
||||
cfg |= EXYNOS_VIDTCON0_VBPD(pvid->vl_vbpd - 1);
|
||||
cfg |= EXYNOS_VIDTCON0_VSPW(pvid->vl_vspw - 1);
|
||||
writel(cfg, &fimd_ctrl->vidtcon0);
|
||||
|
||||
cfg = EXYNOS_VIDTCON1_HFPD(pvid->vl_hfpd - 1);
|
||||
cfg |= EXYNOS_VIDTCON1_HBPD(pvid->vl_hbpd - 1);
|
||||
cfg |= EXYNOS_VIDTCON1_HSPW(pvid->vl_hspw - 1);
|
||||
|
||||
writel(cfg, &fimd_ctrl->vidtcon1);
|
||||
|
||||
/* set lcd size */
|
||||
cfg = EXYNOS_VIDTCON2_HOZVAL(pvid->vl_col - 1);
|
||||
cfg |= EXYNOS_VIDTCON2_LINEVAL(pvid->vl_row - 1);
|
||||
|
||||
writel(cfg, &fimd_ctrl->vidtcon2);
|
||||
}
|
||||
|
||||
/* set display mode */
|
||||
cfg = readl(&fimd_ctrl->vidcon0);
|
||||
cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK;
|
||||
cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT);
|
||||
writel(cfg, &fimd_ctrl->vidcon0);
|
||||
|
||||
/* set par */
|
||||
exynos_fimd_set_par(pvid->win_id);
|
||||
|
||||
/* set memory address */
|
||||
exynos_fimd_set_buffer_address(pvid->win_id);
|
||||
|
||||
/* set buffer size */
|
||||
cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * pvid->vl_bpix / 8);
|
||||
writel(cfg, (unsigned int)&fimd_ctrl->vidw00add2 +
|
||||
EXYNOS_BUFFER_SIZE(pvid->win_id));
|
||||
|
||||
/* set clock */
|
||||
exynos_fimd_set_clock(pvid);
|
||||
|
||||
/* set rgb mode to dual lcd. */
|
||||
exynos_fimd_set_dualrgb(pvid->dual_lcd_enabled);
|
||||
|
||||
/* display on */
|
||||
exynos_fimd_lcd_on();
|
||||
|
||||
/* window on */
|
||||
exynos_fimd_window_on(pvid->win_id);
|
||||
}
|
||||
|
||||
unsigned long exynos_fimd_calc_fbsize(void)
|
||||
{
|
||||
return pvid->vl_col * pvid->vl_row * (pvid->vl_bpix / 8);
|
||||
}
|
||||
Loading…
Reference in New Issue