i.MX: declare iomux_v3_cfg_t arrays as const
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
This commit is contained in:
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5ae28d2db2
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6e14232010
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@ -54,12 +54,12 @@ int dram_init(void)
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return 0;
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}
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iomux_v3_cfg_t uart4_pads[] = {
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iomux_v3_cfg_t const uart4_pads[] = {
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MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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iomux_v3_cfg_t usdhc3_pads[] = {
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iomux_v3_cfg_t const usdhc3_pads[] = {
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MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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@ -73,7 +73,7 @@ iomux_v3_cfg_t usdhc3_pads[] = {
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MX6Q_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
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};
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iomux_v3_cfg_t usdhc4_pads[] = {
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iomux_v3_cfg_t const usdhc4_pads[] = {
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MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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@ -86,7 +86,7 @@ iomux_v3_cfg_t usdhc4_pads[] = {
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MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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iomux_v3_cfg_t enet_pads[] = {
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iomux_v3_cfg_t const enet_pads[] = {
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MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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@ -53,12 +53,12 @@ int dram_init(void)
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return 0;
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}
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iomux_v3_cfg_t uart4_pads[] = {
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iomux_v3_cfg_t const uart4_pads[] = {
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MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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iomux_v3_cfg_t enet_pads[] = {
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iomux_v3_cfg_t const enet_pads[] = {
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MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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@ -81,7 +81,7 @@ static void setup_iomux_enet(void)
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imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
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}
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iomux_v3_cfg_t usdhc3_pads[] = {
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iomux_v3_cfg_t const usdhc3_pads[] = {
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MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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@ -70,12 +70,12 @@ int dram_init(void)
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return 0;
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}
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iomux_v3_cfg_t uart1_pads[] = {
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iomux_v3_cfg_t const uart1_pads[] = {
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MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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iomux_v3_cfg_t uart2_pads[] = {
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iomux_v3_cfg_t const uart2_pads[] = {
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MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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@ -124,7 +124,7 @@ struct i2c_pads_info i2c_pad_info2 = {
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}
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};
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iomux_v3_cfg_t usdhc3_pads[] = {
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iomux_v3_cfg_t const usdhc3_pads[] = {
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MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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@ -134,7 +134,7 @@ iomux_v3_cfg_t usdhc3_pads[] = {
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MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
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};
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iomux_v3_cfg_t usdhc4_pads[] = {
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iomux_v3_cfg_t const usdhc4_pads[] = {
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MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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@ -144,7 +144,7 @@ iomux_v3_cfg_t usdhc4_pads[] = {
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MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
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};
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iomux_v3_cfg_t enet_pads1[] = {
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iomux_v3_cfg_t const enet_pads1[] = {
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MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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@ -170,7 +170,7 @@ iomux_v3_cfg_t enet_pads1[] = {
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MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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iomux_v3_cfg_t enet_pads2[] = {
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iomux_v3_cfg_t const enet_pads2[] = {
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MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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@ -180,7 +180,7 @@ iomux_v3_cfg_t enet_pads2[] = {
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};
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/* Button assignments for J14 */
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static iomux_v3_cfg_t button_pads[] = {
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static iomux_v3_cfg_t const button_pads[] = {
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/* Menu */
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MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
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/* Back */
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@ -213,7 +213,7 @@ static void setup_iomux_enet(void)
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imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
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}
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iomux_v3_cfg_t usb_pads[] = {
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iomux_v3_cfg_t const usb_pads[] = {
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MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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@ -297,7 +297,7 @@ u32 get_board_rev(void)
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}
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#ifdef CONFIG_MXC_SPI
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iomux_v3_cfg_t ecspi1_pads[] = {
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iomux_v3_cfg_t const ecspi1_pads[] = {
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/* SS1 */
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MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
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@ -51,12 +51,12 @@ int dram_init(void)
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return 0;
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}
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iomux_v3_cfg_t uart1_pads[] = {
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iomux_v3_cfg_t const uart1_pads[] = {
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MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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iomux_v3_cfg_t enet_pads[] = {
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iomux_v3_cfg_t const enet_pads[] = {
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MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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@ -86,7 +86,7 @@ static void setup_iomux_enet(void)
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gpio_set_value(IMX_GPIO_NR(1, 25), 1);
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}
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iomux_v3_cfg_t usdhc3_pads[] = {
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iomux_v3_cfg_t const usdhc3_pads[] = {
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MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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@ -94,7 +94,7 @@ static u32 get_mx_rev(void)
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return (~rev & 0x7) + 1;
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}
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static iomux_v3_cfg_t efikasb_revision_pads[] = {
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static iomux_v3_cfg_t const efikasb_revision_pads[] = {
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MX51_PAD_EIM_CS3__GPIO2_28,
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MX51_PAD_EIM_CS4__GPIO2_29,
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};
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@ -141,7 +141,7 @@ int dram_init(void)
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/*
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* UART configuration
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*/
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static iomux_v3_cfg_t efikamx_uart_pads[] = {
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static iomux_v3_cfg_t const efikamx_uart_pads[] = {
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MX51_PAD_UART1_RXD__UART1_RXD,
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MX51_PAD_UART1_TXD__UART1_TXD,
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MX51_PAD_UART1_RTS__UART1_RTS,
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@ -151,7 +151,7 @@ static iomux_v3_cfg_t efikamx_uart_pads[] = {
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/*
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* SPI configuration
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*/
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static iomux_v3_cfg_t efikamx_spi_pads[] = {
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static iomux_v3_cfg_t const efikamx_spi_pads[] = {
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MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
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MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
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MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
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@ -273,7 +273,7 @@ struct fsl_esdhc_cfg esdhc_cfg[2] = {
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{MMC_SDHC2_BASE_ADDR},
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};
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static iomux_v3_cfg_t efikamx_sdhc1_pads[] = {
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static iomux_v3_cfg_t const efikamx_sdhc1_pads[] = {
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MX51_PAD_SD1_CMD__SD1_CMD,
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MX51_PAD_SD1_CLK__SD1_CLK,
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MX51_PAD_SD1_DATA0__SD1_DATA0,
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@ -285,7 +285,7 @@ static iomux_v3_cfg_t efikamx_sdhc1_pads[] = {
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#define EFIKAMX_SDHC1_WP IMX_GPIO_NR(1, 1)
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static iomux_v3_cfg_t efikamx_sdhc1_cd_pads[] = {
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static iomux_v3_cfg_t const efikamx_sdhc1_cd_pads[] = {
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MX51_PAD_GPIO1_0__SD1_CD,
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MX51_PAD_EIM_CS2__SD1_CD,
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};
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@ -293,7 +293,7 @@ static iomux_v3_cfg_t efikamx_sdhc1_cd_pads[] = {
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#define EFIKAMX_SDHC1_CD IMX_GPIO_NR(1, 0)
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#define EFIKASB_SDHC1_CD IMX_GPIO_NR(2, 27)
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static iomux_v3_cfg_t efikasb_sdhc2_pads[] = {
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static iomux_v3_cfg_t const efikasb_sdhc2_pads[] = {
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MX51_PAD_SD2_CMD__SD2_CMD,
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MX51_PAD_SD2_CLK__SD2_CLK,
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MX51_PAD_SD2_DATA0__SD2_DATA0,
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@ -372,7 +372,7 @@ int board_mmc_init(bd_t *bis)
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/*
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* PATA
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*/
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static iomux_v3_cfg_t efikamx_pata_pads[] = {
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static iomux_v3_cfg_t const efikamx_pata_pads[] = {
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MX51_PAD_NANDF_WE_B__PATA_DIOW,
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MX51_PAD_NANDF_RE_B__PATA_DIOR,
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MX51_PAD_NANDF_ALE__PATA_BUFFER_EN,
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@ -423,7 +423,7 @@ static inline void setup_iomux_usb(void) { }
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#define EFIKAMX_LED_GREEN IMX_GPIO_NR(3, 14)
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#define EFIKAMX_LED_RED IMX_GPIO_NR(3, 15)
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static iomux_v3_cfg_t efikasb_led_pads[] = {
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static iomux_v3_cfg_t const efikasb_led_pads[] = {
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MX51_PAD_GPIO1_3__GPIO1_3,
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MX51_PAD_EIM_CS0__GPIO2_25,
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};
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