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x86: Add SPI support to quark/galileo 

The Quark SoC contains a legacy SPI controller in the legacy bridge
which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS
control register offset in the ICH SPI driver is wrong for the Quark
SoC too, unprotect_spi_flash() is added to enable the flash write.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng 2015-02-04 16:26:12 +08:00 committed by Simon Glass
parent 38fc1cdae0
commit 728b393f3b
3 changed files with 32 additions and 1 deletions
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17
arch/x86/cpu/quark/quark.c
View File

@ -13,6 +13,21 @@
#include <asm/arch/msg_port.h>
#include <asm/arch/quark.h>
/*
* TODO:
*
* This whole routine should be removed until we fully convert the ICH SPI
* driver to DM and make use of DT to pass the bios control register offset
*/
static void unprotect_spi_flash(void)
{
u32 bc;
bc = pci_read_config32(QUARK_LEGACY_BRIDGE, 0xd8);
bc |= 0x1; /* unprotect the flash */
pci_write_config32(QUARK_LEGACY_BRIDGE, 0xd8, bc);
}
static void quark_setup_bars(void)
{
/* GPIO - D31:F0:R44h */
@ -74,6 +89,8 @@ int arch_cpu_init(void)
*/
quark_setup_bars();
unprotect_spi_flash();
return 0;
}

13
arch/x86/dts/galileo.dts
View File

@ -79,4 +79,17 @@
bank-name = "B";
};
spi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich-spi";
spi-flash@0 {
#size-cells = <1>;
#address-cells = <1>;
reg = <0>;
compatible = "winbond,w25q64", "spi-flash";
memory-map = <0xff800000 0x00800000>;
};
};
};

3
drivers/spi/ich.c
View File

@ -177,7 +177,8 @@ void spi_free_slave(struct spi_slave *slave)
static int get_ich_version(uint16_t device_id)
{
if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC ||
device_id == PCI_DEVICE_ID_INTEL_ITC_LPC)
device_id == PCI_DEVICE_ID_INTEL_ITC_LPC ||
device_id == PCI_DEVICE_ID_INTEL_QRK_ILB)
return 7;
if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&