dm: usb: Refactor EHCI init
Move the bulk of the code in usb_lowlevel_init() into a separate function which will also be used by driver model. Keep the CONFIG options out of this function by providing a tweak flag for Faraday. We need to avoid using CONFIG options in driver model code where possible, since it makes it impossible to use multiple controllers in that code where they have different options. The CONFIG_EHCI_HCD_INIT_AFTER_RESET option is also kept out of the common init function. With driver model the controller will be able to perform this extra init itself after registering with the EHCI layer. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Simon Glass
parent
24ed894fc0
commit
7372b5bd31
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@ -945,41 +945,19 @@ void *ehci_get_controller_priv(int index)
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return ehcic[index].priv;
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}
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int usb_lowlevel_stop(int index)
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static int ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks)
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{
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ehci_shutdown(&ehcic[index]);
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return ehci_hcd_stop(index);
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}
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int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
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{
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uint32_t reg;
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uint32_t cmd;
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struct QH *qh_list;
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struct QH *periodic;
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uint32_t reg;
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uint32_t cmd;
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int i;
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int rc;
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rc = ehci_hcd_init(index, init, &ehcic[index].hccr, &ehcic[index].hcor);
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if (rc)
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return rc;
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if (init == USB_INIT_DEVICE)
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goto done;
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/* EHCI spec section 4.1 */
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if (ehci_reset(index))
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return -1;
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#if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
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rc = ehci_hcd_init(index, init, &ehcic[index].hccr, &ehcic[index].hcor);
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if (rc)
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return rc;
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#endif
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/* Set the high address word (aka segment) for 64-bit controller */
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if (ehci_readl(&ehcic[index].hccr->cr_hccparams) & 1)
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ehci_writel(&ehcic[index].hcor->or_ctrldssegment, 0);
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if (ehci_readl(&ctrl->hccr->cr_hccparams) & 1)
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ehci_writel(&ctrl->hcor->or_ctrldssegment, 0);
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qh_list = &ehcic[index].qh_list;
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qh_list = &ctrl->qh_list;
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/* Set head of reclaim list */
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memset(qh_list, 0, sizeof(*qh_list));
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@ -995,14 +973,14 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
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ALIGN_END_ADDR(struct QH, qh_list, 1));
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/* Set async. queue head pointer. */
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ehci_writel(&ehcic[index].hcor->or_asynclistaddr, (unsigned long)qh_list);
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ehci_writel(&ctrl->hcor->or_asynclistaddr, (unsigned long)qh_list);
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/*
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* Set up periodic list
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* Step 1: Parent QH for all periodic transfers.
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*/
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ehcic[index].periodic_schedules = 0;
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periodic = &ehcic[index].periodic_queue;
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ctrl->periodic_schedules = 0;
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periodic = &ctrl->periodic_queue;
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memset(periodic, 0, sizeof(*periodic));
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periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
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periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
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@ -1020,25 +998,25 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
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* Split Transactions will be spread across microframes using
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* S-mask and C-mask.
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*/
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if (ehcic[index].periodic_list == NULL)
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ehcic[index].periodic_list = memalign(4096, 1024 * 4);
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if (ctrl->periodic_list == NULL)
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ctrl->periodic_list = memalign(4096, 1024 * 4);
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if (!ehcic[index].periodic_list)
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if (!ctrl->periodic_list)
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return -ENOMEM;
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for (i = 0; i < 1024; i++) {
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ehcic[index].periodic_list[i] = cpu_to_hc32((unsigned long)periodic
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ctrl->periodic_list[i] = cpu_to_hc32((unsigned long)periodic
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| QH_LINK_TYPE_QH);
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}
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flush_dcache_range((unsigned long)ehcic[index].periodic_list,
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ALIGN_END_ADDR(uint32_t, ehcic[index].periodic_list,
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flush_dcache_range((unsigned long)ctrl->periodic_list,
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ALIGN_END_ADDR(uint32_t, ctrl->periodic_list,
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1024));
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/* Set periodic list base address */
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ehci_writel(&ehcic[index].hcor->or_periodiclistbase,
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(unsigned long)ehcic[index].periodic_list);
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ehci_writel(&ctrl->hcor->or_periodiclistbase,
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(unsigned long)ctrl->periodic_list);
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reg = ehci_readl(&ehcic[index].hccr->cr_hcsparams);
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reg = ehci_readl(&ctrl->hccr->cr_hcsparams);
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descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
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debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
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/* Port Indicators */
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@ -1051,29 +1029,66 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
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| 0x01, &descriptor.hub.wHubCharacteristics);
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/* Start the host controller. */
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cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
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cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
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/*
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* Philips, Intel, and maybe others need CMD_RUN before the
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* root hub will detect new devices (why?); NEC doesn't
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*/
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cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
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cmd |= CMD_RUN;
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ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd);
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ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
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#ifndef CONFIG_USB_EHCI_FARADAY
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/* take control over the ports */
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cmd = ehci_readl(&ehcic[index].hcor->or_configflag);
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cmd |= FLAG_CF;
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ehci_writel(&ehcic[index].hcor->or_configflag, cmd);
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#endif
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if (!(tweaks & EHCI_TWEAK_NO_INIT_CF)) {
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/* take control over the ports */
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cmd = ehci_readl(&ctrl->hcor->or_configflag);
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cmd |= FLAG_CF;
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ehci_writel(&ctrl->hcor->or_configflag, cmd);
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}
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/* unblock posted write */
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cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
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cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
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mdelay(5);
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reg = HC_VERSION(ehci_readl(&ehcic[index].hccr->cr_capbase));
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reg = HC_VERSION(ehci_readl(&ctrl->hccr->cr_capbase));
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printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
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ehcic[index].rootdev = 0;
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return 0;
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}
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int usb_lowlevel_stop(int index)
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{
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ehci_shutdown(&ehcic[index]);
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return ehci_hcd_stop(index);
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}
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int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
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{
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struct ehci_ctrl *ctrl = &ehcic[index];
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uint tweaks = 0;
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int rc;
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rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
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if (rc)
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return rc;
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if (init == USB_INIT_DEVICE)
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goto done;
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/* EHCI spec section 4.1 */
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if (ehci_reset(index))
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return -1;
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#if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
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rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
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if (rc)
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return rc;
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#endif
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#ifdef CONFIG_USB_EHCI_FARADAY
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tweaks |= EHCI_TWEAK_NO_INIT_CF;
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#endif
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rc = ehci_common_init(ctrl, tweaks);
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if (rc)
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return rc;
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ctrl->rootdev = 0;
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done:
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*controller = &ehcic[index];
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return 0;
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@ -238,6 +238,12 @@ struct QH {
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};
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};
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/* Tweak flags for EHCI, used to control operation */
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enum {
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/* don't use or_configflag in init */
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EHCI_TWEAK_NO_INIT_CF = 1 << 0,
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};
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struct ehci_ctrl {
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struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
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struct ehci_hcor *hcor;
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