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arm: socfpga: set skew settings for ethernet phy 

Set the PHY skew settings for the ethernet phy on the SOCFPGA Cyclone5
hardware.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Dinh Nguyen 2014-11-13 11:23:41 -06:00 committed by Marek Vasut
parent fa8278d702
commit 74ae12e184
1 changed files with 16 additions and 0 deletions
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16
board/altera/socfpga/socfpga_cyclone5.c
View File

@ -12,7 +12,9 @@
#include <usb/s3c_udc.h>
#include <usb_mass_storage.h>
#include <micrel.h>
#include <netdev.h>
#include <phy.h>
DECLARE_GLOBAL_DATA_PTR;
@ -44,6 +46,20 @@ int board_init(void)
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
/*
* These skew settings for the KSZ9021 ethernet phy is required for ethernet
* to work reliably on most flavors of cyclone5 boards.
*/
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
0x0);
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
0x0);
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
0xf0f0);
}
#ifdef CONFIG_USB_GADGET
struct s3c_plat_otg_data socfpga_otg_data = {
.regs_otg = CONFIG_USB_DWC2_REG_ADDR,