Merge branch 'master' of git://git.denx.de/u-boot

This commit is contained in:
Kim Phillips 2009-02-19 11:06:58 -06:00
commit 7511835b29
129 changed files with 2687 additions and 615 deletions

786
CHANGELOG
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@ -1,3 +1,789 @@
commit 369d0aa9674b65c83f8553b9bcf9d207dc369223
Author: Kim Phillips <kim.phillips@freescale.com>
Date: Wed Feb 18 17:43:59 2009 -0600
sata_sil3114: fix compiler warning
judging from other printfs in the same file, it seems ata should be
postpended with the interface number, not the address of the global
port variable. Fixes this for current u-boot-mpc83xx tree:
Configuring for MPC8349ITX board...
sata_sil3114.c: In function 'sata_bus_softreset':
sata_sil3114.c:99: warning: format '%u' expects type 'unsigned int', but argument 2 has type 'struct sata_port *'
sata_sil3114.c:108: warning: format '%u' expects type 'unsigned int', but argument 2 has type 'struct sata_port *'
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
commit f5675aa5ceeef30740970ab8ca0c8cbc324945cd
Author: Ron Madrid <ron_madrid@sbcglobal.net>
Date: Wed Feb 18 14:30:44 2009 -0800
Create configuration option for restricted ns16550 functions
This patch will create a configuration option for a minimum configuration for
the ns16550 serial driver at drivers/serial/ns16550.c and will apply this new
configuration option to the SIMPC8313.h config file in order to fix the NAND
bootstrap build error. This option will exclude all functions with exception of
NS16550_putc and NS16550_init. This will be used primarily to save space and
remove unused code from builds in which space is limited.
Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
commit 7b0bc0219db8981613259473cf19699ac259b4fb
Author: Kim Phillips <kim.phillips@freescale.com>
Date: Wed Feb 18 16:14:29 2009 -0600
mkconfig: include board config.h before asm/config.h
swapping the include order suppresses warnings for board configs
that define their own CONFIG_MAX_MEM_MAPPED:
In file included from /home/r1aaha/git/u-boot/include/config.h:5,
from /home/r1aaha/git/u-boot/include/common.h:35,
from simpc8313.c:26:
/home/r1aaha/git/u-boot/include/configs/SIMPC8313.h:81:1: warning:
"CONFIG_MAX_MEM_MAPPED" redefined
In file included from /home/r1aaha/git/u-boot/include/config.h:4,
from /home/r1aaha/git/u-boot/include/common.h:35,
from simpc8313.c:26:
/home/r1aaha/git/u-boot/include/asm/config.h:28:1: warning: this is
the location of the previous definition
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
commit b8845abdc0dcf20d0944e965153f5ae7a9c3077c
Author: Wolfgang Denk <wd@denx.de>
Date: Wed Feb 18 21:35:38 2009 +0100
Fix build errors after making flash_get_info() non-static
Fix for these build problems:
error: static declaration of 'flash_get_info' follows non-static declaration
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 5f0320108870e5d62983d1d5c13a2a087dddf686
Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sun Feb 1 17:07:52 2009 +0100
common/console: avoid ifdef CONFIG_CONSOLE_MUX when it's possible
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
commit ec6f14994602276660f7264c6ab3b91ef1f7614d
Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sun Feb 1 17:07:51 2009 +0100
common/console: coding style cleanup
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
commit daaf74f176b548dfd34a9990231f4189201d57ba
Author: Mike Frysinger <vapier@gentoo.org>
Date: Thu Jan 29 20:02:23 2009 -0500
mpc8xx_pcmcia: move CONFIG_8xx out of .c file and into Makefile
Move the CONFIG_8xx mpc8xx_pcmcia.c protection out of the C file and
into the Makefile so we avoid pointless compiling of the file.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit 7bd2722e890bc877a3c057d7ccddc80451c99939
Author: Mike Frysinger <vapier@gentoo.org>
Date: Thu Jan 29 20:02:07 2009 -0500
disk: convert part_* files to COBJ-$(CONFIG_XXX) style
Move the CONFIG_XXX out of the part_XXX.c file and into Makefile to
avoid pointless compiles.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit f05fa9205e04986176dc7ab8b710bcb5fbe9f338
Author: Petri Lehtinen <petri.lehtinen@inoi.fi>
Date: Thu Jan 29 10:35:40 2009 +0200
include/image.h: Ease grepping of image_* functions
Because the functions have been defined using macros, grepping for
their definitions is not possible. This patch adds the real function
names in comments.
Signed-off-by: Petri Lehtinen <petri.lehtinen@inoi.fi>
Acked-by: Mike Frysinger <vapier@gentoo.org>
commit bdab39d358e63aa47f400a8a76b8d5f283842df3
Author: Mike Frysinger <vapier@gentoo.org>
Date: Wed Jan 28 19:08:14 2009 -0500
rename CONFIG_CMD_ENV to CONFIG_CMD_SAVEENV
The CONFIG_CMD_ENV option controls enablement of the `saveenv` command
rather than a generic "env" command, or anything else related to the
environment. So, let's make sure the define is named accordingly.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit 8b0592b89e0f9f81c9e150c81d96f8a43e4d6101
Author: Valeriy Glushkov <gvv@lstec.com>
Date: Fri Jan 23 20:02:17 2009 +0200
disable imls command if no flash is defined
Default CONFIG_CMD_IMLS must be disabled when CONFIG_SYS_NO_FLASH is defined
Signed-off-by: Valeriy Glushkov <gvv@lstec.com>
commit 923aa48126259c13de95131203f1d28bfa5cb889
Author: Rafal Jaworowski <raj@semihalf.com>
Date: Fri Jan 23 13:27:18 2009 +0100
API: Improve glue mid-layer of the API demo application.
- Extend ub_dev_read() and ub_dev_recv() so they return the length actually
read, which allows for better control and error handling (this introduces
additional error code API_ESYSC returned by the glue mid-layer).
- Clean up definitions naming and usage.
- Other minor cosmetics.
Note these changes do not touch the API proper, so the interface between
U-Boot and standalone applications remains unchanged.
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
commit 44a94e596ba0f6d0951b165403c520bf55b1c56f
Author: Rafal Jaworowski <raj@semihalf.com>
Date: Fri Jan 23 13:27:17 2009 +0100
API: Only output test data when reading was successful.
Signed-off-by: Rafal Czubak <rcz@semihalf.com>
commit 7fb6c4f9b06c5539043c8bfc6565710b8090841d
Author: Rafal Jaworowski <raj@semihalf.com>
Date: Fri Jan 23 13:27:16 2009 +0100
API: Provide syscall entry point for the ARM architecture.
Signed-off-by: Rafal Czubak <rcz@semihalf.com>
Acked-by: Rafal Jaworowski <raj@semihalf.com>
commit b84d7d8f1e1066f810866304a16a3583f88e7c98
Author: Rafal Jaworowski <raj@semihalf.com>
Date: Fri Jan 23 13:27:15 2009 +0100
API: Use stack pointer as API signature search hint in the glue layer.
De-hardcode range in RAM we search for the API signature. Instead use the stack
pointer as a hint to narrow down the range in which the signature could reside
(it is malloc'ed on the U-Boot heap, and is hoped to remain in some proximity
from stack area). Adjust PowerPC code in API demo to the new scheme.
Signed-off-by: Rafal Czubak <rcz@semihalf.com>
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
commit 86b4bafdfaf669ede8fd99044abc7e27ea29b4f5
Author: Wolfgang Denk <wd@denx.de>
Date: Tue Feb 17 10:26:38 2009 +0100
TQM8260: fix locations of kernel and ramdisk images in flash
After introducing redundant environment the kernel images was
overlapping with environment.
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit e1ac387f4645499746856adc1aeaa9787da2eca6
Author: Andy Fleming <afleming@freescale.com>
Date: Thu Oct 30 16:50:14 2008 -0500
83xx: Add eSDHC support on 8379 EMDS board
Signed-off-by: Andy Fleming <afleming@freescale.com>
commit 80522dc8369a89938369fbcee572e662373bc9a3
Author: Andy Fleming <afleming@freescale.com>
Date: Thu Oct 30 16:51:33 2008 -0500
85xx: Add eSDHC support for 8536 DS
Signed-off-by: Andy Fleming <afleming@freescale.com>
commit 50586ef24ed5caf6ce5591df76f355009da2cd79
Author: Andy Fleming <afleming@freescale.com>
Date: Thu Oct 30 16:47:16 2008 -0500
Add support for the Freescale eSDHC found on 8379 and 8536 SoCs
This uses the new MMC framework
Some contributions by Dave Liu <daveliu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
commit 272cc70b211e945e4413122aa73868f6ada732a5
Author: Andy Fleming <afleming@freescale.com>
Date: Thu Oct 30 16:41:01 2008 -0500
Add MMC Framework
Here's a new framework (based roughly off the linux one) for managing
MMC controllers. It handles all of the standard SD/MMC transactions,
leaving the host drivers to implement only what is necessary to
deal with their specific hardware.
This also hooks the infrastructure into the PowerPC board code
(similar to how the ethernet infrastructure now hooks in)
Some of this code was contributed by Dave Liu <daveliu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
commit 1de97f9856f697380cc504126ab92561ed238803
Author: Andy Fleming <afleming@freescale.com>
Date: Thu Oct 30 16:31:39 2008 -0500
Eliminated arch-specific mmc header requirement
The current MMC infrastructure relies on the existence of an
arch-specific header file. This isn't necessary, and a couple
drivers were forced to implement dummy files to meet this requirement.
Instead, we move the stuff in those header files into a more appropriate
place, and eliminate the stubs and the #include of asm/arch/mmc.h
Signed-off-by: Andy Fleming <afleming@freescale.com>
commit abb5466ccf4ce50f412d459586f4f4b81cb73ac3
Author: Andy Fleming <afleming@freescale.com>
Date: Thu Oct 30 16:21:00 2008 -0500
Convert mmc_init to mmc_legacy_init
This is to get it out of the way of incoming MMC framework
Signed-off-by: Andy Fleming <afleming@freescale.com>
commit b2e2ed0233a5ef299361abec4fbdaefb63456eff
Author: Andy Fleming <afleming@freescale.com>
Date: Thu Oct 30 16:19:25 2008 -0500
Eliminate support for using MMC as memory
MMC cards are not memory, so we stop treating them that way.
Signed-off-by: Andy Fleming <afleming@freescale.com>
commit e1be0d25ecf494ae81245ca438738ba839d6329b
Author: Poonam_Aggrwal-b10812 <b10812@freescale.com>
Date: Sun Jan 4 08:46:38 2009 +0530
32bit BUg fix for DDR2 on 8572
This errata fix is required for 32 bit DDR2 controller on 8572.
May also be required for P10XX20XX platforms
Signed-off-by: Poonam_Agarwal-b10812 <b10812@lc1106.zin33.ap.freescale.net>
commit e0c4fac79d4d74572ddd43f75e7189cecca8d0ad
Author: Andy Fleming <afleming@freescale.com>
Date: Mon Feb 16 09:40:20 2009 -0600
TQM85xx: Fix a couple warnings in TQM8548 build
The ecm variable in sdram.c was being declared for all 8548, but only
used by specific 8548 boards, so we make that variable require those
specific boards, too
The nand code was using an index "i" into a table, and then re-using "i"
to set addresses for each upm. However, then it relied on the old value
of i still being there to enable things. Changed the second "i" to "j"
Signed-off-by: Andy Fleming <afleming@freescale.com>
commit cf07a5baece0ecfc5284cfda8a4e68eaf92782f8
Author: Wolfgang Grandegger <wg@grandegger.com>
Date: Wed Feb 11 18:38:26 2009 +0100
MPC85xx: TQM8548: workaround for erratum DDR 19 and 20
This patch adds the workaround for erratum DDR20 according to MPC8548
Device Errata document, Rev. 1: "CKE signal may not function correctly
after assertion of HRESET". Furthermore, the bug DDR19 is fixed in
processor version 2.1 and the work-around must be removed.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
commit 080408fdc71706adcb883d22125637c54f6010b1
Author: Wolfgang Grandegger <wg@grandegger.com>
Date: Wed Feb 11 18:38:25 2009 +0100
MPC85xx: TQM8548: use cache for AG and BE variants
This patch makes accesses to the system memory cachable by removing the
caching-inhibited and guarded flags from the relevant TLB entries for
the TQM8548_BE and TQM8548_AG modules. FYI, the Freescale MPC85* boards
are configured similarly.
This results in a big averall performace improvement. TFTP downloads,
NAND Flash accesses, kernel boots, etc. are much faster.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
commit dc5f55d636d7bf21ba17758fac4b929ec4c059f2
Author: Wolfgang Grandegger <wg@grandegger.com>
Date: Wed Feb 11 18:38:24 2009 +0100
MPC85xx: TQM8548_AG: add 1 GiB DDR2-SDRAM configuration
This patch add support for the 1 GiB DDR2-SDRAM on the TQM8548_AG
module.
Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
commit 88b0e88d186479349e5a2b771e82775109e10fb4
Author: Wolfgang Grandegger <wg@grandegger.com>
Date: Wed Feb 11 18:38:23 2009 +0100
MPC85xx: TQM8548: fix SDRAM timing for 533 MHz
According to new TQM8548 timing specification:
Refresh Recovery: 34 -> 53 clocks
CKE pulse width: 1 -> 3 cycles
Window for four activities: 13 -> 14 cycles
Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
commit a865bcdac89278cac4dfc07dec8299403110499d
Author: Wolfgang Grandegger <wg@grandegger.com>
Date: Wed Feb 11 18:38:22 2009 +0100
MPC85xx: TQM8548: add support for the TQM8548_AG module
The TQM8548_AG is a variant of the TQM8548 module with 1 GiB memory,
CAN and without PCI/PCI-X and RTC. U-Boot can be built for this module
with "$ make TQM8548_AG_config".
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
commit ad7ee5d43b0db94079d56521dabca25674f28747
Author: Wolfgang Grandegger <wg@grandegger.com>
Date: Wed Feb 11 18:38:21 2009 +0100
MPC85xx: TQM8548: add support for the TQM8548_BE module
The TQM8548_BE is a variant of the TQM8548 module with NAND and CAN
interface. With NAND support, the image is significantly larger and
TEXT_BASE is adjusted accordingly. U-Boot can be built for this
module with "$ make TQM8548_BE_config".
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
commit a318234878c346e673b2ef8dc4b14b338fe7fc2b
Author: Wolfgang Grandegger <wg@grandegger.com>
Date: Wed Feb 11 18:38:20 2009 +0100
MPC85xx: TQM85xx: make standard PCI/PCI-X configurable
The TQM8548_AG module does not have the standard PCI/PCI-X interface
connected but just the PCI Express interface . So far it was not
possible to disable it without disabling the complete PCI interface
(CONFIG_PCI) including PCI Express.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
commit 31ca9119c3186cec579b54d2a7a2b361b4d2b7bf
Author: Wolfgang Grandegger <wg@grandegger.com>
Date: Wed Feb 11 18:38:19 2009 +0100
MPC85xx: TQM85xx: fix flash protection for boot loader
As the reset vector is located at 0xfffffffc, all flash sectors from the
beginning of the U-Boot binary to 0xffffffff must be protected. On the
TQM8548-AG having small sectors at the end of the flash it happened that
the last two sector were not protected and an "erase all" left an
un-bootable system behind:
Bank # 2: CFI conformant FLASH (32 x 16) Size: 32 MB in 270 Sectors
AMD Standard command set, Manufacturer ID: 0xEC, Device ID: 0x257E
Erase timeout: 8192 ms, write timeout: 1 ms
FFFA0000 E RO FFFC0000 RO FFFE0000 RO FFFE4000 RO FFFE8000 RO
FFFEC000 RO FFFF0000 RO FFFF4000 RO FFFF8000 E FFFFC000
The same bug seems to be in drivers/mtd/cfi_flash.c:flash_init() and many
board BSPs as well.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
commit a1c8a719262151f97119e76166043ee3da3f97b2
Author: Peter Tyser <ptyser@xes-inc.com>
Date: Fri Feb 6 14:30:40 2009 -0600
86xx: Update CPU info output on bootup
- Update style of 86xx CPU information on boot to more closely
match 85xx boards
- Fix detection of 8641/8641D
- Use strmhz() to display frequencies
- Display L1 information
- Display L2 cache size
- Fixed CPU/SVR version output
== Before ==
Freescale PowerPC
CPU:
Core: E600 Core 0, Version: 0.2, (0x80040202)
System: Unknown, Version: 2.1, (0x80900121)
Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz
L2: Enabled
Board: X-ES XPedite5170 3U VPX SBC
== After ==
CPU: 8641D, Version: 2.1, (0x80900121)
Core: E600 Core 0, Version: 2.2, (0x80040202)
Clock Configuration:
CPU:1066.667 MHz, MPX:533.333 MHz
DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz
L1: D-cache 32 KB enabled
I-cache 32 KB enabled
L2: 512 KB enabled
Board: X-ES XPedite5170 3U VPX SBC
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
commit 22c00f8d7d454d77e759df58415d2d3f3d7e154c
Author: Peter Tyser <ptyser@xes-inc.com>
Date: Thu Feb 5 11:25:24 2009 -0600
86xx: Update Global Utilities structure
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
commit 4ef630df773e45806d701bf5d25c328778bb4cde
Author: Peter Tyser <ptyser@xes-inc.com>
Date: Thu Feb 5 11:25:25 2009 -0600
86xx: Reset update
Update the 86xx reset sequence to try executing a board-specific reset
function. If the board-specific reset is not implemented or does not
succeed, then assert #HRESET_REQ. Using #HRESET_REQ is a more standard
reset procedure than the previous method and allows all board
peripherals to be reset if needed.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
commit edf0e2524a8c6a3e91c009c496a0aa0ae89cd8ab
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Tue Feb 10 23:53:40 2009 -0600
fsl-ddr: Allow system to boot if we have more than 4G of memory
Previously if we >=4G of memory and !CONFIG_PHYS_64BIT we'd report
an error and hang. Instead of doing that since DDR is mapped in the
lowest priority LAWs we setup the DDR controller and the max amount
of memory we report back is what we can map (CONFIG_MAX_MEM_MAPPED)
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Becky Bruce <beckyb@kernel.crashing.org>
commit 8d949aff38cfb4388cbd73876e77bcd06d601f20
Author: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Date: Wed Jan 21 17:17:33 2009 -0600
mpc85xx: Add support for the P2020
Added various p2020 processor specific details:
* SVR for p2020, p2020E
* immap updates for LAWs and DDR on p2020
* LAW defines related to p2020
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit cb69e4de8702e108324e1c40363f30ef6f2e2918
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Tue Feb 10 17:36:15 2009 -0600
85xx: print boot header info to distinquish 36-bit addr map on MPC8572 DS
Added some info that is printed out when we boot to distiquish if we
built MPC8572DS_config vs MPC8572DS_36BIT_config since they have
different address maps.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit feede8b07013b33fca8dd2a916b3ac86bf4d4c0a
Author: Andy Fleming <afleming@freescale.com>
Date: Fri Dec 5 20:10:22 2008 -0600
Fixup SGMII PHY ids in the device tree
The device tree's PHY addresses need to be fixed up if we're using the
SGMII Riser Card.
The 8572, 8536, and 8544 DS boards were modified to call this function.
Code idea taken from Liu Yu <yu.liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
commit 5dc0cf68f8f101042997d75188081d8526d705ea
Author: Andy Fleming <afleming@freescale.com>
Date: Wed Feb 11 15:10:31 2009 -0600
Make some minor whitespace changes to eliminate line-wrapping
Signed-off-by: Andy Fleming <afleming@freescale.com>
commit 9e56986a2b74d197f51eca70fad7b836b1900c4d
Author: Andy Fleming <afleming@freescale.com>
Date: Wed Feb 11 15:07:24 2009 -0600
Add eth_get_dev_by_index
This allows code to iterate through the ethernet devices
Signed-off-by: Andy Fleming <afleming@freescale.com>
commit b67305120aaf268a6140125346678166d14f1f47
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Mon Feb 9 22:03:04 2009 -0600
85xx: Fix bug in device tree setup in 36-bit physical confg
In the 36-bit physical config for MPC8572DS when need the start address
of memory and it size to be kept in phys_*_t instead of a ulong since
we support >4G of memory in the config and ulong cant represent that.
Otherwise we end up seeing the memory node in the device tree reporting
back we have memory starting @ 0 and of size 0.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit ad97dce18445ff05bf326094e691a01aa95aa8dc
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Mon Feb 9 22:03:05 2009 -0600
85xx: Fix address map for 36-bit config of MPC8572DS
When we introduced the 36-bit config of the MPC8572DS board we had the
wrong PCI MEM bus address map. Additionally, the change to the address
map exposes a small issue in our dummy read on the ULI bus. We need
to use the new mapping functions to handle that read properly in the
36-bit config.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit f8523cb0815b2d3d2d780b7d49ca614105555f58
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Fri Feb 6 09:56:35 2009 -0600
85xx: Fix how we map DDR memory
Previously we only allowed power-of-two memory sizes and didnt
handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED
and should properly handle any size that we can make in the TLBs
we have available to us
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit 1542fbdeec0d1e2a6df13189df8dcb1ce8802be3
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Fri Feb 6 09:56:34 2009 -0600
fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller
If we only have one controller we can completely ignore how
memctl_intlv_ctl is set. Otherwise other levels of code get confused
and think we have twice as much memory.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit b29dee3c906e9daaf6baf7772d2e15e26b8636b8
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Wed Feb 4 09:35:57 2009 -0600
85xx: Format cpu freq printing to handle 8 cores
Only print 4 cpu freq per line. This way when we have 8 cores its a
bit more readable.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit 9704f9caf53f5cae547d8c5e1ae94aa4e57b160f
Author: Abraham, Thomas <t-abraham@ti.com>
Date: Tue Oct 28 16:51:31 2008 +0530
USB: Remove LUN number from CDB
The LUN number is not part of the Command Descriptor Block (CDB) for scsi inquiry, request sense, test unit ready, read capacity and read10 commands. This patch removes the LUN number information from the CDB.
Signed-off-by: Thomas Abraham <t-abraham@ti.com>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
commit f3c0de636252f3a18654c8f9c6370a9574a7e755
Author: Atin Malaviya <atin.malaviya@gmail.com>
Date: Tue Feb 3 15:17:10 2009 -0500
Added usbtty_configured() check. Fixed attribute(packed) warnings.
V3: Fixed line-wrap problem due to user error in mail!
Added usb_configured() checks in usbtty_puts() and usbtty_putc() to get around a hang
when usb is not connected and the user has set up multi-io (setenv stdout serial,usbtty etc).
Got rid of redundant __attribute__((packed)) directives that were causing warnings from gcc.
Signed-off-by: Atin Malaviya <atin.malaviya@gmail.com>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
commit e7de18afe8ecf96a51ef981d06066eeb6b1254e7
Author: Guennadi Liakhovetski <lg@denx.de>
Date: Fri Feb 13 09:23:36 2009 +0100
i.MX31: Start the I2C clock on driver initialisation
i.MX31 powers on with most clocks running, so, after a power on this explicit
clock start up is not required. However, as Linux boots it disables most clocks
to save power. This includes the I2C clock. If we then soft reboot from Linux
the I2C clock stays off. This breaks the phycore, which has its environment in
I2C EEPROM. Fix the problem by explicitly starting the clock in I2C driver
initialisation routine.
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Ack-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
commit 15208ac9eae1c340c4bc11f70cbf5c9da78a57ba
Author: Mike Frysinger <vapier@gentoo.org>
Date: Wed Feb 11 20:36:14 2009 -0500
i2c.h: drop i2c_reg_{read, write} hack for Blackfin parts
The Blackfin i2c driver has been rewritten thus the special ifdefs in the
common code are no longer needed.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit c2d9befa0b4695b89476fb5d259742c09afe243f
Author: Heiko Schocher <hs@denx.de>
Date: Thu Feb 12 08:08:54 2009 +0100
82xx, mgcoge: fix compile error
With actual u-boot compiling the mgcoge port fails, because
since commit ba705b5b1a97b47388ed48858bef6bf7b6bfcd56 it is
necessary to define CONFIG_NET_MULTI.
Seems to me the mgcoge port is the only actual existing 8260
port who uses CONFIG_ETHER_ON_SCC, so no other 8260 port needed
to be fixed.
Signed-off-by: Heiko Schocher <hs@denx.de>
commit 9cacf4fc4035eabe9d9ae2a9a188c51a8027c91e
Author: Dirk Eibach <eibach@gdsys.de>
Date: Mon Feb 9 08:18:34 2009 +0100
ppc4xx: Add README entry for CONFIG_PCI_DISABLE_PCIE
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
commit 7369f0e384e2a831be13a7773a58242c9173fa9c
Author: Carolyn Smith <carolyn.smith@tektronix.com>
Date: Thu Feb 12 06:13:44 2009 +0100
ppc4xx: Fix initialization of the SDRAM_CODT register
This fixes the initialization of the SDRAM_CODT register in the ppc4xx DDR2
initialization code. It also removes use of the SDRAM_CODT_FEEDBACK_RCV_SINGLE_END
and SDRAM_CODT_FEEDBACK_DRV_SINGLE_END #define's since they are reserved bits.
Signed-off-by: Carolyn Smith <carolyn.smith@tektronix.com>
Signed-off-by: Stefan Roese <sr@denx.de>
commit cef0efaf2fa55d1f25066cfb02bd984c27f9ca31
Author: Stefan Roese <sr@denx.de>
Date: Wed Feb 11 09:29:33 2009 +0100
ppc4xx: Fix problem with board_eth_init() vs cpu_eth_init() on AMCC boards
Some AMCC eval boards do have a board_eth_init() function calling
pci_eth_init(). These boards need to call cpu_eth_init() explicitly now
with the new eth_init rework.
Signed-off-by: Stefan Roese <sr@denx.de>
commit c645012aefebb301e6907d148c6c8efacac049d4
Author: Adam Graham <agraham@amcc.com>
Date: Mon Feb 9 13:18:12 2009 -0800
ppc4xx: Autocalibration can set RDCC to over aggressive value.
The criteria of the AMCC SDRAM Controller DDR autocalibration
U-Boot code is to pick the largest passing write/read/compare
window that also has the smallest SDRAM_RDCC.[RDSS] Read Sample
Cycle Select value.
On some Kilauea boards the DDR autocalibration algorithm can
find a large passing write/read/compare window with a small
SDRAM_RDCC.[RDSS] aggressive value of Read Sample Cycle Select
value "T1 Sample".
This SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of
"T1 Sample" proves to be to aggressive when later on U-Boot
relocates into DDR memory and executes.
The memory traces on the Kilauea board are short so on some
Kilauea boards the SDRAM_RDCC.[RDSS] Read Sample Cycle Select
value of "T1 Sample" shows up as a potentially valid value for
the DDR autocalibratiion algorithm.
The fix is to define a weak default function which provides
the minimum SDRAM_RDCC.[RDSS] Read Sample Cycle Select value
to accept for DDR autocalibration. The default will be the
"T2 Sample" value. A board developer who has a well defined
board and chooses to be more aggressive can always provide
their own board specific string function with the more
aggressive "T1 Sample" value or stick with the default
minimum SDRAM_RDCC.[RDSS] value of "T2".
Also put in a autocalibration loop fix for case where current
write/read/compare passing window size is the same as a prior
window size, then in this case choose the write/read/compare
result that has the associated smallest RDCC T-Sample value.
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
commit 2ede879fcb67470524847bb4fc8972651bb46184
Author: Stefan Roese <sr@denx.de>
Date: Wed Feb 11 09:37:12 2009 +0100
ppc4xx: Fix problem with CONFIG_MAX_MEM_MAPPED in include/asm-ppc/config.h
CONFIG_SDRAM_PPC4xx_IBM_DDR2 is not set when include/asm-ppc/config.h is
included. So for katmai, CONFIG_MAX_MEM_MAPPED will get set to 256MB.
It makes perfect sense to set CONFIG_MAX_MEM_MAPPED to 2GB for all PPC4xx
boards right now.
Signed-off-by: Stefan Roese <sr@denx.de>
commit f15c6515fc23f83c51f3de272ca23d86b80e81b1
Author: Wolfgang Denk <wd@denx.de>
Date: Thu Feb 12 00:08:39 2009 +0100
Coding style cleanup; update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 5fc56b907d993260b9ebdb137af66fe69635ae9e
Author: Peter Tyser <ptyser@xes-inc.com>
Date: Fri Jan 30 16:36:40 2009 -0600

View File

@ -655,6 +655,9 @@ Sergey Lapin <slapin@ossfans.org>
afeb9260 ARM926EJS (AT91SAM9260 SoC)
Wolfgang Denk <wd@denx.de>
qong i.MX31
-------------------------------------------------------------------------
Unknown / orphaned boards:

View File

@ -544,6 +544,7 @@ LIST_ARM11=" \
imx31_litekit \
imx31_phycore \
mx31ads \
qong \
smdk6400 \
"

View File

@ -3038,6 +3038,10 @@ mx31ads_config : unconfig
omap2420h4_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx
qong_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 qong davedenx mx31
#########################################################################
## ARM1176 Systems
#########################################################################

13
README
View File

@ -608,7 +608,7 @@ The following options need to be configured:
CONFIG_CMD_ECHO echo arguments
CONFIG_CMD_EEPROM * EEPROM read/write support
CONFIG_CMD_ELF * bootelf, bootvx
CONFIG_CMD_ENV saveenv
CONFIG_CMD_SAVEENV saveenv
CONFIG_CMD_FDC * Floppy Disk Support
CONFIG_CMD_FAT * FAT partition support
CONFIG_CMD_FDOS * Dos diskette Support
@ -2458,6 +2458,13 @@ use the "saveenv" command to store a valid environment.
- CONFIG_SYS_64BIT_STRTOUL:
Adds simple_strtoull that returns a 64bit value
- CONFIG_NS16550_MIN_FUNCTIONS:
Define this if you desire to only have use of the NS16550_init
and NS16550_putc functions for the serial driver located at
drivers/serial/ns16550.c. This option is useful for saving
space for already greatly restricted images, including but not
limited to NAND_SPL configurations.
Low Level (hardware related) configuration options:
---------------------------------------------------
@ -2623,10 +2630,6 @@ Low Level (hardware related) configuration options:
Only for 83xx systems. If specified, then DDR should
be configured using CS0 and CS1 instead of CS2 and CS3.
- CONFIG_SYS_83XX_DDR_USES_CS0
Only for 83xx systems. If specified, then DDR should
be configured using CS0 and CS1 instead of CS2 and CS3.
- CONFIG_ETHER_ON_FEC[12]
Define to enable FEC[12] on a 8xx series processor.

View File

@ -23,10 +23,9 @@
ifeq ($(ARCH),ppc)
LOAD_ADDR = 0x40000
endif
#ifeq ($(ARCH),arm)
#LOAD_ADDR = 0xc100000
#endif
ifeq ($(ARCH),arm)
LOAD_ADDR = 0x1000000
endif
include $(TOPDIR)/config.mk

View File

@ -26,9 +26,11 @@
#if defined(CONFIG_PPC)
.text
.globl _start
_start:
lis %r11, search_hint@ha
addi %r11, %r11, search_hint@l
stw %r1, 0(%r11)
b main
@ -40,11 +42,30 @@ syscall:
mtctr %r11
bctr
#elif defined(CONFIG_ARM)
.text
.globl _start
_start:
ldr ip, =search_hint
str sp, [ip]
b main
.globl syscall
syscall:
ldr ip, =syscall_ptr
ldr pc, [ip]
#else
#error No support for this arch!
#endif
.globl syscall_ptr
syscall_ptr:
.align 4
.long 0
#else
#error No support for this arch!
#endif
.globl search_hint
search_hint:
.long 0

View File

@ -43,12 +43,11 @@ static char buf[BUF_SZ];
int main(int argc, char *argv[])
{
int rv = 0;
int h, i, j;
int devs_no;
int rv = 0, h, i, j, devs_no;
struct api_signature *sig = NULL;
ulong start, now;
struct device_info *di;
lbasize_t rlen;
if (!api_search_sig(&sig))
return -1;
@ -96,7 +95,6 @@ int main(int argc, char *argv[])
if (devs_no == 0)
return -1;
printf("\n*** Show devices ***\n");
for (i = 0; i < devs_no; i++) {
test_dump_di(i);
@ -133,11 +131,12 @@ int main(int argc, char *argv[])
if ((rv = ub_dev_open(i)) != 0)
errf("open device %d error %d\n", i, rv);
else if ((rv = ub_dev_read(i, buf, 1, 0)) != 0)
else if ((rv = ub_dev_read(i, buf, 1, 0, &rlen)) != 0)
errf("could not read from device %d, error %d\n", i, rv);
printf("Sector 0 dump (512B):\n");
test_dump_buf(buf, 512);
else {
printf("Sector 0 dump (512B):\n");
test_dump_buf(buf, 512);
}
ub_dev_close(i);
}
@ -178,6 +177,7 @@ int main(int argc, char *argv[])
printf("%s = %s\n", env, ub_env_get(env));
/* reset */
printf("\n*** Resetting board ***\n");
ub_reset();
printf("\nHmm, reset returned...?!\n");

View File

@ -1,7 +1,5 @@
/*
* (C) Copyright 2007 Semihalf
*
* Written by: Rafal Jaworowski <raj@semihalf.com>
* (C) Copyright 2007-2008 Semihalf, Rafal Jaworowski <raj@semihalf.com>
*
* See file CREDITS for list of people who contributed to this
* project.
@ -57,16 +55,23 @@ static int valid_sig(struct api_signature *sig)
*
* returns 1/0 depending on found/not found result
*/
int api_search_sig(struct api_signature **sig) {
int api_search_sig(struct api_signature **sig)
{
unsigned char *sp;
uint32_t search_start = 0;
uint32_t search_end = 0;
if (sig == NULL)
return 0;
sp = (unsigned char *)API_SEARCH_START;
if (search_hint == 0)
search_hint = 255 * 1024 * 1024;
while ((sp + (int)API_SIG_MAGLEN) < (unsigned char *)API_SEARCH_END) {
search_start = search_hint & ~0x000fffff;
search_end = search_start + API_SEARCH_LEN - API_SIG_MAGLEN;
sp = (unsigned char *)search_start;
while ((sp + API_SIG_MAGLEN) < (unsigned char *)search_end) {
if (!memcmp(sp, API_SIG_MAGIC, API_SIG_MAGLEN)) {
*sig = (struct api_signature *)sp;
if (valid_sig(*sig))
@ -126,8 +131,7 @@ void ub_reset(void)
syscall(API_RESET, NULL);
}
#define MR_MAX 5
static struct mem_region mr[MR_MAX];
static struct mem_region mr[UB_MAX_MR];
static struct sys_info si;
struct sys_info * ub_get_sys_info(void)
@ -136,7 +140,7 @@ struct sys_info * ub_get_sys_info(void)
memset(&si, 0, sizeof(struct sys_info));
si.mr = mr;
si.mr_no = MR_MAX;
si.mr_no = UB_MAX_MR;
memset(&mr, 0, sizeof(mr));
if (!syscall(API_GET_SYS_INFO, &err, (u_int32_t)&si))
@ -171,17 +175,15 @@ unsigned long ub_get_timer(unsigned long base)
*
* devices
*
* Devices are identified by handles: numbers 0, 1, 2, ..., MAX_DEVS-1
* Devices are identified by handles: numbers 0, 1, 2, ..., UB_MAX_DEV-1
*
***************************************************************************/
#define MAX_DEVS 6
static struct device_info devices[MAX_DEVS];
static struct device_info devices[UB_MAX_DEV];
struct device_info * ub_dev_get(int i)
{
return ((i < 0 || i >= MAX_DEVS) ? NULL : &devices[i]);
return ((i < 0 || i >= UB_MAX_DEV) ? NULL : &devices[i]);
}
/*
@ -195,7 +197,7 @@ int ub_dev_enum(void)
struct device_info *di;
int n = 0;
memset(&devices, 0, sizeof(struct device_info) * MAX_DEVS);
memset(&devices, 0, sizeof(struct device_info) * UB_MAX_DEV);
di = &devices[0];
if (!syscall(API_DEV_ENUM, NULL, di))
@ -203,7 +205,7 @@ int ub_dev_enum(void)
while (di->cookie != NULL) {
if (++n >= MAX_DEVS)
if (++n >= UB_MAX_DEV)
break;
/* take another device_info */
@ -229,7 +231,7 @@ int ub_dev_open(int handle)
struct device_info *di;
int err = 0;
if (handle < 0 || handle >= MAX_DEVS)
if (handle < 0 || handle >= UB_MAX_DEV)
return API_EINVAL;
di = &devices[handle];
@ -244,7 +246,7 @@ int ub_dev_close(int handle)
{
struct device_info *di;
if (handle < 0 || handle >= MAX_DEVS)
if (handle < 0 || handle >= UB_MAX_DEV)
return API_EINVAL;
di = &devices[handle];
@ -265,7 +267,7 @@ int ub_dev_close(int handle)
*/
static int dev_valid(int handle)
{
if (handle < 0 || handle >= MAX_DEVS)
if (handle < 0 || handle >= UB_MAX_DEV)
return 0;
if (devices[handle].state != DEV_STA_OPEN)
@ -285,7 +287,8 @@ static int dev_stor_valid(int handle)
return 1;
}
int ub_dev_read(int handle, void *buf, lbasize_t len, lbastart_t start)
int ub_dev_read(int handle, void *buf, lbasize_t len, lbastart_t start,
lbasize_t *rlen)
{
struct device_info *di;
lbasize_t act_len;
@ -296,15 +299,12 @@ int ub_dev_read(int handle, void *buf, lbasize_t len, lbastart_t start)
di = &devices[handle];
if (!syscall(API_DEV_READ, &err, di, buf, &len, &start, &act_len))
return -1;
return API_ESYSC;
if (err)
return err;
if (!err && rlen)
*rlen = act_len;
if (act_len != len)
return API_EIO;
return 0;
return err;
}
static int dev_net_valid(int handle)
@ -318,7 +318,7 @@ static int dev_net_valid(int handle)
return 1;
}
int ub_dev_recv(int handle, void *buf, int len)
int ub_dev_recv(int handle, void *buf, int len, int *rlen)
{
struct device_info *di;
int err = 0, act_len;
@ -328,12 +328,12 @@ int ub_dev_recv(int handle, void *buf, int len)
di = &devices[handle];
if (!syscall(API_DEV_READ, &err, di, buf, &len, &act_len))
return -1;
return API_ESYSC;
if (err)
return -1;
if (!err && rlen)
*rlen = act_len;
return act_len;
return (err);
}
int ub_dev_send(int handle, void *buf, int len)
@ -346,7 +346,7 @@ int ub_dev_send(int handle, void *buf, int len)
di = &devices[handle];
if (!syscall(API_DEV_WRITE, &err, di, buf, &len))
return -1;
return API_ESYSC;
return err;
}
@ -372,7 +372,6 @@ void ub_env_set(const char *name, char *value)
syscall(API_ENV_SET, NULL, (uint32_t)name, (uint32_t)value);
}
static char env_name[256];
const char * ub_env_enum(const char *last)

View File

@ -30,18 +30,22 @@
#ifndef _API_GLUE_H_
#define _API_GLUE_H_
#define API_SEARCH_START (255 * 1024 * 1024) /* start at 1MB below top RAM */
#define API_SEARCH_END (256 * 1024 * 1024 - 1) /* ...and search to the end */
#define API_SEARCH_LEN (3 * 1024 * 1024) /* 3MB search range */
#define UB_MAX_MR 5 /* max mem regions number */
#define UB_MAX_DEV 6 /* max devices number */
extern void *syscall_ptr;
extern uint32_t search_hint;
int syscall(int, int *, ...);
void * syscall_ptr;
int api_search_sig(struct api_signature **sig);
/*
* ub_ library calls are part of the application, not U-Boot code! They are
* front-end wrappers that are used by the consumer application: they prepare
* arguments for particular syscall and jump to the low level syscall()
* The ub_ library calls are part of the application, not U-Boot code! They
* are front-end wrappers that are used by the consumer application: they
* prepare arguments for particular syscall and jump to the low level
* syscall()
*/
/* console */
@ -67,10 +71,10 @@ const char * ub_env_enum(const char *last);
int ub_dev_enum(void);
int ub_dev_open(int handle);
int ub_dev_close(int handle);
int ub_dev_read(int handle, void *buf,
lbasize_t len, lbastart_t start);
int ub_dev_read(int handle, void *buf, lbasize_t len,
lbastart_t start, lbasize_t *rlen);
int ub_dev_send(int handle, void *buf, int len);
int ub_dev_recv(int handle, void *buf, int len);
int ub_dev_recv(int handle, void *buf, int len, int *rlen);
struct device_info * ub_dev_get(int);
#endif /* _API_GLUE_H_ */

View File

@ -0,0 +1,53 @@
#
# (C) Copyright 2009
# Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := qong.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

View File

@ -0,0 +1 @@
TEXT_BASE = 0x8ff00000

View File

@ -0,0 +1,172 @@
/*
* Copyright (C) 2009, Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
*
* Based on board/freescale/mx31ads/lowlevel_init.S
* by Guennadi Liakhovetski.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <asm/arch/mx31-regs.h>
.macro REG reg, val
ldr r2, =\reg
ldr r3, =\val
str r3, [r2]
.endm
.macro REG8 reg, val
ldr r2, =\reg
ldr r3, =\val
strb r3, [r2]
.endm
.macro DELAY loops
ldr r2, =\loops
1:
subs r2, r2, #1
nop
bcs 1b
.endm
/* RedBoot: To support 133MHz DDR */
.macro init_drive_strength
/*
* Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
* in SW_PAD_CTL registers
*/
/* SDCLK */
ldr r1, =IOMUXC_SW_PAD_CTL(0x2b)
ldr r0, [r1, #0x6C]
bic r0, r0, #(1 << 12)
str r0, [r1, #0x6C]
/* CAS */
ldr r0, [r1, #0x70]
bic r0, r0, #(1 << 22)
str r0, [r1, #0x70]
/* RAS */
ldr r0, [r1, #0x74]
bic r0, r0, #(1 << 2)
str r0, [r1, #0x74]
/* CS2 (CSD0) */
ldr r0, [r1, #0x7C]
bic r0, r0, #(1 << 22)
str r0, [r1, #0x7C]
/* DQM3 */
ldr r0, [r1, #0x84]
bic r0, r0, #(1 << 22)
str r0, [r1, #0x84]
/* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
pad_loop:
ldr r0, [r1, #0x88]
bic r0, r0, #(1 << 22)
bic r0, r0, #(1 << 12)
bic r0, r0, #(1 << 2)
str r0, [r1, #0x88]
add r1, r1, #4
subs r2, r2, #0x1
bne pad_loop
.endm /* init_drive_strength */
.globl lowlevel_init
lowlevel_init:
init_drive_strength
/* Image Processing Unit: */
/* Too early to switch display on? */
/* Switch on Display Interface */
REG IPU_CONF, IPU_CONF_DI_EN
/* Clock Control Module: */
REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */
DELAY 0x40000
REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */
/* Switch to MCU PLL */
REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
/* 399-133-66.5 */
ldr r0, =CCM_BASE
ldr r1, =0xFF871650
/* PDR0 */
str r1, [r0, #0x4]
ldr r1, MPCTL_PARAM_399
/* MPCTL */
str r1, [r0, #0x10]
/* Set UPLL=240MHz, USB=60MHz */
ldr r1, =0x49FCFE7F
/* PDR1 */
str r1, [r0, #0x8]
ldr r1, UPCTL_PARAM_240
/* UPCTL */
str r1, [r0, #0x14]
/* default CLKO to 1/8 of the ARM core */
mov r1, #0x00000208
/* COSR */
str r1, [r0, #0x1c]
/* Default: 1, 4, 12, 1 */
REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
/* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
REG 0xB8001010, 0x00000004
REG 0xB8001004, ((3 << 21) | /* tXP */ \
(0 << 20) | /* tWTR */ \
(2 << 18) | /* tRP */ \
(1 << 16) | /* tMRD */ \
(0 << 15) | /* tWR */ \
(5 << 12) | /* tRAS */ \
(1 << 10) | /* tRRD */ \
(3 << 8) | /* tCAS */ \
(2 << 4) | /* tRCD */ \
(7 << 0) /* tRC */ )
REG 0xB8001000, 0x92100000
REG 0x80000f00, 0x12344321
REG 0xB8001000, 0xa2100000
REG 0x80000000, 0x12344321
REG 0x80000000, 0x12344321
REG 0xB8001000, 0xb2100000
REG8 0x80000033, 0xda
REG8 0x81000000, 0xff
REG 0xB8001000, ((1 << 31) | \
(0 << 28) | \
(0 << 27) | \
(3 << 24) | /* 14 rows */ \
(2 << 20) | /* 10 cols */ \
(2 << 16) | \
(4 << 13) | /* 3.91us (64ms/16384) */ \
(0 << 10) | \
(0 << 8) | \
(1 << 7) | \
(0 << 0))
REG 0x80000000, 0xDEADBEEF
REG 0xB8001010, 0x0000000c
mov pc, lr
MPCTL_PARAM_399:
.word (((1 - 1) << 26) + ((52 - 1) << 16) + (7 << 10) + (35 << 0))
UPCTL_PARAM_240:
.word (((2 - 1) << 26) + ((13 - 1) << 16) + (9 << 10) + (3 << 0))

168
board/davedenx/qong/qong.c Normal file
View File

@ -0,0 +1,168 @@
/*
*
* (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <netdev.h>
#include <asm/arch/mx31.h>
#include <asm/arch/mx31-regs.h>
#include "qong_fpga.h"
DECLARE_GLOBAL_DATA_PTR;
int dram_init (void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
return 0;
}
int board_init (void)
{
/* Chip selects */
/* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
/* Assumptions: HCLK = 133 MHz, tACC = 130ns */
__REG(CSCR_U(0)) = ((0 << 31) | /* SP */
(0 << 30) | /* WP */
(0 << 28) | /* BCD */
(0 << 24) | /* BCS */
(0 << 22) | /* PSZ */
(0 << 21) | /* PME */
(0 << 20) | /* SYNC */
(0 << 16) | /* DOL */
(3 << 14) | /* CNC */
(21 << 8) | /* WSC */
(0 << 7) | /* EW */
(0 << 4) | /* WWS */
(6 << 0) /* EDC */
);
__REG(CSCR_L(0)) = ((2 << 28) | /* OEA */
(1 << 24) | /* OEN */
(3 << 20) | /* EBWA */
(3 << 16) | /* EBWN */
(1 << 12) | /* CSA */
(1 << 11) | /* EBC */
(5 << 8) | /* DSZ */
(1 << 4) | /* CSN */
(0 << 3) | /* PSR */
(0 << 2) | /* CRE */
(0 << 1) | /* WRAP */
(1 << 0) /* CSEN */
);
__REG(CSCR_A(0)) = ((2 << 28) | /* EBRA */
(1 << 24) | /* EBRN */
(2 << 20) | /* RWA */
(2 << 16) | /* RWN */
(0 << 15) | /* MUM */
(0 << 13) | /* LAH */
(2 << 10) | /* LBN */
(0 << 8) | /* LBA */
(0 << 6) | /* DWW */
(0 << 4) | /* DCT */
(0 << 3) | /* WWU */
(0 << 2) | /* AGE */
(0 << 1) | /* CNC2 */
(0 << 0) /* FCE */
);
#ifdef CONFIG_QONG_FPGA
/* CS1: FPGA/Network Controller/GPIO */
/* 16-bit, no DTACK */
__REG(CSCR_U(1)) = 0x00000A01;
__REG(CSCR_L(1)) = 0x20040501;
__REG(CSCR_A(1)) = 0x04020C00;
/* setup pins for FPGA */
mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
#endif
/* setup pins for UART1 */
mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
/* board id for linux */
gd->bd->bi_arch_number = MACH_TYPE_QONG;
gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
return 0;
}
int checkboard (void)
{
printf("Board: DAVE/DENX QongEVB-LITE\n");
return 0;
}
int misc_init_r (void)
{
#ifdef CONFIG_QONG_FPGA
u32 tmp;
/* FPGA reset */
/* rstn = 0 */
tmp = __REG(GPIO2_BASE + GPIO_DR);
tmp &= (~(1 << QONG_FPGA_RST_PIN));
__REG(GPIO2_BASE + GPIO_DR) = tmp;
/* set the GPIO as output */
tmp = __REG(GPIO2_BASE + GPIO_GDIR);
tmp |= (1 << QONG_FPGA_RST_PIN);
__REG(GPIO2_BASE + GPIO_GDIR) = tmp;
/* wait */
udelay(30);
/* rstn = 1 */
tmp = __REG(GPIO2_BASE + GPIO_DR);
tmp |= (1 << QONG_FPGA_RST_PIN);
__REG(GPIO2_BASE + GPIO_DR) = tmp;
/* set interrupt pin as input */
__REG(GPIO2_BASE + GPIO_GDIR) = tmp | (1 << QONG_FPGA_IRQ_PIN);
/* wait while the FPGA starts */
udelay(300);
tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
printf("FPGA: ");
printf("version register = %u.%u.%u\n",
(tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
#endif
return 0;
}
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);
#else
return 0;
#endif
}

View File

@ -0,0 +1,41 @@
/*
*
* (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef QONG_FPGA_H
#define QONG_FPGA_H
#ifdef CONFIG_QONG_FPGA
#define QONG_FPGA_CTRL_BASE CONFIG_FPGA_BASE
#define QONG_FPGA_CTRL_VERSION (QONG_FPGA_CTRL_BASE + 0x00000000)
#define QONG_FPGA_PERIPH_SIZE (1 << 24)
#define QONG_FPGA_TCK_PIN 26
#define QONG_FPGA_TMS_PIN 25
#define QONG_FPGA_TDI_PIN 8
#define QONG_FPGA_TDO_PIN 7
#define QONG_FPGA_RST_PIN 16
#define QONG_FPGA_IRQ_PIN 8
#endif
#endif /* QONG_FPGA_H */

View File

@ -0,0 +1,58 @@
/*
* (C) Copyright 2009
* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
cpu/arm1136/start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
_end = .;
}

View File

@ -82,7 +82,7 @@ flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
static ulong flash_get_size(FPWV *addr, flash_info_t *info);
static void flash_reset(flash_info_t *info);
static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
static flash_info_t *flash_get_info(ulong base);
flash_info_t *flash_get_info(ulong base);
/*-----------------------------------------------------------------------
* flash_init()
@ -142,7 +142,7 @@ static void flash_reset(flash_info_t *info)
/*-----------------------------------------------------------------------
*/
static flash_info_t *flash_get_info(ulong base)
flash_info_t *flash_get_info(ulong base)
{
int i;
flash_info_t * info;

View File

@ -21,8 +21,4 @@
# MA 02111-1307 USA
#
#
# esd PMC405 boards
#
TEXT_BASE = 0xFFFC0000
TEXT_BASE = 0xFFF80000

View File

@ -2,7 +2,7 @@
* (C) Copyright 2001-2003
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2005
* (C) Copyright 2005-2009
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
@ -26,6 +26,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <command.h>
#include <malloc.h>
@ -40,7 +41,6 @@ const unsigned char fpgadata[] =
};
int filesize = sizeof(fpgadata);
int board_early_init_f (void)
{
/*
@ -55,107 +55,104 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0, INT0 highest priority */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
* EBC Configuration Register:
* set ready timeout to 512 ebc-clks -> ca. 15 us
*/
mtebc (epcr, 0xa8400000);
/*
* Setup GPIO pins
*/
mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT | \
CONFIG_SYS_FPGA_DONE | \
CONFIG_SYS_XEREADY | \
CONFIG_SYS_NONMONARCH | \
mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT |
CONFIG_SYS_FPGA_DONE |
CONFIG_SYS_XEREADY |
CONFIG_SYS_NONMONARCH |
CONFIG_SYS_REV1_2) << 5));
if (!(in32(GPIO0_IR) & CONFIG_SYS_REV1_2)) {
if (!(in_be32((void *)GPIO0_IR) & CONFIG_SYS_REV1_2)) {
/* rev 1.2 boards */
mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_INTA_FAKE | \
mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_INTA_FAKE |
CONFIG_SYS_SELF_RST) << 5));
}
out32(GPIO0_OR, 0);
out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY); /* setup for output */
out_be32((void *)GPIO0_OR, CONFIG_SYS_VPEN);
/* setup for output */
out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK |
CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY | CONFIG_SYS_VPEN);
/* - check if rev1_2 is low, then:
* - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST in TCR to assert INTA# or SELFRST#
/*
* - check if rev1_2 is low, then:
* - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST
* in TCR to assert INTA# or SELFRST#
*/
return 0;
}
/* ------------------------------------------------------------------------- */
int misc_init_r (void)
{
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_XEREADY); /* deassert EREADY# */
/* deassert EREADY# */
out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) | CONFIG_SYS_XEREADY);
return (0);
}
ushort pmc405_pci_subsys_deviceid(void)
{
ulong val;
val = in32(GPIO0_IR);
val = in_be32((void *)GPIO0_IR);
if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
if (val & CONFIG_SYS_NONMONARCH) { /* monarch# signal */
/* check monarch# signal */
if (val & CONFIG_SYS_NONMONARCH)
return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
}
return CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH;
}
return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
}
/*
* Check Board Identity:
* Check Board Identity
*/
int checkboard (void)
{
ulong val;
char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
int i = getenv_r("serial#", str, sizeof(str));
puts ("Board: ");
if (i == -1) {
if (i == -1)
puts ("### No HW ID - assuming PMC405");
} else {
else
puts(str);
}
val = in32(GPIO0_IR);
val = in_be32((void *)GPIO0_IR);
if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
puts(" rev1.2 (");
if (val & CONFIG_SYS_NONMONARCH) { /* monarch# signal */
if (val & CONFIG_SYS_NONMONARCH) /* monarch# signal */
puts("non-");
}
puts("monarch)");
} else {
} else
puts(" <=rev1.1");
}
putc ('\n');
return 0;
}
/* ------------------------------------------------------------------------- */
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
@ -166,43 +163,3 @@ void reset_phy(void)
lxt971_no_sleep();
#endif
}
int do_cantest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong addr;
volatile uchar *ptr;
volatile uchar val;
int i;
addr = simple_strtol (argv[1], NULL, 16) + 0x16;
i = 0;
for (;;) {
ptr = (uchar *)addr;
for (i=0; i<8; i++) {
*ptr = i;
val = *ptr;
if (val != i) {
printf("ERROR: addr=%p write=0x%02X, read=0x%02X\n", ptr, i, val);
return 0;
}
/* Abort if ctrl-c was pressed */
if (ctrlc()) {
puts("\nAbort\n");
return 0;
}
ptr++;
}
}
return 0;
}
U_BOOT_CMD(
cantest, 3, 1, do_cantest,
"Test CAN controller",
NULL
);

View File

@ -54,7 +54,6 @@ flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
static ulong flash_get_size (int portwidth, vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
static void flash_get_offsets (ulong base, flash_info_t *info);
static flash_info_t *flash_get_info(ulong base);
/*-----------------------------------------------------------------------
*/
@ -178,7 +177,7 @@ flash_get_offsets (ulong base, flash_info_t *info)
/*-----------------------------------------------------------------------
*/
static flash_info_t *flash_get_info(ulong base)
flash_info_t *flash_get_info(ulong base)
{
int i;
flash_info_t * info;

View File

@ -63,7 +63,6 @@ SECTIONS
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
lib_ppc/cache.o (.text)
lib_ppc/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv)

View File

@ -131,7 +131,7 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
n = mmc->block_dev.block_read(dev, blk, cnt, addr);
/* flush cache after read */
flush_cache((ulong)addr, cnt * 512); //FIXME
flush_cache((ulong)addr, cnt * 512); /* FIXME */
printf("%d blocks read: %s\n",
n, (n==cnt) ? "OK" : "ERROR");

View File

@ -546,7 +546,7 @@ int getenv_r (char *name, char *buf, unsigned len)
return (-1);
}
#if defined(CONFIG_CMD_ENV) && !defined(CONFIG_ENV_IS_NOWHERE)
#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{

View File

@ -40,15 +40,15 @@ int console_changed = 0;
* environment are used
*/
#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
extern int overwrite_console (void);
#define OVERWRITE_CONSOLE overwrite_console ()
extern int overwrite_console(void);
#define OVERWRITE_CONSOLE overwrite_console()
#else
#define OVERWRITE_CONSOLE 0
#endif /* CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE */
#endif /* CONFIG_SYS_CONSOLE_IS_IN_ENV */
static int console_setfile (int file, device_t * dev)
static int console_setfile(int file, device_t * dev)
{
int error = 0;
@ -61,7 +61,7 @@ static int console_setfile (int file, device_t * dev)
case stderr:
/* Start new device */
if (dev->start) {
error = dev->start ();
error = dev->start();
/* If it's not started dont use it */
if (error < 0)
break;
@ -106,7 +106,7 @@ int cd_count[MAX_FILES];
* only from fgetc() which assures it.
* No attempt is made to demultiplex multiple input sources.
*/
static int iomux_getc(void)
static int console_getc(int file)
{
unsigned char ret;
@ -116,7 +116,7 @@ static int iomux_getc(void)
return ret;
}
static int iomux_tstc(int file)
static int console_tstc(int file)
{
int i, ret;
device_t *dev;
@ -138,7 +138,7 @@ static int iomux_tstc(int file)
return 0;
}
static void iomux_putc(int file, const char c)
static void console_putc(int file, const char c)
{
int i;
device_t *dev;
@ -150,7 +150,7 @@ static void iomux_putc(int file, const char c)
}
}
static void iomux_puts(int file, const char *s)
static void console_puts(int file, const char *s)
{
int i;
device_t *dev;
@ -161,28 +161,68 @@ static void iomux_puts(int file, const char *s)
dev->puts(s);
}
}
static inline void console_printdevs(int file)
{
iomux_printdevs(file);
}
static inline void console_doenv(int file, device_t *dev)
{
iomux_doenv(file, dev->name);
}
#else
static inline int console_getc(int file)
{
return stdio_devices[file]->getc();
}
static inline int console_tstc(int file)
{
return stdio_devices[file]->tstc();
}
static inline void console_putc(int file, const char c)
{
stdio_devices[file]->putc(c);
}
static inline void console_puts(int file, const char *s)
{
stdio_devices[file]->puts(s);
}
static inline void console_printdevs(int file)
{
printf("%s\n", stdio_devices[file]->name);
}
static inline void console_doenv(int file, device_t *dev)
{
console_setfile(file, dev);
}
#endif /* defined(CONFIG_CONSOLE_MUX) */
/** U-Boot INITIAL CONSOLE-NOT COMPATIBLE FUNCTIONS *************************/
void serial_printf (const char *fmt, ...)
void serial_printf(const char *fmt, ...)
{
va_list args;
uint i;
char printbuffer[CONFIG_SYS_PBSIZE];
va_start (args, fmt);
va_start(args, fmt);
/* For this to work, printbuffer must be larger than
* anything we ever want to print.
*/
i = vsprintf (printbuffer, fmt, args);
va_end (args);
i = vsprintf(printbuffer, fmt, args);
va_end(args);
serial_puts (printbuffer);
serial_puts(printbuffer);
}
int fgetc (int file)
int fgetc(int file)
{
if (file < MAX_FILES) {
#if defined(CONFIG_CONSOLE_MUX)
@ -195,8 +235,8 @@ int fgetc (int file)
* check for that first.
*/
if (tstcdev != NULL)
return iomux_getc();
iomux_tstc(file);
return console_getc(file);
console_tstc(file);
#ifdef CONFIG_WATCHDOG
/*
* If the watchdog must be rate-limited then it should
@ -206,66 +246,54 @@ int fgetc (int file)
#endif
}
#else
return stdio_devices[file]->getc ();
return console_getc(file);
#endif
}
return -1;
}
int ftstc (int file)
int ftstc(int file)
{
if (file < MAX_FILES)
#if defined(CONFIG_CONSOLE_MUX)
return iomux_tstc(file);
#else
return stdio_devices[file]->tstc ();
#endif
return console_tstc(file);
return -1;
}
void fputc (int file, const char c)
void fputc(int file, const char c)
{
if (file < MAX_FILES)
#if defined(CONFIG_CONSOLE_MUX)
iomux_putc(file, c);
#else
stdio_devices[file]->putc (c);
#endif
console_putc(file, c);
}
void fputs (int file, const char *s)
void fputs(int file, const char *s)
{
if (file < MAX_FILES)
#if defined(CONFIG_CONSOLE_MUX)
iomux_puts(file, s);
#else
stdio_devices[file]->puts (s);
#endif
console_puts(file, s);
}
void fprintf (int file, const char *fmt, ...)
void fprintf(int file, const char *fmt, ...)
{
va_list args;
uint i;
char printbuffer[CONFIG_SYS_PBSIZE];
va_start (args, fmt);
va_start(args, fmt);
/* For this to work, printbuffer must be larger than
* anything we ever want to print.
*/
i = vsprintf (printbuffer, fmt, args);
va_end (args);
i = vsprintf(printbuffer, fmt, args);
va_end(args);
/* Send to desired file */
fputs (file, printbuffer);
fputs(file, printbuffer);
}
/** U-Boot INITIAL CONSOLE-COMPATIBLE FUNCTION *****************************/
int getc (void)
int getc(void)
{
#ifdef CONFIG_DISABLE_CONSOLE
if (gd->flags & GD_FLG_DISABLE_CONSOLE)
@ -274,14 +302,14 @@ int getc (void)
if (gd->flags & GD_FLG_DEVINIT) {
/* Get from the standard input */
return fgetc (stdin);
return fgetc(stdin);
}
/* Send directly to the handler */
return serial_getc ();
return serial_getc();
}
int tstc (void)
int tstc(void)
{
#ifdef CONFIG_DISABLE_CONSOLE
if (gd->flags & GD_FLG_DISABLE_CONSOLE)
@ -290,14 +318,14 @@ int tstc (void)
if (gd->flags & GD_FLG_DEVINIT) {
/* Test the standard input */
return ftstc (stdin);
return ftstc(stdin);
}
/* Send directly to the handler */
return serial_tstc ();
return serial_tstc();
}
void putc (const char c)
void putc(const char c)
{
#ifdef CONFIG_SILENT_CONSOLE
if (gd->flags & GD_FLG_SILENT)
@ -311,14 +339,14 @@ void putc (const char c)
if (gd->flags & GD_FLG_DEVINIT) {
/* Send to the standard output */
fputc (stdout, c);
fputc(stdout, c);
} else {
/* Send directly to the handler */
serial_putc (c);
serial_putc(c);
}
}
void puts (const char *s)
void puts(const char *s)
{
#ifdef CONFIG_SILENT_CONSOLE
if (gd->flags & GD_FLG_SILENT)
@ -332,32 +360,32 @@ void puts (const char *s)
if (gd->flags & GD_FLG_DEVINIT) {
/* Send to the standard output */
fputs (stdout, s);
fputs(stdout, s);
} else {
/* Send directly to the handler */
serial_puts (s);
serial_puts(s);
}
}
void printf (const char *fmt, ...)
void printf(const char *fmt, ...)
{
va_list args;
uint i;
char printbuffer[CONFIG_SYS_PBSIZE];
va_start (args, fmt);
va_start(args, fmt);
/* For this to work, printbuffer must be larger than
* anything we ever want to print.
*/
i = vsprintf (printbuffer, fmt, args);
va_end (args);
i = vsprintf(printbuffer, fmt, args);
va_end(args);
/* Print the string */
puts (printbuffer);
puts(printbuffer);
}
void vprintf (const char *fmt, va_list args)
void vprintf(const char *fmt, va_list args)
{
uint i;
char printbuffer[CONFIG_SYS_PBSIZE];
@ -365,20 +393,20 @@ void vprintf (const char *fmt, va_list args)
/* For this to work, printbuffer must be larger than
* anything we ever want to print.
*/
i = vsprintf (printbuffer, fmt, args);
i = vsprintf(printbuffer, fmt, args);
/* Print the string */
puts (printbuffer);
puts(printbuffer);
}
/* test if ctrl-c was pressed */
static int ctrlc_disabled = 0; /* see disable_ctrl() */
static int ctrlc_was_pressed = 0;
int ctrlc (void)
int ctrlc(void)
{
if (!ctrlc_disabled && gd->have_console) {
if (tstc ()) {
switch (getc ()) {
if (tstc()) {
switch (getc()) {
case 0x03: /* ^C - Control C */
ctrlc_was_pressed = 1;
return 1;
@ -393,7 +421,7 @@ int ctrlc (void)
/* pass 1 to disable ctrlc() checking, 0 to enable.
* returns previous state
*/
int disable_ctrlc (int disable)
int disable_ctrlc(int disable)
{
int prev = ctrlc_disabled; /* save previous state */
@ -406,7 +434,7 @@ int had_ctrlc (void)
return ctrlc_was_pressed;
}
void clear_ctrlc (void)
void clear_ctrlc(void)
{
ctrlc_was_pressed = 0;
}
@ -434,7 +462,8 @@ inline void dbg(const char *fmt, ...)
i = vsprintf(printbuffer, fmt, args);
va_end(args);
if ((screen + sizeof(screen) - 1 - cursor) < strlen(printbuffer)+1) {
if ((screen + sizeof(screen) - 1 - cursor)
< strlen(printbuffer) + 1) {
memset(screen, 0, sizeof(screen));
cursor = screen;
}
@ -450,19 +479,19 @@ inline void dbg(const char *fmt, ...)
/** U-Boot INIT FUNCTIONS *************************************************/
device_t *search_device (int flags, char *name)
device_t *search_device(int flags, char *name)
{
device_t *dev;
dev = device_get_by_name(name);
if(dev && (dev->flags & flags))
if (dev && (dev->flags & flags))
return dev;
return NULL;
}
int console_assign (int file, char *devname)
int console_assign(int file, char *devname)
{
int flag;
device_t *dev;
@ -484,14 +513,14 @@ int console_assign (int file, char *devname)
dev = search_device(flag, devname);
if(dev)
return console_setfile (file, dev);
if (dev)
return console_setfile(file, dev);
return -1;
}
/* Called before relocation - use serial functions */
int console_init_f (void)
int console_init_f(void)
{
gd->have_console = 1;
@ -500,12 +529,12 @@ int console_init_f (void)
gd->flags |= GD_FLG_SILENT;
#endif
return (0);
return 0;
}
#ifdef CONFIG_SYS_CONSOLE_IS_IN_ENV
/* Called after the relocation - use desired console functions */
int console_init_r (void)
int console_init_r(void)
{
char *stdinname, *stdoutname, *stderrname;
device_t *inputdev = NULL, *outputdev = NULL, *errdev = NULL;
@ -525,14 +554,14 @@ int console_init_r (void)
/* stdin stdout and stderr are in environment */
/* scan for it */
stdinname = getenv ("stdin");
stdoutname = getenv ("stdout");
stderrname = getenv ("stderr");
stdinname = getenv("stdin");
stdoutname = getenv("stdout");
stderrname = getenv("stderr");
if (OVERWRITE_CONSOLE == 0) { /* if not overwritten by config switch */
inputdev = search_device (DEV_FLAGS_INPUT, stdinname);
outputdev = search_device (DEV_FLAGS_OUTPUT, stdoutname);
errdev = search_device (DEV_FLAGS_OUTPUT, stderrname);
inputdev = search_device(DEV_FLAGS_INPUT, stdinname);
outputdev = search_device(DEV_FLAGS_OUTPUT, stdoutname);
errdev = search_device(DEV_FLAGS_OUTPUT, stderrname);
#ifdef CONFIG_CONSOLE_MUX
iomux_err = iomux_doenv(stdin, stdinname);
iomux_err += iomux_doenv(stdout, stdoutname);
@ -544,38 +573,26 @@ int console_init_r (void)
}
/* if the devices are overwritten or not found, use default device */
if (inputdev == NULL) {
inputdev = search_device (DEV_FLAGS_INPUT, "serial");
inputdev = search_device(DEV_FLAGS_INPUT, "serial");
}
if (outputdev == NULL) {
outputdev = search_device (DEV_FLAGS_OUTPUT, "serial");
outputdev = search_device(DEV_FLAGS_OUTPUT, "serial");
}
if (errdev == NULL) {
errdev = search_device (DEV_FLAGS_OUTPUT, "serial");
errdev = search_device(DEV_FLAGS_OUTPUT, "serial");
}
/* Initializes output console first */
if (outputdev != NULL) {
#ifdef CONFIG_CONSOLE_MUX
/* need to set a console if not done above. */
iomux_doenv(stdout, outputdev->name);
#else
console_setfile (stdout, outputdev);
#endif
console_doenv(stdout, outputdev);
}
if (errdev != NULL) {
#ifdef CONFIG_CONSOLE_MUX
/* need to set a console if not done above. */
iomux_doenv(stderr, errdev->name);
#else
console_setfile (stderr, errdev);
#endif
console_doenv(stderr, errdev);
}
if (inputdev != NULL) {
#ifdef CONFIG_CONSOLE_MUX
/* need to set a console if not done above. */
iomux_doenv(stdin, inputdev->name);
#else
console_setfile (stdin, inputdev);
#endif
console_doenv(stdin, inputdev);
}
#ifdef CONFIG_CONSOLE_MUX
@ -586,59 +603,47 @@ done:
#ifndef CONFIG_SYS_CONSOLE_INFO_QUIET
/* Print information */
puts ("In: ");
puts("In: ");
if (stdio_devices[stdin] == NULL) {
puts ("No input devices available!\n");
puts("No input devices available!\n");
} else {
#ifdef CONFIG_CONSOLE_MUX
iomux_printdevs(stdin);
#else
printf ("%s\n", stdio_devices[stdin]->name);
#endif
console_printdevs(stdin);
}
puts ("Out: ");
puts("Out: ");
if (stdio_devices[stdout] == NULL) {
puts ("No output devices available!\n");
puts("No output devices available!\n");
} else {
#ifdef CONFIG_CONSOLE_MUX
iomux_printdevs(stdout);
#else
printf ("%s\n", stdio_devices[stdout]->name);
#endif
console_printdevs(stdout);
}
puts ("Err: ");
puts("Err: ");
if (stdio_devices[stderr] == NULL) {
puts ("No error devices available!\n");
puts("No error devices available!\n");
} else {
#ifdef CONFIG_CONSOLE_MUX
iomux_printdevs(stderr);
#else
printf ("%s\n", stdio_devices[stderr]->name);
#endif
console_printdevs(stderr);
}
#endif /* CONFIG_SYS_CONSOLE_INFO_QUIET */
#ifdef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
/* set the environment variables (will overwrite previous env settings) */
for (i = 0; i < 3; i++) {
setenv (stdio_names[i], stdio_devices[i]->name);
setenv(stdio_names[i], stdio_devices[i]->name);
}
#endif /* CONFIG_SYS_CONSOLE_ENV_OVERWRITE */
#if 0
/* If nothing usable installed, use only the initial console */
if ((stdio_devices[stdin] == NULL) && (stdio_devices[stdout] == NULL))
return (0);
return 0;
#endif
return (0);
return 0;
}
#else /* CONFIG_SYS_CONSOLE_IS_IN_ENV */
/* Called after the relocation - use desired console functions */
int console_init_r (void)
int console_init_r(void)
{
device_t *inputdev = NULL, *outputdev = NULL;
int i;
@ -647,8 +652,10 @@ int console_init_r (void)
device_t *dev;
#ifdef CONFIG_SPLASH_SCREEN
/* suppress all output if splash screen is enabled and we have
a bmp to display */
/*
* suppress all output if splash screen is enabled and we have
* a bmp to display
*/
if (getenv("splashimage") != NULL)
gd->flags |= GD_FLG_SILENT;
#endif
@ -669,8 +676,8 @@ int console_init_r (void)
/* Initializes output console first */
if (outputdev != NULL) {
console_setfile (stdout, outputdev);
console_setfile (stderr, outputdev);
console_setfile(stdout, outputdev);
console_setfile(stderr, outputdev);
#ifdef CONFIG_CONSOLE_MUX
console_devices[stdout][0] = outputdev;
console_devices[stderr][0] = outputdev;
@ -679,7 +686,7 @@ int console_init_r (void)
/* Initializes input console */
if (inputdev != NULL) {
console_setfile (stdin, inputdev);
console_setfile(stdin, inputdev);
#ifdef CONFIG_CONSOLE_MUX
console_devices[stdin][0] = inputdev;
#endif
@ -689,40 +696,40 @@ int console_init_r (void)
#ifndef CONFIG_SYS_CONSOLE_INFO_QUIET
/* Print information */
puts ("In: ");
puts("In: ");
if (stdio_devices[stdin] == NULL) {
puts ("No input devices available!\n");
puts("No input devices available!\n");
} else {
printf ("%s\n", stdio_devices[stdin]->name);
printf("%s\n", stdio_devices[stdin]->name);
}
puts ("Out: ");
puts("Out: ");
if (stdio_devices[stdout] == NULL) {
puts ("No output devices available!\n");
puts("No output devices available!\n");
} else {
printf ("%s\n", stdio_devices[stdout]->name);
printf("%s\n", stdio_devices[stdout]->name);
}
puts ("Err: ");
puts("Err: ");
if (stdio_devices[stderr] == NULL) {
puts ("No error devices available!\n");
puts("No error devices available!\n");
} else {
printf ("%s\n", stdio_devices[stderr]->name);
printf("%s\n", stdio_devices[stderr]->name);
}
#endif /* CONFIG_SYS_CONSOLE_INFO_QUIET */
/* Setting environment variables */
for (i = 0; i < 3; i++) {
setenv (stdio_names[i], stdio_devices[i]->name);
setenv(stdio_names[i], stdio_devices[i]->name);
}
#if 0
/* If nothing usable installed, use only the initial console */
if ((stdio_devices[stdin] == NULL) && (stdio_devices[stdout] == NULL))
return (0);
return 0;
#endif
return (0);
return 0;
}
#endif /* CONFIG_SYS_CONSOLE_IS_IN_ENV */

View File

@ -34,10 +34,10 @@
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_FLASH)
#if defined(CONFIG_CMD_SAVEENV) && defined(CONFIG_CMD_FLASH)
#define CMD_SAVEENV
#elif defined(CONFIG_ENV_ADDR_REDUND)
#error Cannot use CONFIG_ENV_ADDR_REDUND without CONFIG_CMD_ENV & CONFIG_CMD_FLASH
#error Cannot use CONFIG_ENV_ADDR_REDUND without CONFIG_CMD_SAVEENV & CONFIG_CMD_FLASH
#endif
#if defined(CONFIG_ENV_SIZE_REDUND) && (CONFIG_ENV_SIZE_REDUND < CONFIG_ENV_SIZE)

View File

@ -39,10 +39,10 @@
#include <malloc.h>
#include <nand.h>
#if defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND)
#if defined(CONFIG_CMD_SAVEENV) && defined(CONFIG_CMD_NAND)
#define CMD_SAVEENV
#elif defined(CONFIG_ENV_OFFSET_REDUND)
#error Cannot use CONFIG_ENV_OFFSET_REDUND without CONFIG_CMD_ENV & CONFIG_CMD_NAND
#error Cannot use CONFIG_ENV_OFFSET_REDUND without CONFIG_CMD_SAVEENV & CONFIG_CMD_NAND
#endif
#if defined(CONFIG_ENV_SIZE_REDUND) && (CONFIG_ENV_SIZE_REDUND != CONFIG_ENV_SIZE)

View File

@ -147,7 +147,8 @@ int checkcpu (void)
puts("Clock Configuration:");
for (i = 0; i < CONFIG_NUM_CPUS; i++) {
if (!(i & 3)) printf ("\n ");
if (!(i & 3))
printf ("\n ");
printf("CPU%d:%-4s MHz, ",
i,strmhz(buf1, sysinfo.freqProcessor[i]));
}

View File

@ -1028,10 +1028,10 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
#endif
}
/* Set up 16GB inbound memory window at 0 */
/* Set up 4GB inbound memory window at 0 */
out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
out_le32(mbase + PECFG_BAR0HMPA, 0x7ffffff);
out_le32(mbase + PECFG_BAR0LMPA, 0);
out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);

View File

@ -28,11 +28,11 @@ include $(TOPDIR)/config.mk
LIB = $(obj)libdisk.a
COBJS-y += part.o
COBJS-y += part_mac.o
COBJS-y += part_dos.o
COBJS-y += part_iso.o
COBJS-y += part_amiga.o
COBJS-y += part_efi.o
COBJS-$(CONFIG_MAC_PARTITION) += part_mac.o
COBJS-$(CONFIG_DOS_PARTITION) += part_dos.o
COBJS-$(CONFIG_ISO_PARTITION) += part_iso.o
COBJS-$(CONFIG_AMIGA_PARTITION) += part_amiga.o
COBJS-$(CONFIG_EFI_PARTITION) += part_efi.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)

View File

@ -26,11 +26,11 @@
#include <ide.h>
#include "part_amiga.h"
#if (defined(CONFIG_CMD_IDE) || \
defined(CONFIG_CMD_SCSI) || \
defined(CONFIG_CMD_USB) || \
defined(CONFIG_MMC) || \
defined(CONFIG_SYSTEMACE) ) && defined(CONFIG_AMIGA_PARTITION)
#if defined(CONFIG_CMD_IDE) || \
defined(CONFIG_CMD_SCSI) || \
defined(CONFIG_CMD_USB) || \
defined(CONFIG_MMC) || \
defined(CONFIG_SYSTEMACE)
#undef AMIGA_DEBUG

View File

@ -35,12 +35,12 @@
#include <ide.h>
#include "part_dos.h"
#if (defined(CONFIG_CMD_IDE) || \
defined(CONFIG_CMD_SATA) || \
defined(CONFIG_CMD_SCSI) || \
defined(CONFIG_CMD_USB) || \
defined(CONFIG_MMC) || \
defined(CONFIG_SYSTEMACE) ) && defined(CONFIG_DOS_PARTITION)
#if defined(CONFIG_CMD_IDE) || \
defined(CONFIG_CMD_SATA) || \
defined(CONFIG_CMD_SCSI) || \
defined(CONFIG_CMD_USB) || \
defined(CONFIG_MMC) || \
defined(CONFIG_SYSTEMACE)
/* Convert char[4] in little endian format to the host format integer
*/

View File

@ -36,12 +36,12 @@
#include <malloc.h>
#include "part_efi.h"
#if (defined(CONFIG_CMD_IDE) || \
defined(CONFIG_CMD_SATA) || \
defined(CONFIG_CMD_SCSI) || \
defined(CONFIG_CMD_USB) || \
defined(CONFIG_MMC) || \
defined(CONFIG_SYSTEMACE) ) && defined(CONFIG_EFI_PARTITION)
#if defined(CONFIG_CMD_IDE) || \
defined(CONFIG_CMD_SATA) || \
defined(CONFIG_CMD_SCSI) || \
defined(CONFIG_CMD_USB) || \
defined(CONFIG_MMC) || \
defined(CONFIG_SYSTEMACE)
/* Convert char[2] in little endian format to the host format integer
*/

View File

@ -25,12 +25,12 @@
#include <command.h>
#include "part_iso.h"
#if (defined(CONFIG_CMD_IDE) || \
defined(CONFIG_CMD_SCSI) || \
defined(CONFIG_CMD_SATA) || \
defined(CONFIG_CMD_USB) || \
defined(CONFIG_MMC) || \
defined(CONFIG_SYSTEMACE) ) && defined(CONFIG_ISO_PARTITION)
#if defined(CONFIG_CMD_IDE) || \
defined(CONFIG_CMD_SCSI) || \
defined(CONFIG_CMD_SATA) || \
defined(CONFIG_CMD_USB) || \
defined(CONFIG_MMC) || \
defined(CONFIG_SYSTEMACE)
/* #define ISO_PART_DEBUG */

View File

@ -34,12 +34,12 @@
#include <ide.h>
#include "part_mac.h"
#if (defined(CONFIG_CMD_IDE) || \
defined(CONFIG_CMD_SCSI) || \
defined(CONFIG_CMD_SATA) || \
defined(CONFIG_CMD_USB) || \
defined(CONFIG_MMC) || \
defined(CONFIG_SYSTEMACE) ) && defined(CONFIG_MAC_PARTITION)
#if defined(CONFIG_CMD_IDE) || \
defined(CONFIG_CMD_SCSI) || \
defined(CONFIG_CMD_SATA) || \
defined(CONFIG_CMD_USB) || \
defined(CONFIG_MMC) || \
defined(CONFIG_SYSTEMACE)
/* stdlib.h causes some compatibility problems; should fixe these! -- wd */
#ifndef __ldiv_t_defined

View File

@ -96,7 +96,7 @@ static int sata_bus_softreset (int num)
}
if (status & ATA_BUSY) {
printf ("ata%u is slow to respond,plz be patient\n", port);
printf ("ata%u is slow to respond,plz be patient\n", num);
}
while ((status & ATA_BUSY)) {
@ -105,7 +105,7 @@ static int sata_bus_softreset (int num)
}
if (status & ATA_BUSY) {
printf ("ata%u failed to respond : ", port);
printf ("ata%u failed to respond : ", num);
printf ("bus reset failed\n");
port[num].dev_mask = 0;
return 1;

View File

@ -33,6 +33,7 @@ COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o
COBJS-$(CONFIG_DRIVER_CS8900) += cs8900.o
COBJS-$(CONFIG_TULIP) += dc2114x.o
COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o
COBJS-$(CONFIG_DNET) += dnet.o
COBJS-$(CONFIG_E1000) += e1000.o
COBJS-$(CONFIG_EEPRO100) += eepro100.o
COBJS-$(CONFIG_ENC28J60) += enc28j60.o

396
drivers/net/dnet.c Normal file
View File

@ -0,0 +1,396 @@
/*
* Dave Ethernet Controller driver
*
* Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <common.h>
#ifndef CONFIG_DNET_AUTONEG_TIMEOUT
#define CONFIG_DNET_AUTONEG_TIMEOUT 5000000 /* default value */
#endif
#include <net.h>
#include <malloc.h>
#include <linux/mii.h>
#include <miiphy.h>
#include <asm/io.h>
#include "dnet.h"
struct dnet_device {
struct dnet_registers *regs;
const struct device *dev;
struct eth_device netdev;
unsigned short phy_addr;
};
/* get struct dnet_device from given struct netdev */
#define to_dnet(_nd) container_of(_nd, struct dnet_device, netdev)
/* function for reading internal MAC register */
u16 dnet_readw_mac(struct dnet_device *dnet, u16 reg)
{
u16 data_read;
/* issue a read */
writel(reg, &dnet->regs->MACREG_ADDR);
/* since a read/write op to the MAC is very slow,
* we must wait before reading the data */
udelay(1);
/* read data read from the MAC register */
data_read = readl(&dnet->regs->MACREG_DATA);
/* all done */
return data_read;
}
/* function for writing internal MAC register */
void dnet_writew_mac(struct dnet_device *dnet, u16 reg, u16 val)
{
/* load data to write */
writel(val, &dnet->regs->MACREG_DATA);
/* issue a write */
writel(reg | DNET_INTERNAL_WRITE, &dnet->regs->MACREG_ADDR);
/* since a read/write op to the MAC is very slow,
* we must wait before exiting */
udelay(1);
}
static void dnet_mdio_write(struct dnet_device *dnet, u8 reg, u16 value)
{
u16 tmp;
debug(DRIVERNAME "dnet_mdio_write %02x:%02x <- %04x\n",
dnet->phy_addr, reg, value);
while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
DNET_INTERNAL_GMII_MNG_CMD_FIN))
;
/* prepare for a write operation */
tmp = (1 << 13);
/* only 5 bits allowed for register offset */
reg &= 0x1f;
/* prepare reg_value for a write */
tmp |= (dnet->phy_addr << 8);
tmp |= reg;
/* write data to write first */
dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_DAT_REG, value);
/* write control word */
dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG, tmp);
while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
DNET_INTERNAL_GMII_MNG_CMD_FIN))
;
}
static u16 dnet_mdio_read(struct dnet_device *dnet, u8 reg)
{
u16 value;
while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
DNET_INTERNAL_GMII_MNG_CMD_FIN))
;
/* only 5 bits allowed for register offset*/
reg &= 0x1f;
/* prepare reg_value for a read */
value = (dnet->phy_addr << 8);
value |= reg;
/* write control word */
dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG, value);
/* wait for end of transfer */
while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
DNET_INTERNAL_GMII_MNG_CMD_FIN))
;
value = dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_DAT_REG);
debug(DRIVERNAME "dnet_mdio_read %02x:%02x <- %04x\n",
dnet->phy_addr, reg, value);
return value;
}
static int dnet_send(struct eth_device *netdev, volatile void *packet,
int length)
{
struct dnet_device *dnet = to_dnet(netdev);
int i, len, wrsz;
unsigned int *bufp;
unsigned int tx_cmd;
debug(DRIVERNAME "[%s] Sending %u bytes\n", __func__, length);
/* frame size (words) */
len = (length + 3) >> 2;
bufp = (unsigned int *) (((u32)packet) & 0xFFFFFFFC);
wrsz = (u32)length + 3;
wrsz += ((u32)packet) & 0x3;
wrsz >>= 2;
tx_cmd = ((((unsigned int)(packet)) & 0x03) << 16) | (u32)length;
/* check if there is enough room for the current frame */
if (wrsz < (DNET_FIFO_SIZE - readl(&dnet->regs->TX_FIFO_WCNT))) {
for (i = 0; i < wrsz; i++)
writel(*bufp++, &dnet->regs->TX_DATA_FIFO);
/*
* inform MAC that a packet's written and ready
* to be shipped out
*/
writel(tx_cmd, &dnet->regs->TX_LEN_FIFO);
} else {
printf(DRIVERNAME "No free space (actual %d, required %d "
"(words))\n", DNET_FIFO_SIZE -
readl(&dnet->regs->TX_FIFO_WCNT), wrsz);
}
/* No one cares anyway */
return 0;
}
static int dnet_recv(struct eth_device *netdev)
{
struct dnet_device *dnet = to_dnet(netdev);
unsigned int *data_ptr;
int pkt_len, poll, i;
u32 cmd_word;
debug("Waiting for pkt (polling)\n");
poll = 50;
while ((readl(&dnet->regs->RX_FIFO_WCNT) >> 16) == 0) {
udelay(10); /* wait 10 usec */
if (--poll == 0)
return 0; /* no pkt available */
}
cmd_word = readl(&dnet->regs->RX_LEN_FIFO);
pkt_len = cmd_word & 0xFFFF;
debug("Got pkt with size %d bytes\n", pkt_len);
if (cmd_word & 0xDF180000)
printf("%s packet receive error %x\n", __func__, cmd_word);
data_ptr = (unsigned int *) NetRxPackets[0];
for (i = 0; i < (pkt_len + 3) >> 2; i++)
*data_ptr++ = readl(&dnet->regs->RX_DATA_FIFO);
NetReceive(NetRxPackets[0], pkt_len + 5); /* ok + 5 ?? */
return 0;
}
static void dnet_set_hwaddr(struct eth_device *netdev)
{
struct dnet_device *dnet = to_dnet(netdev);
u16 tmp;
tmp = cpu_to_be16(*((u16 *)netdev->enetaddr));
dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_0_REG, tmp);
tmp = cpu_to_be16(*((u16 *)(netdev->enetaddr + 2)));
dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_1_REG, tmp);
tmp = cpu_to_be16(*((u16 *)(netdev->enetaddr + 4)));
dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_2_REG, tmp);
}
static void dnet_phy_reset(struct dnet_device *dnet)
{
struct eth_device *netdev = &dnet->netdev;
int i;
u16 status, adv;
adv = ADVERTISE_CSMA | ADVERTISE_ALL;
dnet_mdio_write(dnet, MII_ADVERTISE, adv);
printf("%s: Starting autonegotiation...\n", netdev->name);
dnet_mdio_write(dnet, MII_BMCR, (BMCR_ANENABLE
| BMCR_ANRESTART));
for (i = 0; i < CONFIG_DNET_AUTONEG_TIMEOUT / 100; i++) {
status = dnet_mdio_read(dnet, MII_BMSR);
if (status & BMSR_ANEGCOMPLETE)
break;
udelay(100);
}
if (status & BMSR_ANEGCOMPLETE)
printf("%s: Autonegotiation complete\n", netdev->name);
else
printf("%s: Autonegotiation timed out (status=0x%04x)\n",
netdev->name, status);
}
static int dnet_phy_init(struct dnet_device *dnet)
{
struct eth_device *netdev = &dnet->netdev;
u16 phy_id, status, adv, lpa;
int media, speed, duplex;
int i;
u32 ctl_reg;
/* Find a PHY */
for (i = 0; i < 32; i++) {
dnet->phy_addr = i;
phy_id = dnet_mdio_read(dnet, MII_PHYSID1);
if (phy_id != 0xffff) {
/* ok we found it */
printf("Found PHY at address %d PHYID (%04x:%04x)\n",
i, phy_id,
dnet_mdio_read(dnet, MII_PHYSID2));
break;
}
}
/* Check if the PHY is up to snuff... */
phy_id = dnet_mdio_read(dnet, MII_PHYSID1);
if (phy_id == 0xffff) {
printf("%s: No PHY present\n", netdev->name);
return -1;
}
status = dnet_mdio_read(dnet, MII_BMSR);
if (!(status & BMSR_LSTATUS)) {
/* Try to re-negotiate if we don't have link already. */
dnet_phy_reset(dnet);
for (i = 0; i < CONFIG_DNET_AUTONEG_TIMEOUT / 100; i++) {
status = dnet_mdio_read(dnet, MII_BMSR);
if (status & BMSR_LSTATUS)
break;
udelay(100);
}
}
if (!(status & BMSR_LSTATUS)) {
printf("%s: link down (status: 0x%04x)\n",
netdev->name, status);
return -1;
} else {
adv = dnet_mdio_read(dnet, MII_ADVERTISE);
lpa = dnet_mdio_read(dnet, MII_LPA);
media = mii_nway_result(lpa & adv);
speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
? 1 : 0);
duplex = (media & ADVERTISE_FULL) ? 1 : 0;
/* 1000BaseT ethernet is not supported */
printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
netdev->name,
speed ? "100" : "10",
duplex ? "full" : "half",
lpa);
ctl_reg = dnet_readw_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG);
if (duplex)
ctl_reg &= ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP);
else
ctl_reg |= DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP;
dnet_writew_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg);
return 0;
}
}
static int dnet_init(struct eth_device *netdev, bd_t *bd)
{
struct dnet_device *dnet = to_dnet(netdev);
u32 config;
/*
* dnet_halt should have been called at some point before now,
* so we'll assume the controller is idle.
*/
/* set hardware address */
dnet_set_hwaddr(netdev);
if (dnet_phy_init(dnet) < 0)
return -1;
/* flush rx/tx fifos */
writel(DNET_SYS_CTL_RXFIFOFLUSH | DNET_SYS_CTL_TXFIFOFLUSH,
&dnet->regs->SYS_CTL);
udelay(1000);
writel(0, &dnet->regs->SYS_CTL);
config = dnet_readw_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG);
config |= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE |
DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST |
DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL |
DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS;
dnet_writew_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG, config);
/* Enable TX and RX */
dnet_writew_mac(dnet, DNET_INTERNAL_MODE_REG,
DNET_INTERNAL_MODE_RXEN | DNET_INTERNAL_MODE_TXEN);
return 0;
}
static void dnet_halt(struct eth_device *netdev)
{
struct dnet_device *dnet = to_dnet(netdev);
/* Disable TX and RX */
dnet_writew_mac(dnet, DNET_INTERNAL_MODE_REG, 0);
}
int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr)
{
struct dnet_device *dnet;
struct eth_device *netdev;
unsigned int dev_capa;
dnet = malloc(sizeof(struct dnet_device));
if (!dnet) {
printf("Error: Failed to allocate memory for DNET%d\n", id);
return -1;
}
memset(dnet, 0, sizeof(struct dnet_device));
netdev = &dnet->netdev;
dnet->regs = (struct dnet_registers *)regs;
dnet->phy_addr = phy_addr;
sprintf(netdev->name, "dnet%d", id);
netdev->init = dnet_init;
netdev->halt = dnet_halt;
netdev->send = dnet_send;
netdev->recv = dnet_recv;
dev_capa = readl(&dnet->regs->VERCAPS) & 0xFFFF;
debug("%s: has %smdio, %sirq, %sgigabit, %sdma \n", netdev->name,
(dev_capa & DNET_HAS_MDIO) ? "" : "no ",
(dev_capa & DNET_HAS_IRQ) ? "" : "no ",
(dev_capa & DNET_HAS_GIGABIT) ? "" : "no ",
(dev_capa & DNET_HAS_DMA) ? "" : "no ");
eth_register(netdev);
return 0;
}

166
drivers/net/dnet.h Normal file
View File

@ -0,0 +1,166 @@
/*
* Dave Ethernet Controller driver
*
* Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __DRIVERS_DNET_H__
#define __DRIVERS_DNET_H__
#define DRIVERNAME "dnet"
struct dnet_registers {
/* ALL DNET FIFO REGISTERS */
u32 RX_LEN_FIFO;
u32 RX_DATA_FIFO;
u32 TX_LEN_FIFO;
u32 TX_DATA_FIFO;
u32 pad1[0x3c];
/* ALL DNET CONTROL/STATUS REGISTERS */
u32 VERCAPS;
u32 INTR_SRC;
u32 INTR_ENB;
u32 RX_STATUS;
u32 TX_STATUS;
u32 RX_FRAMES_CNT;
u32 TX_FRAMES_CNT;
u32 RX_FIFO_TH;
u32 TX_FIFO_TH;
u32 SYS_CTL;
u32 PAUSE_TMR;
u32 RX_FIFO_WCNT;
u32 TX_FIFO_WCNT;
u32 pad2[0x33];
/* ALL DNET MAC REGISTERS */
u32 MACREG_DATA; /* Mac-Reg Data */
u32 MACREG_ADDR; /* Mac-Reg Addr */
u32 pad3[0x3e];
/* ALL DNET RX STATISTICS COUNTERS */
u32 RX_PKT_IGNR_CNT;
u32 RX_LEN_CHK_ERR_CNT;
u32 RX_LNG_FRM_CNT;
u32 RX_SHRT_FRM_CNT;
u32 RX_IPG_VIOL_CNT;
u32 RX_CRC_ERR_CNT;
u32 RX_OK_PKT_CNT;
u32 RX_CTL_FRM_CNT;
u32 RX_PAUSE_FRM_CNT;
u32 RX_MULTICAST_CNT;
u32 RX_BROADCAST_CNT;
u32 RX_VLAN_TAG_CNT;
u32 RX_PRE_SHRINK_CNT;
u32 RX_DRIB_NIB_CNT;
u32 RX_UNSUP_OPCD_CNT;
u32 RX_BYTE_CNT;
u32 pad4[0x30];
/* DNET TX STATISTICS COUNTERS */
u32 TX_UNICAST_CNT;
u32 TX_PAUSE_FRM_CNT;
u32 TX_MULTICAST_CNT;
u32 TX_BRDCAST_CNT;
u32 TX_VLAN_TAG_CNT;
u32 TX_BAD_FCS_CNT;
u32 TX_JUMBO_CNT;
u32 TX_BYTE_CNT;
};
/* SOME INTERNAL MAC-CORE REGISTER */
#define DNET_INTERNAL_MODE_REG 0x0
#define DNET_INTERNAL_RXTX_CONTROL_REG 0x2
#define DNET_INTERNAL_MAX_PKT_SIZE_REG 0x4
#define DNET_INTERNAL_IGP_REG 0x8
#define DNET_INTERNAL_MAC_ADDR_0_REG 0xa
#define DNET_INTERNAL_MAC_ADDR_1_REG 0xc
#define DNET_INTERNAL_MAC_ADDR_2_REG 0xe
#define DNET_INTERNAL_TX_RX_STS_REG 0x12
#define DNET_INTERNAL_GMII_MNG_CTL_REG 0x14
#define DNET_INTERNAL_GMII_MNG_DAT_REG 0x16
#define DNET_INTERNAL_GMII_MNG_CMD_FIN (1 << 14)
#define DNET_INTERNAL_WRITE (1 << 31)
/* MAC-CORE REGISTER FIELDS */
/* MAC-CORE MODE REGISTER FIELDS */
#define DNET_INTERNAL_MODE_GBITEN (1 << 0)
#define DNET_INTERNAL_MODE_FCEN (1 << 1)
#define DNET_INTERNAL_MODE_RXEN (1 << 2)
#define DNET_INTERNAL_MODE_TXEN (1 << 3)
/* MAC-CORE RXTX CONTROL REGISTER FIELDS */
#define DNET_INTERNAL_RXTX_CONTROL_RXSHORTFRAME (1 << 8)
#define DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST (1 << 7)
#define DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST (1 << 4)
#define DNET_INTERNAL_RXTX_CONTROL_RXPAUSE (1 << 3)
#define DNET_INTERNAL_RXTX_CONTROL_DISTXFCS (1 << 2)
#define DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS (1 << 1)
#define DNET_INTERNAL_RXTX_CONTROL_ENPROMISC (1 << 0)
#define DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL (1 << 6)
#define DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP (1 << 5)
/* SYSTEM CONTROL REGISTER FIELDS */
#define DNET_SYS_CTL_IGNORENEXTPKT (1 << 0)
#define DNET_SYS_CTL_SENDPAUSE (1 << 2)
#define DNET_SYS_CTL_RXFIFOFLUSH (1 << 3)
#define DNET_SYS_CTL_TXFIFOFLUSH (1 << 4)
/* TX STATUS REGISTER FIELDS */
#define DNET_TX_STATUS_FIFO_ALMOST_EMPTY (1 << 2)
#define DNET_TX_STATUS_FIFO_ALMOST_FULL (1 << 1)
/* INTERRUPT SOURCE REGISTER FIELDS */
#define DNET_INTR_SRC_TX_PKTSENT (1 << 0)
#define DNET_INTR_SRC_TX_FIFOAF (1 << 1)
#define DNET_INTR_SRC_TX_FIFOAE (1 << 2)
#define DNET_INTR_SRC_TX_DISCFRM (1 << 3)
#define DNET_INTR_SRC_TX_FIFOFULL (1 << 4)
#define DNET_INTR_SRC_RX_CMDFIFOAF (1 << 8)
#define DNET_INTR_SRC_RX_CMDFIFOFF (1 << 9)
#define DNET_INTR_SRC_RX_DATAFIFOFF (1 << 10)
#define DNET_INTR_SRC_TX_SUMMARY (1 << 16)
#define DNET_INTR_SRC_RX_SUMMARY (1 << 17)
#define DNET_INTR_SRC_PHY (1 << 19)
/* INTERRUPT ENABLE REGISTER FIELDS */
#define DNET_INTR_ENB_TX_PKTSENT (1 << 0)
#define DNET_INTR_ENB_TX_FIFOAF (1 << 1)
#define DNET_INTR_ENB_TX_FIFOAE (1 << 2)
#define DNET_INTR_ENB_TX_DISCFRM (1 << 3)
#define DNET_INTR_ENB_TX_FIFOFULL (1 << 4)
#define DNET_INTR_ENB_RX_PKTRDY (1 << 8)
#define DNET_INTR_ENB_RX_FIFOAF (1 << 9)
#define DNET_INTR_ENB_RX_FIFOERR (1 << 10)
#define DNET_INTR_ENB_RX_ERROR (1 << 11)
#define DNET_INTR_ENB_RX_FIFOFULL (1 << 12)
#define DNET_INTR_ENB_RX_FIFOAE (1 << 13)
#define DNET_INTR_ENB_TX_SUMMARY (1 << 16)
#define DNET_INTR_ENB_RX_SUMMARY (1 << 17)
#define DNET_INTR_ENB_GLOBAL_ENABLE (1 << 18)
/*
* Capabilities. Used by the driver to know the capabilities that
* the ethernet controller inside the FPGA have.
*/
#define DNET_HAS_MDIO (1 << 0)
#define DNET_HAS_IRQ (1 << 1)
#define DNET_HAS_GIGABIT (1 << 2)
#define DNET_HAS_DMA (1 << 3)
#define DNET_HAS_MII (1 << 4) /* or GMII */
#define DNET_HAS_RMII (1 << 5) /* or RGMII */
#define DNET_CAPS_MASK 0xFFFF
#define DNET_FIFO_SIZE 2048 /* 2K x 32 bit */
#define DNET_FIFO_TX_DATA_AF_TH (DNET_FIFO_SIZE - 384) /* 384 = 1536 / 4 */
#define DNET_FIFO_TX_DATA_AE_TH (384)
#define DNET_FIFO_RX_CMD_AF_TH (1 << 16) /* just one frame inside the FIFO */
#endif

View File

@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libpcmcia.a
COBJS-$(CONFIG_I82365) += i82365.o
COBJS-y += mpc8xx_pcmcia.o
COBJS-$(CONFIG_8xx) += mpc8xx_pcmcia.o
COBJS-$(CONFIG_PXA_PCMCIA) += pxa_pcmcia.o
COBJS-y += rpx_pcmcia.o
COBJS-$(CONFIG_IDE_TI_CARDBUS) += ti_pci1410a.o

View File

@ -1,7 +1,5 @@
#include <common.h>
#if defined(CONFIG_8xx)
#include <mpc8xx.h>
#endif
#include <pcmcia.h>
#undef CONFIG_PCMCIA
@ -14,7 +12,7 @@
#define CONFIG_PCMCIA
#endif
#if defined(CONFIG_8xx) && defined(CONFIG_PCMCIA)
#if defined(CONFIG_PCMCIA)
#if defined(CONFIG_IDE_8xx_PCCARD)
extern int check_ide_device (int slot);
@ -301,4 +299,4 @@ static u_int m8xx_get_speed(u_int ns, u_int is_io)
}
#endif /* 0 */
#endif /* CONFIG_8xx && CONFIG_PCMCIA */
#endif /* CONFIG_PCMCIA */

View File

@ -39,6 +39,7 @@ void NS16550_init (NS16550_t com_port, int baud_divisor)
#endif
}
#ifndef CONFIG_NS16550_MIN_FUNCTIONS
void NS16550_reinit (NS16550_t com_port, int baud_divisor)
{
com_port->ier = 0x00;
@ -53,6 +54,7 @@ void NS16550_reinit (NS16550_t com_port, int baud_divisor)
com_port->dlm = (baud_divisor >> 8) & 0xff;
com_port->lcr = LCRVAL;
}
#endif /* CONFIG_NS16550_MIN_FUNCTIONS */
void NS16550_putc (NS16550_t com_port, char c)
{
@ -60,6 +62,7 @@ void NS16550_putc (NS16550_t com_port, char c)
com_port->thr = c;
}
#ifndef CONFIG_NS16550_MIN_FUNCTIONS
char NS16550_getc (NS16550_t com_port)
{
while ((com_port->lsr & LSR_DR) == 0) {
@ -76,4 +79,5 @@ int NS16550_tstc (NS16550_t com_port)
return ((com_port->lsr & LSR_DR) != 0);
}
#endif /* CONFIG_NS16550_MIN_FUNCTIONS */
#endif

View File

@ -57,6 +57,7 @@
#define API_ENOMEM 3 /* no memory */
#define API_EBUSY 4 /* busy, occupied etc. */
#define API_EIO 5 /* I/O error */
#define API_ESYSC 6 /* syscall error */
typedef int (*scp_t)(int, int *, ...);

View File

@ -86,6 +86,16 @@
#define WDOG_BASE 0x53FDC000
/*
* GPIO
*/
#define GPIO1_BASE 0x53FCC000
#define GPIO2_BASE 0x53FD0000
#define GPIO3_BASE 0x53FA4000
#define GPIO_DR 0x00000000 /* data register */
#define GPIO_GDIR 0x00000004 /* direction register */
#define GPIO_PSR 0x00000008 /* pad status register */
/*
* Signal Multiplexing (IOMUX)
*/

View File

@ -33,7 +33,7 @@
#define CONFIG_CMD_ECHO /* echo arguments */
#define CONFIG_CMD_EEPROM /* EEPROM read/write support */
#define CONFIG_CMD_ELF /* ELF (VxWorks) load/boot cmd */
#define CONFIG_CMD_ENV /* saveenv */
#define CONFIG_CMD_SAVEENV /* saveenv */
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_FDC /* Floppy Disk Support */

View File

@ -21,11 +21,13 @@
#define CONFIG_CMD_BOOTD /* bootd */
#define CONFIG_CMD_CONSOLE /* coninfo */
#define CONFIG_CMD_ECHO /* echo arguments */
#define CONFIG_CMD_ENV /* saveenv */
#define CONFIG_CMD_SAVEENV /* saveenv */
#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
#define CONFIG_CMD_IMI /* iminfo */
#ifndef CONFIG_SYS_NO_FLASH
#define CONFIG_CMD_IMLS /* List all found images */
#endif
#define CONFIG_CMD_ITEST /* Integer (and string) test */
#define CONFIG_CMD_LOADB /* loadb */
#define CONFIG_CMD_LOADS /* loads */

View File

@ -86,7 +86,7 @@
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_CONSOLE
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_ECHO

View File

@ -170,7 +170,7 @@
#define CONFIG_CMD_BDI
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IRQ

View File

@ -170,7 +170,7 @@
#define CONFIG_CMD_BDI
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IRQ

View File

@ -114,7 +114,7 @@
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH

View File

@ -83,7 +83,7 @@
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_NET

View File

@ -430,7 +430,7 @@
#define CONFIG_CMD_PCI
#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif

View File

@ -434,7 +434,7 @@
#define CONFIG_CMD_PCI
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif

View File

@ -427,7 +427,7 @@
#define CONFIG_CMD_PCI
#endif
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif

View File

@ -441,7 +441,7 @@
#endif
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif

View File

@ -509,7 +509,7 @@
#endif
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif

View File

@ -470,7 +470,7 @@
#endif
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif

View File

@ -376,7 +376,7 @@
#endif
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif

View File

@ -497,7 +497,7 @@ extern int board_pci_host_broken(void);
#endif
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif

View File

@ -481,7 +481,7 @@
#endif
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif

View File

@ -423,7 +423,7 @@
#endif
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif

View File

@ -300,7 +300,7 @@
#endif
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif

View File

@ -457,7 +457,7 @@
#endif
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif

View File

@ -489,7 +489,7 @@
#define CONFIG_CMD_MII
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#endif
#if defined(CONFIG_PCI)

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@ -649,7 +649,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#endif
#if defined(CONFIG_PCI)

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@ -85,7 +85,7 @@
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IRQ

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@ -92,7 +92,7 @@
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_RUN

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@ -40,7 +40,7 @@
#define CONFIG_CMD_NFS
#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3

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@ -57,7 +57,7 @@
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_BDI
#define CONFIG_CMD_CONSOLE

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@ -137,7 +137,7 @@
*/
#define CONFIG_CMD_BDI
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IRQ

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@ -177,7 +177,7 @@
#define CONFIG_CMD_BDI
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IRQ

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@ -331,7 +331,7 @@
#endif
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif

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@ -330,7 +330,7 @@
#endif
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif

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@ -12,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -21,16 +21,11 @@
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
@ -45,13 +40,22 @@
#define CONFIG_BAUDRATE 9600
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#undef CONFIG_BOOTARGS
#undef CONFIG_BOOTCOMMAND
/* Only interrupt boot if space is pressed. */
#define CONFIG_AUTOBOOT_KEYED 1
#define CONFIG_AUTOBOOT_PROMPT \
"Press SPACE to abort autoboot in %d seconds\n", bootdelay
#undef CONFIG_AUTOBOOT_DELAY_STR
#define CONFIG_AUTOBOOT_STOP_STR " "
#define CONFIG_PREBOOT /* enable preboot variable */
#undef CONFIG_BOOTARGS
#undef CONFIG_BOOTCOMMAND
#define CONFIG_PREBOOT /* enable preboot variable */
#define CFG_BOOTM_LEN 0x1000000 /* support booting of huge images */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
@ -59,11 +63,8 @@
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */
/*
* BOOTP options
@ -73,7 +74,6 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
@ -91,249 +91,241 @@
#define CONFIG_CMD_UNIVERSE
#define CONFIG_CMD_EEPROM
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible */
#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#ifdef CONFIG_SYS_HUSH_PARSER
#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Sz */
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock */
#define CONFIG_SYS_BASE_BAUD 806400
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
57600, 115200, 230400, 460800, 921600 }
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
#define CONFIG_SYS_RX_ETH_BUFFER 16
/*-----------------------------------------------------------------------
/*
* PCI stuff
*-----------------------------------------------------------------------
*/
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config */
#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID: Non-Monarch */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID: Monarch */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid()
#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* Processor/PPC */
#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#if 1
#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs */
#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */
#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
#else /* old mapping */
#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
#endif
/*-----------------------------------------------------------------------
#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable */
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs */
#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */
#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* 128 kB for malloc() */
#define CONFIG_PRAM 0 /* use pram variable to overwrite */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
/*
* FLASH organization
*/
#define CONFIG_SYS_FLASH_BASE 0xFE000000
#define CONFIG_SYS_FLASH_INCREMENT 0x01000000
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* don't use hardware protection */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT }
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* don't use hardware protection */
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST {{0xfff80000, 0x80000}}
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (faster) */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT}
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on fli */
/*
* JFFS2 partitions - second bank contains u-boot
*
*/
/* No command line, one static partition, whole device */
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV "nor0"
#define CONFIG_JFFS2_PART_SIZE 0x01b00000
#define CONFIG_JFFS2_PART_OFFSET 0x00400000
/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=pmc405-0"
#define MTDPARTS_DEFAULT "mtdparts=pmc405-0:-(jffs2)"
*/
/*-----------------------------------------------------------------------
* Environment Variable setup
*/
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
/* total size of a CAT24WC16 is 2048 bytes */
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
/* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_OFFSET 0x000
#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars */
/*-----------------------------------------------------------------------
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
/*
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24W16 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24W16 has */
/* 16 byte page write mode using*/
/* last 4 bits of the address */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
/* last 4 bits of the address */
/*-----------------------------------------------------------------------
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
/*
* External Bus Controller (EBC) Setup
*/
#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */
#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */
#define CAN_BA 0xF0000000 /* CAN Base Address */
#define RTC_BA 0xF0000500 /* RTC Base Address */
#define NVRAM_BA 0xF0200000 /* NVRAM Base Address */
#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */
#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */
#define CAN_BA 0xF0000000 /* CAN Base Addres */
#define RTC_BA 0xF0000500 /* RTC Base Address */
#define NVRAM_BA 0xF0200000 /* NVRAM Base Address */
/* Memory Bank 0 (Flash Bank 0) initialization */
/* Memory Bank 0 (Flash Bank 0) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x92015480
#define CONFIG_SYS_EBC_PB0CR FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
/* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
#define CONFIG_SYS_EBC_PB0CR (FLASH0_BA | 0x9A000)
/* Memory Bank 1 (Flash Bank 1) initialization */
/* Memory Bank 1 (Flash Bank 1) initialization */
#define CONFIG_SYS_EBC_PB1AP 0x92015480
#define CONFIG_SYS_EBC_PB1CR FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
/* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
#define CONFIG_SYS_EBC_PB1CR (FLASH1_BA | 0x9A000)
/* Memory Bank 2 (CAN0, 1, RTC) initialization */
#define CONFIG_SYS_EBC_PB2AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
#define CONFIG_SYS_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
/* Memory Bank 2 (CAN0, 1, RTC) initialization */
/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
#define CONFIG_SYS_EBC_PB2AP 0x03000440
/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
#define CONFIG_SYS_EBC_PB2CR (CAN_BA | 0x18000)
/* Memory Bank 3 -> unused */
/* Memory Bank 4 (NVRAM) initialization */
#define CONFIG_SYS_EBC_PB4AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
#define CONFIG_SYS_EBC_PB4CR NVRAM_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
/* Memory Bank 4 (NVRAM) initialization */
/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
#define CONFIG_SYS_EBC_PB4AP 0x03000440
/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
#define CONFIG_SYS_EBC_PB4CR (NVRAM_BA | 0x18000)
/*-----------------------------------------------------------------------
/*
* FPGA stuff
*/
#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
#define CONFIG_SYS_FPGA_MAX_SIZE (32 * 1024) /* 32kByte for CPLD */
/* FPGA program pin configuration */
#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (output) */
#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (output) */
#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO pin (output) */
#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI pin (input) */
#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
/* pass Ethernet MAC to VxWorks */
#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000
/*-----------------------------------------------------------------------
/*
* GPIOs
*/
#define CONFIG_SYS_NONMONARCH (0x80000000 >> 14) /* GPIO24 */
#define CONFIG_SYS_XEREADY (0x80000000 >> 15) /* GPIO15 */
#define CONFIG_SYS_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */
#define CONFIG_SYS_SELF_RST (0x80000000 >> 21) /* GPIO21 */
#define CONFIG_SYS_REV1_2 (0x80000000 >> 23) /* GPIO23 */
#define CONFIG_SYS_VPEN (0x80000000 >> 3) /* GPIO3 */
#define CONFIG_SYS_NONMONARCH (0x80000000 >> 14) /* GPIO14 */
#define CONFIG_SYS_XEREADY (0x80000000 >> 15) /* GPIO15 */
#define CONFIG_SYS_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */
#define CONFIG_SYS_SELF_RST (0x80000000 >> 21) /* GPIO21 */
#define CONFIG_SYS_REV1_2 (0x80000000 >> 23) /* GPIO23 */
/*-----------------------------------------------------------------------
/*
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
/* use on chip memory (OCM) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM 1
/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
/* inside of SDRAM */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
/* End of used area in RAM */
#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE
/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
@ -341,7 +333,10 @@
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#endif /* __CONFIG_H */
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#endif /* __CONFIG_H */

View File

@ -61,7 +61,7 @@
#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS

View File

@ -211,7 +211,7 @@
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CONSOLE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IMMAP

View File

@ -211,7 +211,7 @@
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CONSOLE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IMMAP

View File

@ -382,7 +382,7 @@
#endif
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif

View File

@ -205,6 +205,9 @@
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#ifdef CONFIG_NAND_SPL
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
@ -332,7 +335,7 @@
#define CONFIG_CMD_JFFS2
#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif

View File

@ -67,7 +67,7 @@
#define CONFIG_CMD_IDE
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_FLASH

View File

@ -81,8 +81,8 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
"bootfile=tqm8260/uImage\0" \
"kernel_addr=40080000\0" \
"ramdisk_addr=40200000\0" \
"kernel_addr=400C0000\0" \
"ramdisk_addr=40240000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"

View File

@ -340,7 +340,7 @@ extern int tqm834x_num_flash_banks;
#endif
#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif

View File

@ -154,7 +154,7 @@
#define CONFIG_CMD_BDI
#define CONFIG_CMD_CONSOLE
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IMLS

View File

@ -330,7 +330,7 @@
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2

View File

@ -375,7 +375,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2

View File

@ -40,7 +40,7 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_IDE
#define CONFIG_CMD_EXT2
#define CONFIG_DOS_PARTITION

View File

@ -73,7 +73,7 @@
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#define CONFIG_BOOTDELAY 0

View File

@ -73,7 +73,7 @@
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#define CONFIG_BOOTDELAY 0

View File

@ -69,7 +69,7 @@
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BDI
#define CONFIG_CMD_CONSOLE
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_RUN
#define CONFIG_CMD_IMI

View File

@ -78,7 +78,7 @@
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_RUN
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_ECHO

View File

@ -97,7 +97,7 @@
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_BEDBUG
#undef CONFIG_CMD_ELF
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_FAT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_MII

View File

@ -108,7 +108,7 @@
#else
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_NAND
#define CONFIG_CMD_I2C

View File

@ -75,7 +75,7 @@
#define CONFIG_CMD_BOOTD /* bootd */
#define CONFIG_CMD_CONSOLE /* coninfo */
#define CONFIG_CMD_ECHO /* echo arguments */
#define CONFIG_CMD_ENV /* saveenv */
#define CONFIG_CMD_SAVEENV /* saveenv */
#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
#define CONFIG_CMD_IMI /* iminfo */

View File

@ -77,7 +77,7 @@
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_PCI

View File

@ -90,7 +90,7 @@
#define CONFIG_CMD_IDE
#define CONFIG_CMD_DHCP
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_FAT
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_FPGA

View File

@ -73,7 +73,7 @@
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IMI

View File

@ -85,7 +85,7 @@
*/
#define CONFIG_CMD_BDI
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_MEMORY

View File

@ -305,7 +305,7 @@
#endif
#if defined(CFG_RAMBOOT)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif

View File

@ -69,7 +69,7 @@
*/
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_RUN

View File

@ -154,7 +154,7 @@
#define CONFIG_CMD_IMI
#define CONFIG_CMD_NFS
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_AUTO_COMPLETE

View File

@ -248,7 +248,7 @@
#define CONFIG_CMD_JFFS2
#if !defined(RAMENV)
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SAVES
#endif
#else

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