arm: imx-common: init: extend init_aips to support imx7
Extend init_aips to support imx7 SoC, use is_soc_type and is_cpu_type to resolve at run time aips3 settings Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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@ -13,16 +13,11 @@
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void init_aips(void)
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void init_aips(void)
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{
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{
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struct aipstz_regs *aips1, *aips2;
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struct aipstz_regs *aips1, *aips2, *aips3;
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#ifdef CONFIG_MX6SX
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struct aipstz_regs *aips3;
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#endif
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aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
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aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
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aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
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aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
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#ifdef CONFIG_MX6SX
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aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
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aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
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#endif
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/*
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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@ -49,25 +44,26 @@ void init_aips(void)
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writel(0x00000000, &aips2->opacr3);
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writel(0x00000000, &aips2->opacr3);
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writel(0x00000000, &aips2->opacr4);
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writel(0x00000000, &aips2->opacr4);
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#ifdef CONFIG_MX6SX
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if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7))
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/*
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{
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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/*
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* not forced to user-mode.
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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*/
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* not forced to user-mode.
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writel(0x77777777, &aips3->mprot0);
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*/
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writel(0x77777777, &aips3->mprot1);
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writel(0x77777777, &aips3->mprot0);
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writel(0x77777777, &aips3->mprot1);
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/*
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/*
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* Set all OPACRx to be non-bufferable, not require
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* Set all OPACRx to be non-bufferable, not require
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* supervisor privilege level for access,allow for
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* supervisor privilege level for access,allow for
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* write access and untrusted master access.
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* write access and untrusted master access.
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*/
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*/
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writel(0x00000000, &aips3->opacr0);
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writel(0x00000000, &aips3->opacr0);
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writel(0x00000000, &aips3->opacr1);
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writel(0x00000000, &aips3->opacr1);
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writel(0x00000000, &aips3->opacr2);
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writel(0x00000000, &aips3->opacr2);
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writel(0x00000000, &aips3->opacr3);
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writel(0x00000000, &aips3->opacr3);
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writel(0x00000000, &aips3->opacr4);
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writel(0x00000000, &aips3->opacr4);
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#endif
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}
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}
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}
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#define SRC_SCR_WARM_RESET_ENABLE 0
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#define SRC_SCR_WARM_RESET_ENABLE 0
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