mx6: Disable Power Down Bit of watchdog
On a mx6qsabresd revision C board with rev1.2 mx6q, the system gets resetted and it is not able to reach the Linux prompt. Comparing the watchdog behaviour on a revB versus revC board: - On a mx6qsabresd revB: U-Boot > reset resetting ... U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46) CPU: Freescale i.MX6Q rev1.1 at 792 MHz Reset cause: WDOG ... - On a mx6qsabresd revC: U-Boot > reset resetting ... U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46) CPU: Freescale i.MX6Q rev1.1 at 792 MHz Reset cause: POR So due to revC POR/watchdog circuitry whenever a watchdog occurs, it causes a POR. Clearing the PDE - Power Down Enable bit of WMCR registers fixes the problem and is also safe for all mx6 boards. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
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@ -30,6 +30,7 @@
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#include <asm/arch/clock.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/imx-common/boot_mode.h>
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#include <asm/imx-common/boot_mode.h>
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#include <stdbool.h>
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struct scu_regs {
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struct scu_regs {
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u32 ctrl;
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u32 ctrl;
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@ -121,12 +122,23 @@ void set_vddsoc(u32 mv)
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writel(reg, &anatop->reg_core);
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writel(reg, &anatop->reg_core);
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}
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}
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static void imx_set_wdog_powerdown(bool enable)
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{
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struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
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struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
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/* Write to the PDE (Power Down Enable) bit */
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writew(enable, &wdog1->wmcr);
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writew(enable, &wdog2->wmcr);
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}
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int arch_cpu_init(void)
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int arch_cpu_init(void)
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{
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{
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init_aips();
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init_aips();
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set_vddsoc(1200); /* Set VDDSOC to 1.2V */
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set_vddsoc(1200); /* Set VDDSOC to 1.2V */
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imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
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return 0;
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return 0;
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}
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}
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@ -601,5 +601,13 @@ struct iomuxc_base_regs {
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u32 daisy[104]; /* 0x7b0..94c */
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u32 daisy[104]; /* 0x7b0..94c */
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};
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};
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struct wdog_regs {
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u16 wcr; /* Control */
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u16 wsr; /* Service */
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u16 wrsr; /* Reset Status */
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u16 wicr; /* Interrupt Control */
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u16 wmcr; /* Miscellaneous Control */
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};
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#endif /* __ASSEMBLER__*/
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#endif /* __ASSEMBLER__*/
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#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
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#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
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