From f33c9305830d5f8b996a2aaea66591dc93143fe5 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Fri, 5 Sep 2014 12:49:48 +0200 Subject: [PATCH 1/8] mmc: dw_mmc: cleanups The dw_mmc driver was responding to errors with debug(). Change that to prinf()/puts() respectively so that any errors are immediately obvious. Also adjust english in comments. Signed-off-by: Pavel Machek Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Cc: Pantelis Antoniou Acked-by: Chin Liang See --- drivers/mmc/dw_mmc.c | 34 ++++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 0df30bc045..785eed567c 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -119,7 +119,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { if (get_timer(start) > timeout) { - printf("Timeout on data busy\n"); + printf("%s: Timeout on data busy\n", __func__); return TIMEOUT; } } @@ -177,14 +177,24 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, } } - if (i == retry) + if (i == retry) { + printf("%s: Timeout.\n", __func__); return TIMEOUT; + } if (mask & DWMCI_INTMSK_RTO) { - debug("Response Timeout..\n"); + /* + * Timeout here is not necessarily fatal. (e)MMC cards + * will splat here when they receive CMD55 as they do + * not support this command and that is exactly the way + * to tell them apart from SD cards. Thus, this output + * below shall be debug(). eMMC cards also do not favor + * CMD8, please keep that in mind. + */ + debug("%s: Response Timeout.\n", __func__); return TIMEOUT; } else if (mask & DWMCI_INTMSK_RE) { - debug("Response Error..\n"); + printf("%s: Response Error.\n", __func__); return -1; } @@ -204,7 +214,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, do { mask = dwmci_readl(host, DWMCI_RINTSTS); if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { - debug("DATA ERROR!\n"); + printf("%s: DATA ERROR!\n", __func__); return -1; } } while (!(mask & DWMCI_INTMSK_DTO)); @@ -232,16 +242,16 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) if ((freq == host->clock) || (freq == 0)) return 0; /* - * If host->get_mmc_clk didn't define, + * If host->get_mmc_clk isn't defined, * then assume that host->bus_hz is source clock value. - * host->bus_hz should be set from user. + * host->bus_hz should be set by user. */ if (host->get_mmc_clk) sclk = host->get_mmc_clk(host); else if (host->bus_hz) sclk = host->bus_hz; else { - printf("Didn't get source clock value..\n"); + printf("%s: Didn't get source clock value.\n", __func__); return -EINVAL; } @@ -260,7 +270,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) do { status = dwmci_readl(host, DWMCI_CMD); if (timeout-- < 0) { - printf("TIMEOUT error!!\n"); + printf("%s: Timeout!\n", __func__); return -ETIMEDOUT; } } while (status & DWMCI_CMD_START); @@ -275,7 +285,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) do { status = dwmci_readl(host, DWMCI_CMD); if (timeout-- < 0) { - printf("TIMEOUT error!!\n"); + printf("%s: Timeout!\n", __func__); return -ETIMEDOUT; } } while (status & DWMCI_CMD_START); @@ -290,7 +300,7 @@ static void dwmci_set_ios(struct mmc *mmc) struct dwmci_host *host = (struct dwmci_host *)mmc->priv; u32 ctype, regs; - debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock); + debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock); dwmci_setup_bus(host, mmc->clock); switch (mmc->bus_width) { @@ -329,7 +339,7 @@ static int dwmci_init(struct mmc *mmc) dwmci_writel(host, DWMCI_PWREN, 1); if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) { - debug("%s[%d] Fail-reset!!\n",__func__,__LINE__); + printf("%s[%d] Fail-reset!!\n", __func__, __LINE__); return -1; } From 1bf29b3d5571bed2b61581e839599337968deb80 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 01:18:15 +0200 Subject: [PATCH 2/8] mmc: dw_mmc: Fix cache alignment issue The DMA descriptors used by the DW MMC block must be aligned to cacheline size, otherwise we are unable to properly flush/inval cache over them and we get data corruption. The reason I chose this approach of expanding the structure is because the driver allocates the descriptors in bulk. This approach does waste space by inserting slop inbetween the descriptors, but it makes access to the descriptors easy as the compiler does know the real size of the structure. It also makes cache operations easy, since the size of the structure is cache aligned and the structure start address is as well. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Cc: Pantelis Antoniou Acked-by: Pavel Machek --- include/dwmmc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/dwmmc.h b/include/dwmmc.h index b67f11b113..109f7c8ac7 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -157,7 +157,7 @@ struct dwmci_idmac { u32 cnt; u32 addr; u32 next_addr; -}; +} __aligned(ARCH_DMA_MINALIGN); static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val) { From 464eec6d42cbdb5a57573d40ba64aad0e92aa689 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Tue, 9 Sep 2014 02:45:03 +0200 Subject: [PATCH 3/8] net: Remove unused CONFIG_DW_SEARCH_PHY from configs Remove this symbol from configs, since it's unused. Signed-off-by: Pavel Machek Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Cc: Joe Hershberger Acked-by: Chin Liang See --- include/configs/axs101.h | 1 - include/configs/socfpga_cyclone5.h | 1 - 2 files changed, 2 deletions(-) diff --git a/include/configs/axs101.h b/include/configs/axs101.h index c22d6d0c75..1bf8390722 100644 --- a/include/configs/axs101.h +++ b/include/configs/axs101.h @@ -125,7 +125,6 @@ */ #define CONFIG_DESIGNWARE_ETH #define CONFIG_DW_AUTONEG -#define CONFIG_DW_SEARCH_PHY #define CONFIG_NET_MULTI /* diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 5d145cd821..39e9368340 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -225,7 +225,6 @@ /* designware */ #define CONFIG_NET_MULTI #define CONFIG_DW_ALTDESCRIPTOR -#define CONFIG_DW_SEARCH_PHY #define CONFIG_MII #define CONFIG_PHY_GIGE #define CONFIG_DW_AUTONEG From 58ec63d6bcbe392ebed83197c90dc743f3b9e701 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Tue, 9 Sep 2014 14:26:51 +0200 Subject: [PATCH 4/8] net: phy: Cleanup drivers/net/phy/micrel.c Old saying says that more than three exclamation marks in a row are sign of mental disease. Cleanup micrel.c. Signed-off-by: Pavel Machek Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Cc: Joe Hershberger Acked-by: Chin Liang See --- drivers/net/phy/micrel.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 5d7e3be52e..507b9a368b 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -25,8 +25,7 @@ static struct phy_driver KSZ804_driver = { #ifndef CONFIG_PHY_MICREL_KSZ9021 /* * I can't believe Micrel used the exact same part number - * for the KSZ9021 - * Shame Micrel, Shame!!!!! + * for the KSZ9021. Shame Micrel, Shame! */ static struct phy_driver KS8721_driver = { .name = "Micrel KS8721BL", @@ -40,7 +39,7 @@ static struct phy_driver KS8721_driver = { #endif -/** +/* * KSZ9021 - KSZ9031 common */ @@ -69,8 +68,8 @@ static int ksz90xx_startup(struct phy_device *phydev) phydev->speed = SPEED_10; return 0; } -#ifdef CONFIG_PHY_MICREL_KSZ9021 +#ifdef CONFIG_PHY_MICREL_KSZ9021 /* * KSZ9021 */ From 4f68678b1941af7d75f391d1189c776fb434dc08 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 00:50:37 +0200 Subject: [PATCH 5/8] net: dwc: Fix cache alignment issues Fix remaining cache alignment issues in the DWC Ethernet driver. Please note that the cache handling in the driver is making the code hideous and thus the next patch cleans that up. In order to make this change reviewable though, the cleanup is split from it. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Cc: Joe Hershberger Acked-by: Pavel Machek --- drivers/net/designware.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 7186e3b491..aaf146d444 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -303,7 +303,8 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) /* Flush data to be sent */ flush_dcache_range((unsigned long)desc_p->dmamac_addr, - (unsigned long)desc_p->dmamac_addr + length); + (unsigned long)desc_p->dmamac_addr + + roundup(length, ARCH_DMA_MINALIGN)); #if defined(CONFIG_DW_ALTDESCRIPTOR) desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; @@ -372,7 +373,8 @@ static int dw_eth_recv(struct eth_device *dev) /* Flush only status field - others weren't changed */ flush_dcache_range((unsigned long)&desc_p->txrx_status, (unsigned long)&desc_p->txrx_status + - sizeof(desc_p->txrx_status)); + roundup(sizeof(desc_p->txrx_status), + ARCH_DMA_MINALIGN)); /* Test the wrap-around condition. */ if (++desc_num >= CONFIG_RX_DESCR_NUM) From 96cec17d3cd22ca2251d6f7946409933a231ce6f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 01:05:23 +0200 Subject: [PATCH 6/8] net: dwc: Make the cache handling less cryptic Add a few new variables to make the cache handling less cryptic. Add a variable for DMA and DATA descriptor start and end, so the correctness of the code is easier to inspect. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Cc: Joe Hershberger Acked-by: Pavel Machek Acked-by: Chin Liang See --- drivers/net/designware.c | 48 +++++++++++++++++++--------------------- 1 file changed, 23 insertions(+), 25 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index aaf146d444..9ded8950b8 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -279,19 +279,21 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) struct eth_dma_regs *dma_p = priv->dma_regs_p; u32 desc_num = priv->tx_currdescnum; struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; - + uint32_t desc_start = (uint32_t)desc_p; + uint32_t desc_end = desc_start + + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); + uint32_t data_start = (uint32_t)desc_p->dmamac_addr; + uint32_t data_end = data_start + + roundup(length, ARCH_DMA_MINALIGN); /* * Strictly we only need to invalidate the "txrx_status" field * for the following check, but on some platforms we cannot - * invalidate only 4 bytes, so roundup to - * ARCH_DMA_MINALIGN. This is safe because the individual - * descriptors in the array are each aligned to - * ARCH_DMA_MINALIGN. + * invalidate only 4 bytes, so we flush the entire descriptor, + * which is 16 bytes in total. This is safe because the + * individual descriptors in the array are each aligned to + * ARCH_DMA_MINALIGN and padded appropriately. */ - invalidate_dcache_range( - (unsigned long)desc_p, - (unsigned long)desc_p + - roundup(sizeof(desc_p->txrx_status), ARCH_DMA_MINALIGN)); + invalidate_dcache_range(desc_start, desc_end); /* Check if the descriptor is owned by CPU */ if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { @@ -299,12 +301,10 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) return -1; } - memcpy((void *)desc_p->dmamac_addr, packet, length); + memcpy(desc_p->dmamac_addr, packet, length); /* Flush data to be sent */ - flush_dcache_range((unsigned long)desc_p->dmamac_addr, - (unsigned long)desc_p->dmamac_addr + - roundup(length, ARCH_DMA_MINALIGN)); + flush_dcache_range(data_start, data_end); #if defined(CONFIG_DW_ALTDESCRIPTOR) desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; @@ -322,8 +322,7 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) #endif /* Flush modified buffer descriptor */ - flush_dcache_range((unsigned long)desc_p, - (unsigned long)desc_p + sizeof(struct dmamacdescr)); + flush_dcache_range(desc_start, desc_end); /* Test the wrap-around condition. */ if (++desc_num >= CONFIG_TX_DESCR_NUM) @@ -343,11 +342,14 @@ static int dw_eth_recv(struct eth_device *dev) u32 status, desc_num = priv->rx_currdescnum; struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; int length = 0; + uint32_t desc_start = (uint32_t)desc_p; + uint32_t desc_end = desc_start + + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); + uint32_t data_start = (uint32_t)desc_p->dmamac_addr; + uint32_t data_end; /* Invalidate entire buffer descriptor */ - invalidate_dcache_range((unsigned long)desc_p, - (unsigned long)desc_p + - sizeof(struct dmamacdescr)); + invalidate_dcache_range(desc_start, desc_end); status = desc_p->txrx_status; @@ -358,9 +360,8 @@ static int dw_eth_recv(struct eth_device *dev) DESC_RXSTS_FRMLENSHFT; /* Invalidate received data */ - invalidate_dcache_range((unsigned long)desc_p->dmamac_addr, - (unsigned long)desc_p->dmamac_addr + - roundup(length, ARCH_DMA_MINALIGN)); + data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); + invalidate_dcache_range(data_start, data_end); NetReceive(desc_p->dmamac_addr, length); @@ -371,10 +372,7 @@ static int dw_eth_recv(struct eth_device *dev) desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; /* Flush only status field - others weren't changed */ - flush_dcache_range((unsigned long)&desc_p->txrx_status, - (unsigned long)&desc_p->txrx_status + - roundup(sizeof(desc_p->txrx_status), - ARCH_DMA_MINALIGN)); + flush_dcache_range(desc_start, desc_end); /* Test the wrap-around condition. */ if (++desc_num >= CONFIG_RX_DESCR_NUM) From 832472a94d1adb4f1f86e491a2387c43c960b4e2 Mon Sep 17 00:00:00 2001 From: Charles Manning Date: Thu, 6 Mar 2014 15:40:50 +1300 Subject: [PATCH 7/8] tools: socfpga: Add socfpga preloader signing to mkimage Like many platforms, the Altera socfpga platform requires that the preloader be "signed" in a certain way or the built-in boot ROM will not boot the code. This change automatically creates an appropriately signed preloader from an SPL image. The signed image includes a CRC which must, of course, be generated with a CRC generator that the SoCFPGA boot ROM agrees with otherwise the boot ROM will reject the image. Unfortunately the CRC used in this boot ROM is not the same as the Adler CRC in lib/crc32.c. Indeed the Adler code is not technically a CRC but is more correctly described as a checksum. Thus, the appropriate CRC generator is added to lib/ as crc32_alt.c. Signed-off-by: Charles Manning Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek V2: - Zap unused constant - Explicitly print an error message in case of error - Rework the hdr_checksum() function to take the *header directly instead of a plan buffer pointer --- common/image.c | 1 + include/image.h | 1 + tools/Makefile | 1 + tools/imagetool.c | 2 + tools/imagetool.h | 1 + tools/socfpgaimage.c | 259 +++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 265 insertions(+) create mode 100644 tools/socfpgaimage.c diff --git a/common/image.c b/common/image.c index 38b56e3deb..085771c763 100644 --- a/common/image.c +++ b/common/image.c @@ -138,6 +138,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_PBLIMAGE, "pblimage", "Freescale PBL Boot Image",}, { IH_TYPE_RAMDISK, "ramdisk", "RAMDisk Image", }, { IH_TYPE_SCRIPT, "script", "Script", }, + { IH_TYPE_SOCFPGAIMAGE, "socfpgaimage", "Altera SOCFPGA preloader",}, { IH_TYPE_STANDALONE, "standalone", "Standalone Program", }, { IH_TYPE_UBLIMAGE, "ublimage", "Davinci UBL image",}, { IH_TYPE_MXSIMAGE, "mxsimage", "Freescale MXS Boot Image",}, diff --git a/include/image.h b/include/image.h index 340105658c..4347532520 100644 --- a/include/image.h +++ b/include/image.h @@ -232,6 +232,7 @@ struct lmb; #define IH_TYPE_MXSIMAGE 16 /* Freescale MXSBoot Image */ #define IH_TYPE_GPIMAGE 17 /* TI Keystone GPHeader Image */ #define IH_TYPE_ATMELIMAGE 18 /* ATMEL ROM bootable Image */ +#define IH_TYPE_SOCFPGAIMAGE 19 /* Altera SOCFPGA Preloader */ /* * Compression Types diff --git a/tools/Makefile b/tools/Makefile index 90e966d893..2b05b202a0 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -87,6 +87,7 @@ dumpimage-mkimage-objs := aisimage.o \ os_support.o \ pblimage.o \ pbl_crc32.o \ + socfpgaimage.o \ lib/sha1.o \ lib/sha256.o \ ublimage.o \ diff --git a/tools/imagetool.c b/tools/imagetool.c index 32d6278edb..98717bdedd 100644 --- a/tools/imagetool.c +++ b/tools/imagetool.c @@ -47,6 +47,8 @@ void register_image_tool(imagetool_register_t image_register) init_ubl_image_type(); /* Init Davinci AIS support */ init_ais_image_type(); + /* Init Altera SOCFPGA support */ + init_socfpga_image_type(); /* Init TI Keystone boot image generation/list support */ init_gpimage_type(); } diff --git a/tools/imagetool.h b/tools/imagetool.h index c8af0e82f8..8bce059482 100644 --- a/tools/imagetool.h +++ b/tools/imagetool.h @@ -168,6 +168,7 @@ void init_mxs_image_type(void); void init_fit_image_type(void); void init_ubl_image_type(void); void init_omap_image_type(void); +void init_socfpga_image_type(void); void init_gpimage_type(void); void pbl_load_uboot(int fd, struct image_tool_params *mparams); diff --git a/tools/socfpgaimage.c b/tools/socfpgaimage.c new file mode 100644 index 0000000000..396d8a5472 --- /dev/null +++ b/tools/socfpgaimage.c @@ -0,0 +1,259 @@ +/* + * Copyright (C) 2014 Charles Manning + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Reference doc http://www.altera.com.cn/literature/hb/cyclone-v/cv_5400A.pdf + * Note this doc is not entirely accurate. Of particular interest to us is the + * "header" length field being in U32s and not bytes. + * + * "Header" is a structure of the following format. + * this is positioned at 0x40. + * + * Endian is LSB. + * + * Offset Length Usage + * ----------------------- + * 0x40 4 Validation word 0x31305341 + * 0x44 1 Version (whatever, zero is fine) + * 0x45 1 Flags (unused, zero is fine) + * 0x46 2 Length (in units of u32, including the end checksum). + * 0x48 2 Zero + * 0x4A 2 Checksum over the header. NB Not CRC32 + * + * At the end of the code we have a 32-bit CRC checksum over whole binary + * excluding the CRC. + * + * Note that the CRC used here is **not** the zlib/Adler crc32. It is the + * CRC-32 used in bzip2, ethernet and elsewhere. + * + * The image is padded out to 64k, because that is what is + * typically used to write the image to the boot medium. + */ + +#include "pbl_crc32.h" +#include "imagetool.h" +#include + +#define HEADER_OFFSET 0x40 +#define VALIDATION_WORD 0x31305341 +#define PADDED_SIZE 0x10000 + +/* To allow for adding CRC, the max input size is a bit smaller. */ +#define MAX_INPUT_SIZE (PADDED_SIZE - sizeof(uint32_t)) + +static uint8_t buffer[PADDED_SIZE]; + +static struct socfpga_header { + uint32_t validation; + uint8_t version; + uint8_t flags; + uint16_t length_u32; + uint16_t zero; + uint16_t checksum; +} header; + +/* + * The header checksum is just a very simple checksum over + * the header area. + * There is still a crc32 over the whole lot. + */ +static uint16_t hdr_checksum(struct socfpga_header *header) +{ + int len = sizeof(*header) - sizeof(header->checksum); + uint8_t *buf = (uint8_t *)header; + uint16_t ret = 0; + + while (--len) + ret += *buf++; + + return ret; +} + + +static void build_header(uint8_t *buf, uint8_t version, uint8_t flags, + uint16_t length_bytes) +{ + header.validation = htole32(VALIDATION_WORD); + header.version = version; + header.flags = flags; + header.length_u32 = htole16(length_bytes/4); + header.zero = 0; + header.checksum = htole16(hdr_checksum(&header)); + + memcpy(buf, &header, sizeof(header)); +} + +/* + * Perform a rudimentary verification of header and return + * size of image. + */ +static int verify_header(const uint8_t *buf) +{ + memcpy(&header, buf, sizeof(header)); + + if (le32toh(header.validation) != VALIDATION_WORD) + return -1; + if (le16toh(header.checksum) != hdr_checksum(&header)) + return -1; + + return le16toh(header.length_u32) * 4; +} + +/* Sign the buffer and return the signed buffer size */ +static int sign_buffer(uint8_t *buf, + uint8_t version, uint8_t flags, + int len, int pad_64k) +{ + uint32_t calc_crc; + + /* Align the length up */ + len = (len + 3) & (~3); + + /* Build header, adding 4 bytes to length to hold the CRC32. */ + build_header(buf + HEADER_OFFSET, version, flags, len + 4); + + /* Calculate and apply the CRC */ + calc_crc = ~pbl_crc32(0, (char *)buf, len); + + *((uint32_t *)(buf + len)) = htole32(calc_crc); + + if (!pad_64k) + return len + 4; + + return PADDED_SIZE; +} + +/* Verify that the buffer looks sane */ +static int verify_buffer(const uint8_t *buf) +{ + int len; /* Including 32bit CRC */ + uint32_t calc_crc; + uint32_t buf_crc; + + len = verify_header(buf + HEADER_OFFSET); + if (len < 0) { + fprintf(stderr, "Invalid header\n"); + return -1; + } + + if (len < HEADER_OFFSET || len > PADDED_SIZE) { + fprintf(stderr, "Invalid header length (%i)\n", len); + return -1; + } + + /* + * Adjust length to the base of the CRC. + * Check the CRC. + */ + len -= 4; + + calc_crc = ~pbl_crc32(0, (const char *)buf, len); + + buf_crc = le32toh(*((uint32_t *)(buf + len))); + + if (buf_crc != calc_crc) { + fprintf(stderr, "CRC32 does not match (%08x != %08x)\n", + buf_crc, calc_crc); + return -1; + } + + return 0; +} + +/* mkimage glue functions */ +static int socfpgaimage_verify_header(unsigned char *ptr, int image_size, + struct image_tool_params *params) +{ + if (image_size != PADDED_SIZE) + return -1; + + return verify_buffer(ptr); +} + +static void socfpgaimage_print_header(const void *ptr) +{ + if (verify_buffer(ptr) == 0) + printf("Looks like a sane SOCFPGA preloader\n"); + else + printf("Not a sane SOCFPGA preloader\n"); +} + +static int socfpgaimage_check_params(struct image_tool_params *params) +{ + /* Not sure if we should be accepting fflags */ + return (params->dflag && (params->fflag || params->lflag)) || + (params->fflag && (params->dflag || params->lflag)) || + (params->lflag && (params->dflag || params->fflag)); +} + +static int socfpgaimage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_SOCFPGAIMAGE) + return EXIT_SUCCESS; + return EXIT_FAILURE; +} + +/* + * To work in with the mkimage framework, we do some ugly stuff... + * + * First, socfpgaimage_vrec_header() is called. + * We prepend a fake header big enough to make the file PADDED_SIZE. + * This gives us enough space to do what we want later. + * + * Next, socfpgaimage_set_header() is called. + * We fix up the buffer by moving the image to the start of the buffer. + * We now have some room to do what we need (add CRC and padding). + */ + +static int data_size; +#define FAKE_HEADER_SIZE (PADDED_SIZE - data_size) + +static int socfpgaimage_vrec_header(struct image_tool_params *params, + struct image_type_params *tparams) +{ + struct stat sbuf; + + if (params->datafile && + stat(params->datafile, &sbuf) == 0 && + sbuf.st_size <= MAX_INPUT_SIZE) { + data_size = sbuf.st_size; + tparams->header_size = FAKE_HEADER_SIZE; + } + return 0; +} + +static void socfpgaimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) +{ + uint8_t *buf = (uint8_t *)ptr; + + /* + * This function is called after vrec_header() has been called. + * At this stage we have the FAKE_HEADER_SIZE dummy bytes followed by + * data_size image bytes. Total = PADDED_SIZE. + * We need to fix the buffer by moving the image bytes back to + * the beginning of the buffer, then actually do the signing stuff... + */ + memmove(buf, buf + FAKE_HEADER_SIZE, data_size); + memset(buf + data_size, 0, FAKE_HEADER_SIZE); + + sign_buffer(buf, 0, 0, data_size, 0); +} + +static struct image_type_params socfpgaimage_params = { + .name = "Altera SOCFPGA preloader support", + .vrec_header = socfpgaimage_vrec_header, + .header_size = 0, /* This will be modified by vrec_header() */ + .hdr = (void *)buffer, + .check_image_type = socfpgaimage_check_image_types, + .verify_header = socfpgaimage_verify_header, + .print_header = socfpgaimage_print_header, + .set_header = socfpgaimage_set_header, + .check_params = socfpgaimage_check_params, +}; + +void init_socfpga_image_type(void) +{ + register_image_type(&socfpgaimage_params); +} From ff7e9700eda14ccf8ebe399d3831ef266e743c2d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 02:44:36 +0200 Subject: [PATCH 8/8] arm: cache: Add support for write-allocate D-Cache Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek --- arch/arm/include/asm/system.h | 1 + arch/arm/lib/cache-cp15.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index d51ba668f3..ca2d44faf4 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -185,6 +185,7 @@ enum dcache_option { DCACHE_OFF = 0x12, DCACHE_WRITETHROUGH = 0x1a, DCACHE_WRITEBACK = 0x1e, + DCACHE_WRITEALLOC = 0x16, }; /* Size of an MMU section */ diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 3e62d58542..2155fe8187 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -73,6 +73,8 @@ __weak void dram_bank_mmu_setup(int bank) i++) { #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) set_section_dcache(i, DCACHE_WRITETHROUGH); +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) + set_section_dcache(i, DCACHE_WRITEALLOC); #else set_section_dcache(i, DCACHE_WRITEBACK); #endif