MX53: Add support to ESG ima3 board
The ESG ima3-mx53 board is based on the Freescale i.MX53 SOC. It boots from NOR (128 MB) and supports Ethernet (FEC), SATA. Signed-off-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Stefano Babic
Albert ARIBAUD
parent
9f472e6540
commit
79656d27b3
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#
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# Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
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#
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# Based on ti/evm/Makefile
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := ima3-mx53.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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/*
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* (C) Copyright 2012, Stefano Babic <sbabic@denx.de>
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*
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* (C) Copyright 2010 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx5x_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux.h>
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#include <asm/errno.h>
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#include <netdev.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <asm/gpio.h>
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/* NOR flash configuration */
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#define IMA3_MX53_CS0GCR1 (CSEN | DSZ(2))
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#define IMA3_MX53_CS0GCR2 0
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#define IMA3_MX53_CS0RCR1 (RCSN(2) | OEN(1) | RWSC(15))
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#define IMA3_MX53_CS0RCR2 0
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#define IMA3_MX53_CS0WCR1 (WBED1 | WCSN(2) | WEN(1) | WWSC(15))
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#define IMA3_MX53_CS0WCR2 0
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DECLARE_GLOBAL_DATA_PTR;
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static void weim_nor_settings(void)
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{
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struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
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writel(IMA3_MX53_CS0GCR1, &weim_regs->cs0gcr1);
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writel(IMA3_MX53_CS0GCR2, &weim_regs->cs0gcr2);
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writel(IMA3_MX53_CS0RCR1, &weim_regs->cs0rcr1);
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writel(IMA3_MX53_CS0RCR2, &weim_regs->cs0rcr2);
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writel(IMA3_MX53_CS0WCR1, &weim_regs->cs0wcr1);
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writel(IMA3_MX53_CS0WCR2, &weim_regs->cs0wcr2);
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writel(0x0, &weim_regs->wcr);
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set_chipselect_size(CS0_128);
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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static void setup_iomux_uart(void)
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{
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/* UART4 RXD */
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mxc_request_iomux(MX53_PIN_CSI0_D13, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX53_PIN_CSI0_D13,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
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PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
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mxc_iomux_set_input(MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
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/* UART4 TXD */
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mxc_request_iomux(MX53_PIN_CSI0_D12, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX53_PIN_CSI0_D12,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
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PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
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}
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static void setup_iomux_fec(void)
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{
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/*FEC_MDIO*/
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mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU |
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PAD_CTL_ODE_OPENDRAIN_ENABLE);
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mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
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/*FEC_MDC*/
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mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
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/* FEC RXD3 */
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mxc_request_iomux(MX53_PIN_KEY_COL0, IOMUX_CONFIG_ALT6);
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mxc_iomux_set_pad(MX53_PIN_KEY_COL0, PAD_CTL_HYS_ENABLE |
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PAD_CTL_PKE_ENABLE);
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/* FEC RXD2 */
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mxc_request_iomux(MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT6);
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mxc_iomux_set_pad(MX53_PIN_KEY_COL2, PAD_CTL_HYS_ENABLE |
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PAD_CTL_PKE_ENABLE);
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/* FEC RXD1 */
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mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, PAD_CTL_HYS_ENABLE |
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PAD_CTL_PKE_ENABLE);
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/* FEC RXD0 */
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mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, PAD_CTL_HYS_ENABLE |
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PAD_CTL_PKE_ENABLE);
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/* FEC TXD3 */
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mxc_request_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT6);
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mxc_iomux_set_pad(MX53_PIN_GPIO_19, PAD_CTL_DRV_HIGH);
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/* FEC TXD2 */
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mxc_request_iomux(MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT6);
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mxc_iomux_set_pad(MX53_PIN_KEY_ROW2, PAD_CTL_DRV_HIGH);
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/* FEC TXD1 */
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mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
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/* FEC TXD0 */
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mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
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/* FEC TX_EN */
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mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
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/* FEC TX_CLK */
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mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, PAD_CTL_HYS_ENABLE |
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PAD_CTL_PKE_ENABLE);
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/* FEC RX_ER */
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mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, PAD_CTL_HYS_ENABLE |
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PAD_CTL_PKE_ENABLE);
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/* FEC RX_DV */
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mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, PAD_CTL_HYS_ENABLE |
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PAD_CTL_PKE_ENABLE);
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/* FEC CRS */
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mxc_request_iomux(MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT6);
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mxc_iomux_set_pad(MX53_PIN_KEY_COL3, PAD_CTL_HYS_ENABLE |
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PAD_CTL_PKE_ENABLE);
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/* FEC COL */
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mxc_request_iomux(MX53_PIN_KEY_ROW1, IOMUX_CONFIG_ALT6);
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mxc_iomux_set_pad(MX53_PIN_KEY_ROW1, PAD_CTL_HYS_ENABLE |
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PAD_CTL_PKE_ENABLE);
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mxc_iomux_set_input(MX53_FEC_FEC_COL_SELECT_INPUT, 0x0);
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/* FEC RX_CLK */
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mxc_request_iomux(MX53_PIN_KEY_COL1, IOMUX_CONFIG_ALT6);
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mxc_iomux_set_pad(MX53_PIN_KEY_COL1, PAD_CTL_HYS_ENABLE |
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PAD_CTL_PKE_ENABLE);
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mxc_iomux_set_input(MX53_FEC_FEC_RX_CLK_SELECT_INPUT, 0x0);
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}
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg esdhc_cfg = { MMC_SDHC1_BASE_ADDR, 1 };
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int board_mmc_getcd(struct mmc *mmc)
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{
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int ret;
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ret = !gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
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mxc_iomux_set_pad(MX53_PIN_GPIO_1,
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PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
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PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
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PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PKE_ENABLE);
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gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));
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mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
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mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
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PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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return fsl_esdhc_initialize(bis, &esdhc_cfg);
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}
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#endif
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static void setup_iomux_spi(void)
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{
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/* SCLK */
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mxc_request_iomux(MX53_PIN_CSI0_D8, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_input(MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT, 0x1);
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/* MOSI */
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mxc_request_iomux(MX53_PIN_CSI0_D9, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT, 0x1);
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/* MISO */
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mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT, 0x1);
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/* SSEL 0 */
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mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_GPIO);
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mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D11), 1);
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}
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int board_early_init_f(void)
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{
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/* configure I/O pads */
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setup_iomux_uart();
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setup_iomux_fec();
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weim_nor_settings();
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/* configure spi */
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setup_iomux_spi();
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return 0;
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}
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int board_init(void)
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{
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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mxc_set_sata_internal_clock();
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return 0;
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}
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#if defined(CONFIG_RESET_PHY_R)
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#include <miiphy.h>
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void reset_phy(void)
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{
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unsigned short reg;
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/* reset the phy */
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miiphy_reset("FEC", CONFIG_PHY_ADDR);
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/* set hard link to 100Mbit, full-duplex */
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miiphy_read("FEC", CONFIG_PHY_ADDR, MII_BMCR, ®);
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reg &= ~BMCR_ANENABLE;
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reg |= (BMCR_SPEED100 | BMCR_FULLDPLX);
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miiphy_write("FEC", CONFIG_PHY_ADDR, MII_BMCR, reg);
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miiphy_read("FEC", CONFIG_PHY_ADDR, 0x16, ®);
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reg |= (1 << 5);
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miiphy_write("FEC", CONFIG_PHY_ADDR, 0x16, reg);
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}
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#endif
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int checkboard(void)
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{
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puts("Board: IMA3_MX53\n");
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return 0;
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}
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@ -0,0 +1,108 @@
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#
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# (C) Copyright 2012
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# Stefano Babic DENX Software Engineering sbabic@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not write to the Free Software
|
||||
# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
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# MA 02110-1301 USA
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#
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# Refer docs/README.imxmage for more details about how-to configure
|
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# and create imximage boot image
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#
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# The syntax is taken as close as possible with the kwbimage
|
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||||
# image version
|
||||
|
||||
IMAGE_VERSION 2
|
||||
|
||||
# Boot Device : one of
|
||||
# spi, sd (the board has no nand neither onenand)
|
||||
|
||||
BOOT_FROM nor
|
||||
|
||||
# Device Configuration Data (DCD)
|
||||
#
|
||||
# Each entry must have the format:
|
||||
# Addr-type Address Value
|
||||
#
|
||||
# where:
|
||||
# Addr-type register length (1,2 or 4 bytes)
|
||||
# Address absolute address of the register
|
||||
# value value to be stored in the register
|
||||
|
||||
# IOMUX for RAM only
|
||||
DATA 4 0x53fa8554 0x300020
|
||||
DATA 4 0x53fa8560 0x300020
|
||||
DATA 4 0x53fa8594 0x300020
|
||||
DATA 4 0x53fa8584 0x300020
|
||||
DATA 4 0x53fa8558 0x300040
|
||||
DATA 4 0x53fa8568 0x300040
|
||||
DATA 4 0x53fa8590 0x300040
|
||||
DATA 4 0x53fa857c 0x300040
|
||||
DATA 4 0x53fa8564 0x300040
|
||||
DATA 4 0x53fa8580 0x300040
|
||||
DATA 4 0x53fa8570 0x300220
|
||||
DATA 4 0x53fa8578 0x300220
|
||||
DATA 4 0x53fa872c 0x300000
|
||||
DATA 4 0x53fa8728 0x300000
|
||||
DATA 4 0x53fa871c 0x300000
|
||||
DATA 4 0x53fa8718 0x300000
|
||||
DATA 4 0x53fa8574 0x300020
|
||||
DATA 4 0x53fa8588 0x300020
|
||||
DATA 4 0x53fa855c 0x0
|
||||
DATA 4 0x53fa858c 0x0
|
||||
DATA 4 0x53fa856c 0x300040
|
||||
DATA 4 0x53fa86f0 0x300000
|
||||
DATA 4 0x53fa8720 0x300000
|
||||
DATA 4 0x53fa86fc 0x0
|
||||
DATA 4 0x53fa86f4 0x0
|
||||
DATA 4 0x53fa8714 0x0
|
||||
DATA 4 0x53fa8724 0x4000000
|
||||
#
|
||||
# DDR RAM
|
||||
DATA 4 0x63fd9088 0x40404040
|
||||
DATA 4 0x63fd9090 0x40404040
|
||||
DATA 4 0x63fd907C 0x01420143
|
||||
DATA 4 0x63fd9080 0x01450146
|
||||
DATA 4 0x63fd9018 0x00111740
|
||||
DATA 4 0x63fd9000 0x84190000
|
||||
# esdcfgX
|
||||
DATA 4 0x63fd900C 0x9f5152e3
|
||||
DATA 4 0x63fd9010 0xb68e8a63
|
||||
DATA 4 0x63fd9014 0x01ff00db
|
||||
# Read/Write command delay
|
||||
DATA 4 0x63fd902c 0x000026d2
|
||||
# Out of reset delays
|
||||
DATA 4 0x63fd9030 0x00ff0e21
|
||||
# ESDCTL ODT timing control
|
||||
DATA 4 0x63fd9008 0x12273030
|
||||
# ESDCTL power down control
|
||||
DATA 4 0x63fd9004 0x0002002d
|
||||
# Set registers in DDR memory chips
|
||||
DATA 4 0x63fd901c 0x00008032
|
||||
DATA 4 0x63fd901c 0x00008033
|
||||
DATA 4 0x63fd901c 0x00028031
|
||||
DATA 4 0x63fd901c 0x052080b0
|
||||
DATA 4 0x63fd901c 0x04008040
|
||||
# ESDCTL refresh control
|
||||
DATA 4 0x63fd9020 0x00005800
|
||||
# PHY ZQ HW control
|
||||
DATA 4 0x63fd9040 0x05380003
|
||||
# PHY ODT control
|
||||
DATA 4 0x63fd9058 0x00022222
|
||||
# start DDR3
|
||||
DATA 4 0x63fd901c 0x00000000
|
||||
|
|
@ -192,6 +192,7 @@ mx53ard arm armv7 mx53ard freesca
|
|||
mx53evk arm armv7 mx53evk freescale mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg
|
||||
mx53loco arm armv7 mx53loco freescale mx5 mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg
|
||||
mx53smd arm armv7 mx53smd freescale mx5 mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg
|
||||
ima3-mx53 arm armv7 ima3-mx53 esg mx5 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg
|
||||
vision2 arm armv7 vision2 ttcontrol mx5 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
|
||||
mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg
|
||||
mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/mx6qsabrelite/imximage.cfg
|
||||
|
|
|
|||
|
|
@ -0,0 +1,269 @@
|
|||
/*
|
||||
* (C) Copyright 2012, Stefano Babic <sbabic@denx.de>
|
||||
*
|
||||
* Copyright (C) 2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the MX53-EVK Freescale board.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* SOC type must be included before imx-regs.h */
|
||||
#define CONFIG_MX53
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/mx5x_pins.h>
|
||||
|
||||
#define CONFIG_SYS_MX5_HCLK 24000000
|
||||
#define CONFIG_SYS_MX5_CLK32 32768
|
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
|
||||
#define CONFIG_OF_LIBFDT
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
|
||||
/* Enable GPIOs */
|
||||
#define CONFIG_MXC_GPIO
|
||||
|
||||
/* UART */
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR
|
||||
|
||||
/* MMC */
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define CONFIG_SYS_FSL_ESDHC_NUM 1
|
||||
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/* Ethernet on FEC */
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_DISCOVER_PHY
|
||||
|
||||
#define CONFIG_FEC_MXC
|
||||
#define IMX_FEC_BASE FEC_BASE_ADDR
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x01
|
||||
#define CONFIG_PHY_ADDR CONFIG_FEC_MXC_PHYADDR
|
||||
#define CONFIG_RESET_PHY_R
|
||||
#define CONFIG_FEC_MXC_NO_ANEG
|
||||
#define CONFIG_PRIME "FEC0"
|
||||
|
||||
/* SPI */
|
||||
#define CONFIG_HARD_SPI
|
||||
#define CONFIG_MXC_SPI
|
||||
#define CONFIG_DEFAULT_SPI_BUS 1
|
||||
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
|
||||
|
||||
/* SPI FLASH - not used for environment */
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_STMICRO
|
||||
#define CONFIG_SPI_FLASH_CS (IOMUX_TO_GPIO(MX53_PIN_CSI0_D11) \
|
||||
<< 8) | 0
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||
#define CONFIG_SF_DEFAULT_SPEED 25000000
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
/* Command definition */
|
||||
#include <config_cmd_default.h>
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_CMD_SPI
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_CMD_GPIO
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
|
||||
#define CONFIG_SYS_TEXT_BASE 0xf0001400 /* uboot in nor flash */
|
||||
|
||||
#define CONFIG_ARP_TIMEOUT 200UL
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_SYS_PROMPT "IMA3 MX53 U-Boot > "
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x70000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x10000
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
|
||||
/* Stack sizes */
|
||||
#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
|
||||
#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
|
||||
#define MTDIDS_DEFAULT "nor0=f0000000.flash"
|
||||
|
||||
/* FLASH and environment organization */
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0xF0000000
|
||||
#define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */
|
||||
#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */
|
||||
#define CONFIG_FLASH_CFI_MTD /* with MTD support */
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024
|
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
||||
|
||||
#define CONFIG_ENV_SIZE (8 * 1024)
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
|
||||
CONFIG_SYS_MONITOR_LEN)
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
|
||||
CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
|
||||
|
||||
/*
|
||||
* Default environment and default scripts
|
||||
* to update uboot and load kernel
|
||||
*/
|
||||
|
||||
#define HOSTNAME ima3-mx53
|
||||
#define xstr(s) str(s)
|
||||
#define str(s) #s
|
||||
|
||||
#define CONFIG_HOSTNAME ima3-mx53
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram0 rw\0" \
|
||||
"addip_sta=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
|
||||
"addip=if test -n ${ipdyn};then run addip_dyn;" \
|
||||
"else run addip_sta;fi\0" \
|
||||
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
|
||||
"addtty=setenv bootargs ${bootargs}" \
|
||||
" console=${console},${baudrate}\0" \
|
||||
"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
|
||||
"console=ttymxc3\0" \
|
||||
"loadaddr=70800000\0" \
|
||||
"kernel_addr_r=70800000\0" \
|
||||
"ramdisk_addr_r=71000000\0" \
|
||||
"hostname=" xstr(CONFIG_HOSTNAME) "\0" \
|
||||
"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
|
||||
"ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
|
||||
"mmcargs=setenv bootargs root=${mmcroot} " \
|
||||
"rootfstype=${mmcrootfstype}\0" \
|
||||
"mmcroot=/dev/mmcblk0p3 rw\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs addip addtty addmtd addmisc mmcload;" \
|
||||
"bootm\0" \
|
||||
"mmcload=fatload mmc ${mmcdev}:${mmcpart} " \
|
||||
"${loadaddr} ${uimage}\0" \
|
||||
"mmcrootfstype=ext3 rootwait\0" \
|
||||
"flash_self=run ramargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
|
||||
"run nfsargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr_r}\0" \
|
||||
"net_self_load=tftp ${ramdisk_addr_r} ${ramdisk_file};" \
|
||||
"tftp ${kernel_addr_r} ${bootfile}\0" \
|
||||
"net_self=if run net_self_load;then " \
|
||||
"run ramargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
|
||||
"else echo Images not loades;fi\0" \
|
||||
"satargs=setenv bootargs root=/dev/sda1\0" \
|
||||
"satafile=boot/uImage\0" \
|
||||
"ssdboot=echo Booting from ssd ...; " \
|
||||
"run satargs addip addtty addmtd addmisc;" \
|
||||
"sata init;ext2load sata 0:1 ${kernel_addr_r} " \
|
||||
"${satafile};bootm\0" \
|
||||
"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.imx\0" \
|
||||
"uimage=uImage\0" \
|
||||
"load=tftp ${loadaddr} ${u-boot}\0" \
|
||||
"uboot_addr=0xf0001000\0" \
|
||||
"update=protect off 0xf0000000 +60000;" \
|
||||
"erase ${uboot_addr} +60000;" \
|
||||
"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
|
||||
"upd=if run load;then echo Updating u-boot;if run update;" \
|
||||
"then echo U-Boot updated;" \
|
||||
"else echo Error updating u-boot !;" \
|
||||
"echo Board without bootloader !!;" \
|
||||
"fi;" \
|
||||
"else echo U-Boot not downloaded..exiting;fi\0" \
|
||||
"bootcmd=run net_nfs\0"
|
||||
|
||||
|
||||
#define CONFIG_CMD_SATA
|
||||
#ifdef CONFIG_CMD_SATA
|
||||
#define CONFIG_DWC_AHSATA
|
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 1
|
||||
#define CONFIG_DWC_AHSATA_PORT_ID 0
|
||||
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
|
||||
#define CONFIG_LBA48
|
||||
#define CONFIG_LIBATA
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue