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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

This commit is contained in:
Wolfgang Denk 2010-04-08 00:23:11 +02:00
parent 92abce8731 933419096e
commit 797131c125
33 changed files with 517 additions and 304 deletions
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1
board/freescale/common/Makefile
View File

@ -33,6 +33,7 @@ COBJS-${CONFIG_FSL_CADMUS} += cadmus.o
COBJS-${CONFIG_FSL_VIA} += cds_via.o
COBJS-${CONFIG_FSL_DIU_FB} += fsl_diu_fb.o fsl_logo_bmp.o
COBJS-${CONFIG_FSL_PIXIS} += pixis.o
COBJS-${CONFIG_FSL_NGPIXIS} += ngpixis.o
COBJS-${CONFIG_PQ_MDS_PIB} += pq-mds-pib.o
COBJS-${CONFIG_ID_EEPROM} += sys_eeprom.o
COBJS-${CONFIG_FSL_SGMII_RISER} += sgmii_riser.o

136
board/freescale/common/ngpixis.c Normal file
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@ -0,0 +1,136 @@
/**
* Copyright 2010 Freescale Semiconductor
* Author: Timur Tabi <timur@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This file provides support for the ngPIXIS, a board-specific FPGA used on
* some Freescale reference boards.
*
* A "switch" is black rectangular block on the motherboard. It contains
* eight "bits". The ngPIXIS has a set of memory-mapped registers (SWx) that
* shadow the actual physical switches. There is also another set of
* registers (ENx) that tell the ngPIXIS which bits of SWx should actually be
* used to override the values of the bits in the physical switches.
*
* The following macros need to be defined:
*
* PIXIS_BASE - The virtual address of the base of the PIXIS register map
*
* PIXIS_LBMAP_SWITCH - The switch number (i.e. the "x" in "SWx"). This value
* is used in the PIXIS_SW() macro to determine which offset in
* the PIXIS register map corresponds to the physical switch that controls
* the boot bank.
*
* PIXIS_LBMAP_MASK - A bit mask the defines which bits in SWx to use.
*
* PIXIS_LBMAP_SHIFT - The shift value that corresponds to PIXIS_LBMAP_MASK.
*
* PIXIS_LBMAP_ALTBANK - The value to program into SWx to tell the ngPIXIS to
* boot from the alternate bank.
*/
#include <common.h>
#include <command.h>
#include <watchdog.h>
#include <asm/cache.h>
#include <asm/io.h>
#include "ngpixis.h"
/*
* Reset the board. This ignores the ENx registers.
*/
void pixis_reset(void)
{
out_8(&pixis->rst, 0);
while (1);
}
/*
* Reset the board. Like pixis_reset(), but it honors the ENx registers.
*/
void pixis_bank_reset(void)
{
out_8(&pixis->vctl, 0);
out_8(&pixis->vctl, 1);
while (1);
}
/**
* Set the boot bank to the power-on default bank
*/
void clear_altbank(void)
{
/* Tell the ngPIXIS to use this the bits in the physical switch for the
* boot bank value, instead of the SWx register. We need to be careful
* only to set the bits in SWx that correspond to the boot bank.
*/
clrbits_8(&PIXIS_EN(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK);
}
/**
* Set the boot bank to the alternate bank
*/
void set_altbank(void)
{
/* Program the alternate bank number into the SWx register.
*/
clrsetbits_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK,
PIXIS_LBMAP_ALTBANK);
/* Tell the ngPIXIS to use this the bits in the SWx register for the
* boot bank value, instead of the physical switch. We need to be
* careful only to set the bits in SWx that correspond to the boot bank.
*/
setbits_8(&PIXIS_EN(PIXIS_LBMAP_SWITCH), PIXIS_LBMAP_MASK);
}
int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
unsigned int i;
char *p_altbank = NULL;
char *unknown_param = NULL;
/* No args is a simple reset request.
*/
if (argc <= 1)
pixis_reset();
for (i = 1; i < argc; i++) {
if (strcmp(argv[i], "altbank") == 0) {
p_altbank = argv[i];
continue;
}
unknown_param = argv[i];
}
if (unknown_param) {
printf("Invalid option: %s\n", unknown_param);
return 1;
}
if (p_altbank)
set_altbank();
else
clear_altbank();
pixis_bank_reset();
/* Shouldn't be reached. */
return 0;
}
U_BOOT_CMD(
pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
"Reset the board using the FPGA sequencer",
"- hard reset to default bank\n"
"pixis_reset altbank - reset to alternate bank\n"
);

57
board/freescale/common/ngpixis.h Normal file
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@ -0,0 +1,57 @@
/**
* Copyright 2010 Freescale Semiconductor
* Author: Timur Tabi <timur@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This file provides support for the ngPIXIS, a board-specific FPGA used on
* some Freescale reference boards.
*/
/* ngPIXIS register set. Hopefully, this won't change too much over time.
* Feel free to add board-specific #ifdefs where necessary.
*/
typedef struct ngpixis {
u8 id;
u8 arch;
u8 scver;
u8 csr;
u8 rst;
u8 res1;
u8 aux;
u8 spd;
u8 brdcfg0;
u8 dma;
u8 addr;
u8 res2[2];
u8 data;
u8 led;
u8 res3;
u8 vctl;
u8 vstat;
u8 vcfgen0;
u8 res4;
u8 ocmcsr;
u8 ocmmsg;
u8 gmdbg;
u8 res5[2];
u8 sclk[3];
u8 dclk[3];
u8 watch;
struct {
u8 sw;
u8 en;
} s[8];
} ngpixis_t __attribute__ ((aligned(1)));
/* Pointer to the PIXIS register set */
#define pixis ((ngpixis_t *)PIXIS_BASE)
/* The PIXIS SW register that corresponds to board switch X, where x >= 1 */
#define PIXIS_SW(x) (pixis->s[(x) - 1].sw)
/* The PIXIS EN register that corresponds to board switch X, where x >= 1 */
#define PIXIS_EN(x) (pixis->s[(x) - 1].en)

254
board/freescale/common/pixis.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2006 Freescale Semiconductor
* Copyright 2006,2010 Freescale Semiconductor
* Jeff Brown
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*
@ -24,33 +24,26 @@
#include <common.h>
#include <command.h>
#include <watchdog.h>
#include <asm/cache.h>
#include <asm/io.h>
#include "pixis.h"
static ulong strfractoint(uchar *strptr);
#define pixis_base (u8 *)PIXIS_BASE
/*
* Simple board reset.
*/
void pixis_reset(void)
{
u8 *pixis_base = (u8 *)PIXIS_BASE;
out_8(pixis_base + PIXIS_RST, 0);
}
while (1);
}
/*
* Per table 27, page 58 of MPC8641HPCN spec.
*/
int set_px_sysclk(ulong sysclk)
static int set_px_sysclk(unsigned long sysclk)
{
u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
u8 *pixis_base = (u8 *)PIXIS_BASE;
switch (sysclk) {
case 33:
@ -117,13 +110,13 @@ int set_px_sysclk(ulong sysclk)
return 1;
}
int set_px_mpxpll(ulong mpxpll)
/* Set the CFG_SYSPLL bits
*
* This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if
* read_from_px_regs() is called.
*/
static int set_px_mpxpll(unsigned long mpxpll)
{
u8 tmp;
u8 val;
u8 *pixis_base = (u8 *)PIXIS_BASE;
switch (mpxpll) {
case 2:
case 4:
@ -133,28 +126,19 @@ int set_px_mpxpll(ulong mpxpll)
case 12:
case 14:
case 16:
val = (u8) mpxpll;
break;
default:
printf("Unsupported MPXPLL ratio.\n");
return 0;
clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll);
return 1;
}
tmp = in_8(pixis_base + PIXIS_VSPEED1);
tmp = (tmp & 0xF0) | (val & 0x0F);
out_8(pixis_base + PIXIS_VSPEED1, tmp);
return 1;
printf("Unsupported MPXPLL ratio.\n");
return 0;
}
int set_px_corepll(ulong corepll)
static int set_px_corepll(unsigned long corepll)
{
u8 tmp;
u8 val;
u8 *pixis_base = (u8 *)PIXIS_BASE;
switch ((int)corepll) {
switch (corepll) {
case 20:
val = 0x08;
break;
@ -178,113 +162,132 @@ int set_px_corepll(ulong corepll)
return 0;
}
tmp = in_8(pixis_base + PIXIS_VSPEED0);
tmp = (tmp & 0xE0) | (val & 0x1F);
out_8(pixis_base + PIXIS_VSPEED0, tmp);
clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val);
return 1;
}
#ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
#define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE 0x1C
#endif
void read_from_px_regs(int set)
/* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
*
* The PIXIS can be programmed to look at either the on-board dip switches
* or various other PIXIS registers to determine the values for COREPLL,
* MPXPLL, and SYSCLK.
*
* CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
* register that tells the pixis to use the various PIXIS register.
*/
static void read_from_px_regs(int set)
{
u8 *pixis_base = (u8 *)PIXIS_BASE;
u8 mask = 0x1C; /* COREPLL, MPXPLL, SYSCLK controlled by PIXIS */
u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
if (set)
tmp = tmp | mask;
tmp = tmp | CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
else
tmp = tmp & ~mask;
tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
out_8(pixis_base + PIXIS_VCFGEN0, tmp);
}
/* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
* register that tells the pixis to use the PX_VBOOT[LBMAP] register.
*/
#ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE
#define CONFIG_SYS_PIXIS_VBOOT_ENABLE 0x04
#endif
void read_from_px_regs_altbank(int set)
/* Configure the source of the boot location
*
* The PIXIS can be programmed to look at either the on-board dip switches
* or the PX_VBOOT[LBMAP] register to determine where we should boot.
*
* If we want to boot from the alternate boot bank, we need to tell the PIXIS
* to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead.
*/
static void read_from_px_regs_altbank(int set)
{
u8 *pixis_base = (u8 *)PIXIS_BASE;
u8 mask = 0x04; /* FLASHBANK and FLASHMAP controlled by PIXIS */
u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
if (set)
tmp = tmp | mask;
tmp = tmp | CONFIG_SYS_PIXIS_VBOOT_ENABLE;
else
tmp = tmp & ~mask;
tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE;
out_8(pixis_base + PIXIS_VCFGEN1, tmp);
}
/* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
* tells the PIXIS what the alternate flash bank is.
*
* Note that it's not really a mask. It contains the actual LBMAP bits that
* must be set to select the alternate bank. This code assumes that the
* primary bank has these bits set to 0, and the alternate bank has these
* bits set to 1.
*/
#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
#define CONFIG_SYS_PIXIS_VBOOT_MASK (0x40)
#endif
void clear_altbank(void)
/* Tell the PIXIS to boot from the default flash bank
*
* Program the default flash bank into the VBOOT register. This register is
* used only if PX_VCFGEN1[FLASH]=1.
*/
static void clear_altbank(void)
{
u8 tmp;
u8 *pixis_base = (u8 *)PIXIS_BASE;
tmp = in_8(pixis_base + PIXIS_VBOOT);
tmp &= ~CONFIG_SYS_PIXIS_VBOOT_MASK;
out_8(pixis_base + PIXIS_VBOOT, tmp);
clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
}
void set_altbank(void)
/* Tell the PIXIS to boot from the alternate flash bank
*
* Program the alternate flash bank into the VBOOT register. This register is
* used only if PX_VCFGEN1[FLASH]=1.
*/
static void set_altbank(void)
{
u8 tmp;
u8 *pixis_base = (u8 *)PIXIS_BASE;
tmp = in_8(pixis_base + PIXIS_VBOOT);
tmp |= CONFIG_SYS_PIXIS_VBOOT_MASK;
out_8(pixis_base + PIXIS_VBOOT, tmp);
setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
}
void set_px_go(void)
/* Reset the board with watchdog disabled.
*
* This respects the altbank setting.
*/
static void set_px_go(void)
{
u8 tmp;
u8 *pixis_base = (u8 *)PIXIS_BASE;
/* Disable the VELA sequencer and watchdog */
clrbits_8(pixis_base + PIXIS_VCTL, 9);
tmp = in_8(pixis_base + PIXIS_VCTL);
tmp = tmp & 0x1E; /* clear GO bit */
out_8(pixis_base + PIXIS_VCTL, tmp);
/* Reboot by starting the VELA sequencer */
setbits_8(pixis_base + PIXIS_VCTL, 0x1);
tmp = in_8(pixis_base + PIXIS_VCTL);
tmp = tmp | 0x01; /* set GO bit - start reset sequencer */
out_8(pixis_base + PIXIS_VCTL, tmp);
while (1);
}
void set_px_go_with_watchdog(void)
/* Reset the board with watchdog enabled.
*
* This respects the altbank setting.
*/
static void set_px_go_with_watchdog(void)
{
u8 tmp;
u8 *pixis_base = (u8 *)PIXIS_BASE;
/* Disable the VELA sequencer */
clrbits_8(pixis_base + PIXIS_VCTL, 1);
tmp = in_8(pixis_base + PIXIS_VCTL);
tmp = tmp & 0x1E;
out_8(pixis_base + PIXIS_VCTL, tmp);
/* Enable the watchdog and reboot by starting the VELA sequencer */
setbits_8(pixis_base + PIXIS_VCTL, 0x9);
tmp = in_8(pixis_base + PIXIS_VCTL);
tmp = tmp | 0x09;
out_8(pixis_base + PIXIS_VCTL, tmp);
while (1);
}
int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp,
int flag, int argc, char *argv[])
/* Disable the watchdog
*
*/
static int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
char *argv[])
{
u8 tmp;
u8 *pixis_base = (u8 *)PIXIS_BASE;
tmp = in_8(pixis_base + PIXIS_VCTL);
tmp = tmp & 0x1E;
out_8(pixis_base + PIXIS_VCTL, tmp);
/* setting VCTL[WDEN] to 0 to disable watch dog */
tmp = in_8(pixis_base + PIXIS_VCTL);
tmp &= ~0x08;
out_8(pixis_base + PIXIS_VCTL, tmp);
/* Disable the VELA sequencer and the watchdog */
clrbits_8(pixis_base + PIXIS_VCTL, 9);
return 0;
}
@ -296,16 +299,17 @@ U_BOOT_CMD(
);
#ifdef CONFIG_PIXIS_SGMII_CMD
int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/* Enable or disable SGMII mode for a TSEC
*/
static int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int which_tsec = -1;
u8 *pixis_base = (u8 *)PIXIS_BASE;
uchar mask;
uchar switch_mask;
unsigned char mask;
unsigned char switch_mask;
if (argc > 2)
if (strcmp(argv[1], "all") != 0)
which_tsec = simple_strtoul(argv[1], NULL, 0);
if ((argc > 2) && (strcmp(argv[1], "all") != 0))
which_tsec = simple_strtoul(argv[1], NULL, 0);
switch (which_tsec) {
#ifdef CONFIG_TSEC1
@ -363,6 +367,7 @@ U_BOOT_CMD(
" off - disables SGMII\n"
" switch - use switch settings"
);
#endif
/*
@ -371,14 +376,13 @@ U_BOOT_CMD(
* FPGA register values.
* input: strptr i.e. argv[2]
*/
static ulong strfractoint(uchar *strptr)
static unsigned long strfractoint(char *strptr)
{
int i, j, retval;
int i, j;
int mulconst;
int intarr_len = 0, decarr_len = 0, no_dec = 0;
ulong intval = 0, decval = 0;
uchar intarr[3], decarr[3];
int intarr_len, no_dec = 0;
unsigned long intval = 0, decval = 0;
char intarr[3], decarr[3];
/* Assign the integer part to intarr[]
* If there is no decimal point i.e.
@ -412,26 +416,21 @@ static ulong strfractoint(uchar *strptr)
j++;
}
decarr_len = j;
decarr[j] = '\0';
mulconst = 1;
for (i = 0; i < decarr_len; i++)
for (i = 0; i < j; i++)
mulconst *= 10;
decval = simple_strtoul((char *)decarr, NULL, 10);
decval = simple_strtoul(decarr, NULL, 10);
}
intval = simple_strtoul((char *)intarr, NULL, 10);
intval = simple_strtoul(intarr, NULL, 10);
intval = intval * mulconst;
retval = intval + decval;
return retval;
return intval + decval;
}
int
pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
static int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
unsigned int i;
char *p_cf = NULL;
@ -440,7 +439,7 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
char *p_cf_mpxpll = NULL;
char *p_altbank = NULL;
char *p_wd = NULL;
unsigned int unknown_param = 0;
int unknown_param = 0;
/*
* No args is a simple reset request.
@ -493,9 +492,9 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
*/
read_from_px_regs(0);
if (p_altbank) {
if (p_altbank)
read_from_px_regs_altbank(0);
}
clear_altbank();
/*
@ -507,7 +506,7 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
unsigned long mpxpll;
sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
corepll = strfractoint((uchar *) p_cf_corepll);
corepll = strfractoint(p_cf_corepll);
mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);
if (!(set_px_sysclk(sysclk)
@ -536,11 +535,10 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/*
* Reset with watchdog specified.
*/
if (p_wd) {
if (p_wd)
set_px_go_with_watchdog();
} else {
else
set_px_go();
}
/*
* Shouldn't be reached.

31
board/freescale/common/pixis.h
View File

@ -1,31 +0,0 @@
/*
* Copyright 2006 Freescale Semiconductor
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
extern void pixis_reset(void);
extern int set_px_sysclk(ulong sysclk);
extern int set_px_mpxpll(ulong mpxpll);
extern int set_px_corepll(ulong corepll);
extern void read_from_px_regs(int set);
extern void read_from_px_regs_altbank(int set);
extern void set_altbank(void);
extern void set_px_go(void);
extern void set_px_go_with_watchdog(void);

1
board/freescale/mpc8536ds/mpc8536ds.c
View File

@ -39,7 +39,6 @@
#include <netdev.h>
#include <sata.h>
#include "../common/pixis.h"
#include "../common/sgmii_riser.h"
phys_size_t fixed_sdram(void);

1
board/freescale/mpc8544ds/mpc8544ds.c
View File

@ -35,7 +35,6 @@
#include <tsec.h>
#include <netdev.h>
#include "../common/pixis.h"
#include "../common/sgmii_riser.h"
int checkboard (void)

1
board/freescale/mpc8572ds/mpc8572ds.c
View File

@ -36,7 +36,6 @@
#include <tsec.h>
#include <netdev.h>
#include "../common/pixis.h"
#include "../common/sgmii_riser.h"
long int fixed_sdram(void);

2
board/freescale/mpc8610hpcd/mpc8610hpcd.c
View File

@ -34,8 +34,6 @@
#include <spd_sdram.h>
#include <netdev.h>
#include "../common/pixis.h"
void sdram_init(void);
phys_size_t fixed_sdram(void);
void mpc8610hpcd_diu_init(void);

1
board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
View File

@ -29,7 +29,6 @@
#ifdef CONFIG_FSL_DIU_FB
#include "../common/pixis.h"
#include "../common/fsl_diu_fb.h"
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)

2
board/freescale/mpc8641hpcn/mpc8641hpcn.c
View File

@ -31,8 +31,6 @@
#include <fdt_support.h>
#include <netdev.h>
#include "../common/pixis.h"
phys_size_t fixed_sdram(void);
int board_early_init_f(void)

56
board/freescale/p2020ds/p2020ds.c
View File

@ -38,7 +38,7 @@
#include <asm/mp.h>
#include <netdev.h>
#include "../common/pixis.h"
#include "../common/ngpixis.h"
#include "../common/sgmii_riser.h"
DECLARE_GLOBAL_DATA_PTR;
@ -47,30 +47,24 @@ phys_size_t fixed_sdram(void);
int checkboard(void)
{
u8 sw7;
u8 *pixis_base = (u8 *)PIXIS_BASE;
u8 sw;
puts("Board: P2020DS ");
#ifdef CONFIG_PHYS_64BIT
puts("(36-bit addrmap) ");
#endif
printf("Sys ID: 0x%02x, "
"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
in_8(pixis_base + PIXIS_PVER));
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
sw7 = in_8(pixis_base + PIXIS_SW(7));
switch ((sw7 & PIXIS_SW7_LBMAP) >> 6) {
case 0:
case 1:
printf ("vBank: %d\n", ((sw7 & PIXIS_SW7_VBANK) >> 4));
break;
case 2:
case 3:
puts ("Promjet\n");
break;
}
sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
if (sw < 0x8)
/* The lower two bits are the actual vbank number */
printf("vBank: %d\n", sw & 3);
else
puts("Promjet\n");
return 0;
}
@ -371,30 +365,22 @@ unsigned long get_board_ddr_clk(ulong dummy)
return gd->mem_clk;
}
unsigned long
calculate_board_sys_clk(ulong dummy)
unsigned long calculate_board_sys_clk(ulong dummy)
{
ulong val;
u8 *pixis_base = (u8 *)PIXIS_BASE;
val = ics307_clk_freq(
in_8(pixis_base + PIXIS_VSYSCLK0),
in_8(pixis_base + PIXIS_VSYSCLK1),
in_8(pixis_base + PIXIS_VSYSCLK2));
val = ics307_clk_freq(in_8(&pixis->sclk[0]), in_8(&pixis->sclk[1]),
in_8(&pixis->sclk[2]));
debug("sysclk val = %lu\n", val);
return val;
}
unsigned long
calculate_board_ddr_clk(ulong dummy)
unsigned long calculate_board_ddr_clk(ulong dummy)
{
ulong val;
u8 *pixis_base = (u8 *)PIXIS_BASE;
val = ics307_clk_freq(
in_8(pixis_base + PIXIS_VDDRCLK0),
in_8(pixis_base + PIXIS_VDDRCLK1),
in_8(pixis_base + PIXIS_VDDRCLK2));
val = ics307_clk_freq(in_8(&pixis->dclk[0]), in_8(&pixis->dclk[1]),
in_8(&pixis->dclk[2]));
debug("ddrclk val = %lu\n", val);
return val;
}
@ -403,9 +389,8 @@ unsigned long get_board_sys_clk(ulong dummy)
{
u8 i;
ulong val = 0;
u8 *pixis_base = (u8 *)PIXIS_BASE;
i = in_8(pixis_base + PIXIS_SPD);
i = in_8(&pixis->spd);
i &= 0x07;
switch (i) {
@ -442,9 +427,8 @@ unsigned long get_board_ddr_clk(ulong dummy)
{
u8 i;
ulong val = 0;
u8 *pixis_base = (u8 *)PIXIS_BASE;
i = in_8(pixis_base + PIXIS_SPD);
i = in_8(&pixis->spd);
i &= 0x38;
i >>= 3;

13
common/fdt_support.c
View File

@ -976,3 +976,16 @@ void fdt_fixup_mtdparts(void *blob, void *node_info, int node_info_size)
}
}
#endif
void fdt_del_node_and_alias(void *blob, const char *alias)
{
int off = fdt_path_offset(blob, alias);
if (off < 0)
return;
fdt_del_node(blob, off);
off = fdt_path_offset(blob, "/aliases");
fdt_delprop(blob, off, alias);
}

1
cpu/mpc512x/diu.c
View File

@ -27,7 +27,6 @@
#include <command.h>
#include <asm/io.h>
#include "../../board/freescale/common/pixis.h"
#include "../../board/freescale/common/fsl_diu_fb.h"
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)

4
cpu/mpc85xx/Makefile
View File

@ -50,7 +50,11 @@ COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
COBJS-$(CONFIG_MPC8569) += ddr-gen3.o
COBJS-$(CONFIG_P1011) += ddr-gen3.o
COBJS-$(CONFIG_P1012) += ddr-gen3.o
COBJS-$(CONFIG_P1013) += ddr-gen3.o
COBJS-$(CONFIG_P1020) += ddr-gen3.o
COBJS-$(CONFIG_P1021) += ddr-gen3.o
COBJS-$(CONFIG_P1022) += ddr-gen3.o
COBJS-$(CONFIG_P2010) += ddr-gen3.o
COBJS-$(CONFIG_P2020) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o

12
cpu/mpc85xx/release.S
View File

@ -1,5 +1,5 @@
/*
* Copyright 2008-2009 Freescale Semiconductor, Inc.
* Copyright 2008-2010 Freescale Semiconductor, Inc.
* Kumar Gala <kumar.gala@freescale.com>
*
* See file CREDITS for list of people who contributed to this
@ -57,11 +57,19 @@ __secondary_start_page:
#ifndef CONFIG_E500MC
li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mfspr r0,PVR
andi. r0,r0,0xff
cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */
blt 1f
/* Set MBDD bit also */
ori r3, r3, HID1_MBDD@l
1:
mtspr SPRN_HID1,r3
#endif
/* Enable branch prediction */
li r3,0x201
lis r3,BUCSR_ENABLE@h
ori r3,r3,BUCSR_ENABLE@l
mtspr SPRN_BUCSR,r3
/* Ensure TB is 0 */

14
cpu/mpc85xx/start.S
View File

@ -1,5 +1,5 @@
/*
* Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
* Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
* Copyright (C) 2003 Motorola,Inc.
*
* See file CREDITS for list of people who contributed to this
@ -208,13 +208,21 @@ _start_e500:
#ifndef CONFIG_E500MC
li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mfspr r3,PVR
andi. r3,r3, 0xff
cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
blt 1f
/* Set MBDD bit also */
ori r0, r0, HID1_MBDD@l
1:
mtspr HID1,r0
#endif
/* Enable Branch Prediction */
#if defined(CONFIG_BTB)
li r0,0x201 /* BBFI = 1, BPEN = 1 */
mtspr BUCSR,r0
lis r0,BUCSR_ENABLE@h
ori r0,r0,BUCSR_ENABLE@l
mtspr SPRN_BUCSR,r0
#endif
#if defined(CONFIG_SYS_INIT_DBCR)

10
cpu/mpc8xxx/cpu.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2009 Freescale Semiconductor, Inc.
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* This file is derived from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c.
* Basically this file contains cpu specific common code for 85xx/86xx
@ -66,8 +66,16 @@ struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(8572, 8572_E, 2),
CPU_TYPE_ENTRY(P1011, P1011, 1),
CPU_TYPE_ENTRY(P1011, P1011_E, 1),
CPU_TYPE_ENTRY(P1012, P1012, 1),
CPU_TYPE_ENTRY(P1012, P1012_E, 1),
CPU_TYPE_ENTRY(P1013, P1013, 1),
CPU_TYPE_ENTRY(P1013, P1013_E, 1),
CPU_TYPE_ENTRY(P1020, P1020, 2),
CPU_TYPE_ENTRY(P1020, P1020_E, 2),
CPU_TYPE_ENTRY(P1021, P1021, 2),
CPU_TYPE_ENTRY(P1021, P1021_E, 2),
CPU_TYPE_ENTRY(P1022, P1022, 2),
CPU_TYPE_ENTRY(P1022, P1022_E, 2),
CPU_TYPE_ENTRY(P2010, P2010, 1),
CPU_TYPE_ENTRY(P2010, P2010_E, 1),
CPU_TYPE_ENTRY(P2020, P2020, 2),

26
cpu/mpc8xxx/ddr/ctrl_regs.c
View File

@ -1,9 +1,10 @@
/*
* Copyright 2008-2009 Freescale Semiconductor, Inc.
* Copyright 2008-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*/
/*
@ -934,7 +935,8 @@ static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
}
/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts)
{
unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
@ -943,9 +945,15 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
#if defined(CONFIG_FSL_DDR3)
/* We need set BL/2 + 4 for BC4 or OTF */
rrt = 4; /* BL/2 + 4 clocks */
wwt = 4; /* BL/2 + 4 clocks */
if (popts->burst_length == DDR_BL8) {
/* We set BL/2 for fixed BL8 */
rrt = 0; /* BL/2 clocks */
wwt = 0; /* BL/2 clocks */
} else {
/* We need to set BL/2 + 2 to BC4 and OTF */
rrt = 2; /* BL/2 + 2 clocks */
wwt = 2; /* BL/2 + 2 clocks */
}
dll_lock = 1; /* tDLLK = 512 clocks from spec */
#endif
ddr->timing_cfg_4 = (0
@ -1343,7 +1351,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
set_ddr_sdram_clk_cntl(ddr, popts);
set_ddr_init_addr(ddr);
set_ddr_init_ext_addr(ddr);
set_timing_cfg_4(ddr);
set_timing_cfg_4(ddr, popts);
set_timing_cfg_5(ddr);
set_ddr_zq_cntl(ddr, zq_en);

14
cpu/mpc8xxx/ddr/options.c
View File

@ -1,9 +1,10 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
* Copyright 2008, 2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*/
#include <common.h>
@ -109,8 +110,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
/* Choose burst length. */
#if defined(CONFIG_FSL_DDR3)
#if defined(CONFIG_E500MC)
popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */
popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
#else
popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */
popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
#endif
#else
popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
#endif

30
cpu/mpc8xxx/pci_cfg.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2009 Freescale Semiconductor, Inc.
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -25,7 +25,7 @@
#include <pci.h>
struct pci_info {
u16 cfg;
u32 cfg;
};
/* The cfg field is a bit mask in which each bit represents the value of
@ -153,7 +153,8 @@ static struct pci_info pci_config_info[] =
(1 << 7) | (1 << 0xe) | (1 << 0xf),
},
};
#elif defined(CONFIG_P1011) || defined(CONFIG_P1020)
#elif defined(CONFIG_P1011) || defined(CONFIG_P1020) || \
defined(CONFIG_P1012) || defined(CONFIG_P1021)
static struct pci_info pci_config_info[] =
{
[LAW_TRGT_IF_PCIE_1] = {
@ -163,6 +164,29 @@ static struct pci_info pci_config_info[] =
.cfg = (1 << 0xe),
},
};
#elif defined(CONFIG_P1013) || defined(CONFIG_P1022)
static struct pci_info pci_config_info[] =
{
[LAW_TRGT_IF_PCIE_1] = {
.cfg = (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xa) |
(1 << 0xb) | (1 << 0xd) | (1 << 0xe) |
(1 << 0xf) | (1 << 0x15) | (1 << 0x16) |
(1 << 0x17) | (1 << 0x18) | (1 << 0x19) |
(1 << 0x1a) | (1 << 0x1b) | (1 << 0x1c) |
(1 << 0x1d) | (1 << 0x1e) | (1 << 0x1f),
},
[LAW_TRGT_IF_PCIE_2] = {
.cfg = (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) |
(1 << 9) | (1 << 0xa) | (1 << 0xb) | (1 << 0xd) |
(1 << 0x15) | (1 << 0x16) | (1 << 0x17) |
(1 << 0x18) | (1 << 0x1c),
},
[LAW_TRGT_IF_PCIE_3] = {
.cfg = (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xd) |
(1 << 0x15) | (1 << 0x16) | (1 << 0x17) | (1 << 0x18) |
(1 << 0x19) | (1 << 0x1a) | (1 << 0x1b),
},
};
#elif defined(CONFIG_P2010) || defined(CONFIG_P2020)
static struct pci_info pci_config_info[] =
{

4
drivers/misc/fsl_law.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2008-2009 Freescale Semiconductor, Inc.
* Copyright 2008-2010 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -39,6 +39,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define FSL_HW_NUM_LAWS 10
#elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \
defined(CONFIG_P1011) || defined(CONFIG_P1020) || \
defined(CONFIG_P1012) || defined(CONFIG_P1021) || \
defined(CONFIG_P1013) || defined(CONFIG_P1022) || \
defined(CONFIG_P2010) || defined(CONFIG_P2020)
#define FSL_HW_NUM_LAWS 12
#elif defined(CONFIG_PPC_P4080)

37
drivers/mmc/fsl_esdhc.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2007, Freescale Semiconductor, Inc
* Copyright 2007,2010 Freescale Semiconductor, Inc
* Andy Fleming
*
* Based vaguely on the pxa mmc code:
@ -110,8 +110,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
if (wml_value > 0x10)
wml_value = 0x10;
wml_value = 0x100000 | wml_value;
esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
esdhc_write32(&regs->dsaddr, (u32)data->dest);
} else {
if (wml_value > 0x80)
@ -120,12 +119,12 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
return TIMEOUT;
}
wml_value = wml_value << 16 | 0x10;
esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
wml_value << 16);
esdhc_write32(&regs->dsaddr, (u32)data->src);
}
esdhc_write32(&regs->wml, wml_value);
esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
/* Calculate the timeout period for data transactions */
@ -265,18 +264,13 @@ void set_sysctl(struct mmc *mmc, uint clock)
clk = (pre_div << 8) | (div << 4);
/* On imx the clock must be stopped before changing frequency */
if (cfg->clk_enable)
esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
udelay(10000);
clk = SYSCTL_PEREN;
/* On imx systems the clock must be explicitely enabled */
if (cfg->clk_enable)
clk |= SYSCTL_CKEN;
clk = SYSCTL_PEREN | SYSCTL_CKEN;
esdhc_setbits32(&regs->sysctl, clk);
}
@ -349,6 +343,20 @@ static int esdhc_init(struct mmc *mmc)
return ret;
}
static void esdhc_reset(struct fsl_esdhc *regs)
{
unsigned long timeout = 100; /* wait max 100 ms */
/* reset the controller */
esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
/* hardware clears the bit when it is done */
while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
udelay(1000);
if (!timeout)
printf("MMC/SD: Reset never completed.\n");
}
int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
{
struct fsl_esdhc *regs;
@ -363,6 +371,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
sprintf(mmc->name, "FSL_ESDHC");
regs = (struct fsl_esdhc *)cfg->esdhc_base;
/* First reset the eSDHC controller */
esdhc_reset(regs);
mmc->priv = cfg;
mmc->send_cmd = esdhc_send_cmd;
mmc->set_ios = esdhc_set_ios;

18
drivers/pci/fsl_pci_init.c
View File

@ -1,9 +1,10 @@
/*
* Copyright 2007-2009 Freescale Semiconductor, Inc.
* Copyright 2007-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -513,10 +514,15 @@ void ft_fsl_pci_setup(void *blob, const char *pci_alias,
struct pci_controller *hose)
{
int off = fdt_path_offset(blob, pci_alias);
u32 bus_range[2];
if (off >= 0) {
u32 bus_range[2];
if (off < 0)
return;
/* We assume a cfg_addr not being set means we didn't setup the controller */
if ((hose == NULL) || (hose->cfg_addr == NULL)) {
fdt_del_node_and_alias(blob, pci_alias);
} else {
bus_range[0] = 0;
bus_range[1] = hose->last_busno - hose->first_busno;
fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);

3
include/asm-ppc/config.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2009 Freescale Semiconductor, Inc.
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -41,6 +41,7 @@
#endif
#if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \
defined(CONFIG_P1021) || defined(CONFIG_P1022) || \
defined(CONFIG_P2020) || defined(CONFIG_MPC8641)
#define CONFIG_MAX_CPUS 2
#elif defined(CONFIG_PPC_P4080)

12
include/asm-ppc/processor.h
View File

@ -265,6 +265,7 @@
#define HID1_RFXE (1<<17) /* Read Fault Exception Enable */
#define HID1_ASTME (1<<13) /* Address bus streaming mode */
#define HID1_ABE (1<<12) /* Address broadcast enable */
#define HID1_MBDD (1<<6) /* optimized sync instruction */
#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
#ifndef CONFIG_BOOKE
#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
@ -533,6 +534,9 @@
#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */
#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */
#define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */
#define BUCSR_BBFI 0x00000200 /* Branch buffer flash invalidate */
#define BUCSR_BPEN 0x00000001 /* Branch prediction enable */
#define BUCSR_ENABLE (BUCSR_BBFI|BUCSR_BPEN)
#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
#define SPRN_PID1 0x279 /* Process ID Register 1 */
@ -1032,8 +1036,16 @@
#define SVR_8572_E 0x80E800
#define SVR_P1011 0x80E500
#define SVR_P1011_E 0x80ED00
#define SVR_P1012 0x80E501
#define SVR_P1012_E 0x80ED01
#define SVR_P1013 0x80E700
#define SVR_P1013_E 0x80EF00
#define SVR_P1020 0x80E400
#define SVR_P1020_E 0x80EC00
#define SVR_P1021 0x80E401
#define SVR_P1021_E 0x80EC01
#define SVR_P1022 0x80E600
#define SVR_P1022_E 0x80EE00
#define SVR_P2010 0x80E300
#define SVR_P2010_E 0x80EB00
#define SVR_P2020 0x80E200

3
include/configs/MPC8536DS.h
View File

@ -413,6 +413,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#ifdef CONFIG_NAND_SPL
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

3
include/configs/MPC8569MDS.h
View File

@ -284,6 +284,9 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#ifdef CONFIG_NAND_SPL
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

2
include/configs/MPC8610HPCD.h
View File

@ -177,7 +177,7 @@
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x0C /* Reset altbank mask*/
#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */

3
include/configs/P1_P2_RDB.h
View File

@ -286,6 +286,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#ifdef CONFIG_NAND_SPL
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */

62
include/configs/P2020DS.h
View File

@ -238,7 +238,9 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
#ifdef CONFIG_FSL_NGPIXIS
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
#ifdef CONFIG_PHYS_64BIT
#define PIXIS_BASE_PHYS 0xfffdf0000ull
@ -249,59 +251,11 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
#define PIXIS_VER 0x1 /* Board version at offset 1 */
#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
#define PIXIS_PWR 0x5 /* PIXIS Power status register */
#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
#define PIXIS_VCTL 0x10 /* VELA Control Register */
#define PIXIS_VSTAT 0x11 /* VELA Status Register */
#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
#define PIXIS_VSYSCLK0 0x19 /* VELA SYSCLK0 Register */
#define PIXIS_VSYSCLK1 0x1A /* VELA SYSCLK1 Register */
#define PIXIS_VSYSCLK2 0x1B /* VELA SYSCLK2 Register */
#define PIXIS_VDDRCLK0 0x1C /* VELA DDRCLK0 Register */
#define PIXIS_VDDRCLK1 0x1D /* VELA DDRCLK1 Register */
#define PIXIS_VDDRCLK2 0x1E /* VELA DDRCLK2 Register */
#define PIXIS_VWATCH 0x24 /* Watchdog Register */
#define PIXIS_LED 0x25 /* LED Register */
#define PIXIS_SW(x) 0x20 + (x - 1) * 2
#define PIXIS_EN(x) 0x21 + (x - 1) * 2
#define PIXIS_SW7_LBMAP 0xc0 /* SW7 - cfg_lbmap */
#define PIXIS_SW7_VBANK 0x30 /* SW7 - cfg_vbank */
/* old pixis referenced names */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
#define PIXIS_VSPEED2_TSEC1SER 0x8
#define PIXIS_VSPEED2_TSEC2SER 0x4
#define PIXIS_VSPEED2_TSEC3SER 0x2
#define PIXIS_VSPEED2_TSEC4SER 0x1
#define PIXIS_VCFGEN1_TSEC1SER 0x20
#define PIXIS_VCFGEN1_TSEC2SER 0x20
#define PIXIS_VCFGEN1_TSEC3SER 0x20
#define PIXIS_VCFGEN1_TSEC4SER 0x20
#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
| PIXIS_VSPEED2_TSEC2SER \
| PIXIS_VSPEED2_TSEC3SER \
| PIXIS_VSPEED2_TSEC4SER)
#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
| PIXIS_VCFGEN1_TSEC2SER \
| PIXIS_VCFGEN1_TSEC3SER \
| PIXIS_VCFGEN1_TSEC4SER)
#define PIXIS_LBMAP_SWITCH 7
#define PIXIS_LBMAP_MASK 0xf0
#define PIXIS_LBMAP_SHIFT 4
#define PIXIS_LBMAP_ALTBANK 0x20
#endif
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */

1
include/fdt_support.h
View File

@ -82,6 +82,7 @@ int fdt_resize(void *blob);
int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size);
void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size);
void fdt_del_node_and_alias(void *blob, const char *alias);
#endif /* ifdef CONFIG_OF_LIBFDT */
#endif /* ifndef __FDT_SUPPORT_H */

6
include/fsl_esdhc.h
View File

@ -2,7 +2,7 @@
* FSL SD/MMC Defines
*-------------------------------------------------------------------
*
* Copyright 2007-2008, Freescale Semiconductor, Inc
* Copyright 2007-2008,2010 Freescale Semiconductor, Inc
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -39,6 +39,7 @@
#define SYSCTL_PEREN 0x00000004
#define SYSCTL_HCKEN 0x00000002
#define SYSCTL_IPGEN 0x00000001
#define SYSCTL_RSTA 0x01000000
#define IRQSTAT 0x0002e030
#define IRQSTAT_DMAE (0x10000000)
@ -132,6 +133,8 @@
#define WML 0x2e044
#define WML_WRITE 0x00010000
#define WML_RD_WML_MASK 0xff
#define WML_WR_WML_MASK 0xff0000
#define BLKATTR 0x2e004
#define BLKATTR_CNT(x) ((x & 0xffff) << 16)
@ -148,7 +151,6 @@
struct fsl_esdhc_cfg {
u32 esdhc_base;
u32 no_snoop;
u32 clk_enable;
};
/* Select the correct accessors depending on endianess */