sysmo-bts
/
u-boot
9
0
Fork 0
Code Pull Requests Releases Activity

arm: socfpga: Fix delay in clock manager 

This code claims it needs to wait 7us, yet it uses get_timer() function
which operates with millisecond granularity. Use timer_get_us() instead,
which operates with microsecond granularity.

Signed-off-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Marek Vasut 2015-08-11 00:54:12 +02:00
parent a8535c306c
commit 7e4d2fa2ed
1 changed files with 5 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm/mach-socfpga/clock_manager.c
View File

@ -90,7 +90,7 @@ static void cm_write_with_phase(uint32_t value,
void cm_basic_init(const struct cm_config * const cfg) void cm_basic_init(const struct cm_config * const cfg)
{ {
uint32_t start, timeout; unsigned long end;
/* Start by being paranoid and gate all sw managed clocks */ /* Start by being paranoid and gate all sw managed clocks */
@ -159,12 +159,10 @@ void cm_basic_init(const struct cm_config * const cfg)
writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco); writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
/* /*
* Time starts here * Time starts here. Must wait 7 us from
* must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1) * BGPWRDN_SET(0) to VCO_ENABLE_SET(1).
*/ */
start = get_timer(0); end = timer_get_us() + 7;
/* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */
timeout = 7;
/* main mpu */ /* main mpu */
writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk); writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
@ -204,7 +202,7 @@ void cm_basic_init(const struct cm_config * const cfg)
writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk); writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
/* 7 us must have elapsed before we can enable the VCO */ /* 7 us must have elapsed before we can enable the VCO */
while (get_timer(start) < timeout) while (timer_get_us() < end)
; ;
/* Enable vco */ /* Enable vco */