arm: socfpga: Fix delay in clock manager
This code claims it needs to wait 7us, yet it uses get_timer() function which operates with millisecond granularity. Use timer_get_us() instead, which operates with microsecond granularity. Signed-off-by: Marek Vasut <marex@denx.de>
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@ -90,7 +90,7 @@ static void cm_write_with_phase(uint32_t value,
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void cm_basic_init(const struct cm_config * const cfg)
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void cm_basic_init(const struct cm_config * const cfg)
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{
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{
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uint32_t start, timeout;
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unsigned long end;
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/* Start by being paranoid and gate all sw managed clocks */
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/* Start by being paranoid and gate all sw managed clocks */
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@ -159,12 +159,10 @@ void cm_basic_init(const struct cm_config * const cfg)
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writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
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writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
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/*
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/*
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* Time starts here
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* Time starts here. Must wait 7 us from
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* must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
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* BGPWRDN_SET(0) to VCO_ENABLE_SET(1).
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*/
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*/
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start = get_timer(0);
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end = timer_get_us() + 7;
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/* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */
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timeout = 7;
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/* main mpu */
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/* main mpu */
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writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
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writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
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@ -204,7 +202,7 @@ void cm_basic_init(const struct cm_config * const cfg)
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writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
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writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
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/* 7 us must have elapsed before we can enable the VCO */
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/* 7 us must have elapsed before we can enable the VCO */
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while (get_timer(start) < timeout)
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while (timer_get_us() < end)
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;
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;
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/* Enable vco */
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/* Enable vco */
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