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EXYNOS5: Add L2 Cache Support. 

This patch set adds L2 Cache Support to EXYNOS.

Signed-off-by: Arun Mankuzhi <arun.m@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Rajeshwari Shinde 2012-11-29 20:29:35 +00:00 committed by Minkyu Kang
parent ebd749da69
commit 7ee68fe85f
1 changed files with 36 additions and 0 deletions
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36
arch/arm/cpu/armv7/exynos/soc.c
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@ -23,6 +23,14 @@
#include <common.h>
#include <asm/io.h>
#include <asm/system.h>
enum l2_cache_params {
CACHE_TAG_RAM_SETUP = (1 << 9),
CACHE_DATA_RAM_SETUP = (1 << 5),
CACHE_TAG_RAM_LATENCY = (2 << 6),
CACHE_DATA_RAM_LATENCY = (2 << 0)
};
void reset_cpu(ulong addr)
{
@ -36,3 +44,31 @@ void enable_caches(void)
dcache_enable();
}
#endif
#ifndef CONFIG_SYS_L2CACHE_OFF
/*
* Set L2 cache parameters
*/
static void exynos5_set_l2cache_params(void)
{
unsigned int val = 0;
asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val));
val |= CACHE_TAG_RAM_SETUP |
CACHE_DATA_RAM_SETUP |
CACHE_TAG_RAM_LATENCY |
CACHE_DATA_RAM_LATENCY;
asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
}
/*
* Sets L2 cache related parameters before enabling data cache
*/
void v7_outer_cache_enable(void)
{
if (cpu_is_exynos5())
exynos5_set_l2cache_params();
}
#endif