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MIPS: clear TagLo select 2 during cache init 

Current MIPS cores from Imagination Technologies use TagLo select 2 for
the data cache. The architecture requires that it is safe for software
to write to this register even if it isn't present, so take the trivial
option of clearing both selects 0 & 2.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This commit is contained in:
Paul Burton 2015-01-29 01:28:03 +00:00 committed by Daniel Schwierzeck
parent dd7c72006e
commit 8755d50706
1 changed files with 8 additions and 2 deletions
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10
arch/mips/lib/cache_init.S
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@ -138,6 +138,14 @@ LEAF(mips_cache_reset)
#endif /* CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD */
/*
* The TagLo registers used depend upon the CPU implementation, but the
* architecture requires that it is safe for software to write to both
* TagLo selects 0 & 2 covering supported cases.
*/
mtc0 zero, CP0_TAGLO
mtc0 zero, CP0_TAGLO, 2
/*
* The caches are probably in an indeterminate state, so we force good
* parity into them by doing an invalidate for each line. If
@ -151,7 +159,6 @@ LEAF(mips_cache_reset)
* Initialize the I-cache first,
*/
blez t2, 1f
mtc0 zero, CP0_TAGLO
PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, t2
/* clear tag to invalidate */
@ -169,7 +176,6 @@ LEAF(mips_cache_reset)
* then initialize D-cache.
*/
1: blez t3, 3f
mtc0 zero, CP0_TAGLO
PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, t3
/* clear all tags */