arm: omap3: devkit8000: inherit from ti_armv7_common.h
This commit is contained in:
Anthoine Bourgeois
Tom Rini
parent
1ee9c6c0c0
commit
875e415492
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@ -16,12 +16,8 @@
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_OMAP 1 /* in a TI OMAP core */
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#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
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#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
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#define CONFIG_OMAP_GPIO
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#define CONFIG_OMAP_COMMON
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#define CONFIG_SYS_GENERIC_BOARD
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/*
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* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
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@ -31,11 +27,28 @@
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*/
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#define CONFIG_SYS_TEXT_BASE 0x80100000
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#define CONFIG_SDRC /* The chip has SDRC controller */
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#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <asm/arch/omap3.h>
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#define CONFIG_SDRC /* The chip has SDRC controller */
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#define CONFIG_NAND
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#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
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/* to access nand at */
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/* CS0 */
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/* Physical Memory Map */
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
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#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
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#include <configs/ti_armv7_common.h>
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/* Display CPU and Board information */
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#define CONFIG_DISPLAY_CPUINFO 1
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#define CONFIG_DISPLAY_BOARDINFO 1
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@ -46,16 +59,12 @@
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#define CONFIG_MISC_INIT_R
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_REVISION_TAG 1
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#define CONFIG_OF_LIBFDT 1
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/* Size of malloc() pool */
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#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
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/* Sector */
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#undef CONFIG_SYS_MALLOC_LEN
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
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/* Hardware drivers */
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@ -79,20 +88,15 @@
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#define CONFIG_CONS_INDEX 3
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#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
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#define CONFIG_SERIAL3 3
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
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115200}
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/* MMC */
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#define CONFIG_GENERIC_MMC 1
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#define CONFIG_MMC 1
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#define CONFIG_OMAP_HSMMC 1
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#define CONFIG_DOS_PARTITION 1
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/* SPI */
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#undef CONFIG_SPI
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#undef CONFIG_OMAP3_SPI
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
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#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
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#undef CONFIG_SYS_I2C_OMAP24XX
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#define CONFIG_SYS_I2C_OMAP34XX
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/* TWL4030 */
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@ -100,8 +104,6 @@
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#define CONFIG_TWL4030_LED 1
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/* Board NAND Info */
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#define CONFIG_SYS_NO_FLASH /* no NOR flash */
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#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
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#define MTDIDS_DEFAULT "nand0=nand"
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#define MTDPARTS_DEFAULT "mtdparts=nand:" \
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"512k(x-loader)," \
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@ -110,14 +112,8 @@
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"4m(kernel)," \
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"-(fs)"
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#define CONFIG_NAND_OMAP_GPMC
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#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
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/* to access nand */
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#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
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/* to access nand at */
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/* CS0 */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
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/* devices */
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#define CONFIG_JFFS2_NAND
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/* nand device jffs2 lives on */
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#define CONFIG_JFFS2_DEV "nand0"
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@ -127,20 +123,20 @@
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/* partition */
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/* commands to include */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP /* DHCP support */
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#define CONFIG_CMD_EXT2 /* EXT2 Support */
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#define CONFIG_CMD_FAT /* FAT support */
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#define CONFIG_CMD_I2C /* I2C serial bus support */
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#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
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#define CONFIG_CMD_MMC /* MMC support */
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#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
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#define CONFIG_CMD_NAND /* NAND support */
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#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
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#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
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#undef CONFIG_CMD_IMI /* iminfo */
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#undef CONFIG_CMD_SPI
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#undef CONFIG_CMD_GPIO
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#undef CONFIG_CMD_ASKENV
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#undef CONFIG_CMD_BOOTZ
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#undef CONFIG_SUPPORT_RAW_INITRD
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#undef CONFIG_FAT_WRITE
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#undef CONFIG_CMD_EXT4
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#undef CONFIG_CMD_FS_GENERIC
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/* BOOTP/DHCP options */
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#define CONFIG_BOOTP_SUBNETMASK
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@ -157,10 +153,6 @@
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#undef CONFIG_BOOTP_VENDOREX
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/* Environment information */
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#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"loadaddr=0x82000000\0" \
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"console=ttyO2,115200n8\0" \
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@ -228,38 +220,17 @@
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#define CONFIG_BOOTCOMMAND "run autoboot"
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#define CONFIG_AUTO_COMPLETE 1
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#define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # "
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 128 /* max number of command args */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
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#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
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0x01000000) /* 16MB */
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#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
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/*
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* OMAP3 has 12 GP timers, they can be driven by the system clock
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* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
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* This rate is divided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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/* Physical Memory Map */
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
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#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
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/* NAND and environment organization */
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
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@ -269,47 +240,22 @@
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#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
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#define CONFIG_SYS_INIT_RAM_SIZE 0x800
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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/* SRAM config */
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#define CONFIG_SYS_SRAM_START 0x40200000
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#define CONFIG_SYS_SRAM_SIZE 0x10000
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/* Defines for SPL */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_NAND_SIMPLE
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBDISK_SUPPORT
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SPL_I2C_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_GPIO_SUPPORT
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#define CONFIG_SPL_POWER_SUPPORT
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_NAND_BASE
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#define CONFIG_SPL_NAND_DRIVERS
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#define CONFIG_SPL_NAND_ECC
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SPL_FAT_SUPPORT
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#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
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#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
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#undef CONFIG_SPL_MTD_SUPPORT
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#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
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#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
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#undef CONFIG_SPL_STACK
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#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
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#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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/* NAND boot config */
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#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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@ -325,26 +271,18 @@
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
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#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
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/* SPL OS boot options */
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#define CONFIG_SPL_OS_BOOT
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#define CONFIG_CMD_SPL
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#define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */
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#define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
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0x400000)
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#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
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#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
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#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
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#undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
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#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
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#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
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#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */
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#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */
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#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */
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