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am33xx: Turn a number of 'int' functions to 'void' 

A number of memory initalization functions were int and always returned
0.  Further it's not feasible to be doing error checking here, so simply
turn them into void functions.

Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
Tom Rini 2012-07-24 14:54:41 -07:00 committed by Albert ARIBAUD
parent c48c895433
commit 87a1acbb69
3 changed files with 15 additions and 42 deletions
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29
arch/arm/cpu/armv7/am33xx/ddr.c
View File

@ -39,27 +39,20 @@ static struct ddr_regs *ddr_reg[2] = {
static struct ddr_cmdtctrl *ioctrl_reg = { static struct ddr_cmdtctrl *ioctrl_reg = {
(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR}; (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
/**
* As a convention, all functions here return 0 on success
* -1 on failure.
*/
/** /**
* Configure SDRAM * Configure SDRAM
*/ */
int config_sdram(struct sdram_config *cfg) void config_sdram(struct sdram_config *cfg)
{ {
writel(cfg->refresh, &emif_reg->emif_sdram_ref_ctrl); writel(cfg->refresh, &emif_reg->emif_sdram_ref_ctrl);
writel(cfg->refresh_sh, &emif_reg->emif_sdram_ref_ctrl_shdw); writel(cfg->refresh_sh, &emif_reg->emif_sdram_ref_ctrl_shdw);
writel(cfg->sdrcr, &emif_reg->emif_sdram_config); writel(cfg->sdrcr, &emif_reg->emif_sdram_config);
return 0;
} }
/** /**
* Set SDRAM timings * Set SDRAM timings
*/ */
int set_sdram_timings(struct sdram_timing *t) void set_sdram_timings(struct sdram_timing *t)
{ {
writel(t->time1, &emif_reg->emif_sdram_tim_1); writel(t->time1, &emif_reg->emif_sdram_tim_1);
writel(t->time1_sh, &emif_reg->emif_sdram_tim_1_shdw); writel(t->time1_sh, &emif_reg->emif_sdram_tim_1_shdw);
@ -67,25 +60,21 @@ int set_sdram_timings(struct sdram_timing *t)
writel(t->time2_sh, &emif_reg->emif_sdram_tim_2_shdw); writel(t->time2_sh, &emif_reg->emif_sdram_tim_2_shdw);
writel(t->time3, &emif_reg->emif_sdram_tim_3); writel(t->time3, &emif_reg->emif_sdram_tim_3);
writel(t->time3_sh, &emif_reg->emif_sdram_tim_3_shdw); writel(t->time3_sh, &emif_reg->emif_sdram_tim_3_shdw);
return 0;
} }
/** /**
* Configure DDR PHY * Configure DDR PHY
*/ */
int config_ddr_phy(struct ddr_phy_control *p) void config_ddr_phy(struct ddr_phy_control *p)
{ {
writel(p->reg, &emif_reg->emif_ddr_phy_ctrl_1); writel(p->reg, &emif_reg->emif_ddr_phy_ctrl_1);
writel(p->reg_sh, &emif_reg->emif_ddr_phy_ctrl_1_shdw); writel(p->reg_sh, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
return 0;
} }
/** /**
* Configure DDR CMD control registers * Configure DDR CMD control registers
*/ */
int config_cmd_ctrl(const struct cmd_control *cmd) void config_cmd_ctrl(const struct cmd_control *cmd)
{ {
writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio); writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
writel(cmd->cmd0csforce, &ddr_reg[0]->cm0csforce); writel(cmd->cmd0csforce, &ddr_reg[0]->cm0csforce);
@ -104,14 +93,12 @@ int config_cmd_ctrl(const struct cmd_control *cmd)
writel(cmd->cmd2csdelay, &ddr_reg[0]->cm2csdelay); writel(cmd->cmd2csdelay, &ddr_reg[0]->cm2csdelay);
writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff); writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout); writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
return 0;
} }
/** /**
* Configure DDR DATA registers * Configure DDR DATA registers
*/ */
int config_ddr_data(int macrono, const struct ddr_data *data) void config_ddr_data(int macrono, const struct ddr_data *data)
{ {
writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0); writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
writel(data->datardsratio1, &ddr_reg[macrono]->dt0rdsratio1); writel(data->datardsratio1, &ddr_reg[macrono]->dt0rdsratio1);
@ -131,17 +118,13 @@ int config_ddr_data(int macrono, const struct ddr_data *data)
writel(data->datawrsratio1, &ddr_reg[macrono]->dt0wrsratio1); writel(data->datawrsratio1, &ddr_reg[macrono]->dt0wrsratio1);
writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0); writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
return 0;
} }
int config_io_ctrl(struct ddr_ioctrl *ioctrl) void config_io_ctrl(struct ddr_ioctrl *ioctrl)
{ {
writel(ioctrl->cmd1ctl, &ioctrl_reg->cm0ioctl); writel(ioctrl->cmd1ctl, &ioctrl_reg->cm0ioctl);
writel(ioctrl->cmd2ctl, &ioctrl_reg->cm1ioctl); writel(ioctrl->cmd2ctl, &ioctrl_reg->cm1ioctl);
writel(ioctrl->cmd3ctl, &ioctrl_reg->cm2ioctl); writel(ioctrl->cmd3ctl, &ioctrl_reg->cm2ioctl);
writel(ioctrl->data1ctl, &ioctrl_reg->dt0ioctl); writel(ioctrl->data1ctl, &ioctrl_reg->dt0ioctl);
writel(ioctrl->data2ctl, &ioctrl_reg->dt1ioctl); writel(ioctrl->data2ctl, &ioctrl_reg->dt1ioctl);
return 0;
} }

16
arch/arm/cpu/armv7/am33xx/emif4.c
View File

@ -107,7 +107,6 @@ static void config_vtp(void)
static void config_emif_ddr2(void) static void config_emif_ddr2(void)
{ {
int ret;
struct sdram_config cfg; struct sdram_config cfg;
struct sdram_timing tmg; struct sdram_timing tmg;
struct ddr_phy_control phyc; struct ddr_phy_control phyc;
@ -130,18 +129,9 @@ static void config_emif_ddr2(void)
cfg.refresh_sh = DDR2_EMIF_SDREF; cfg.refresh_sh = DDR2_EMIF_SDREF;
/* Program EMIF instance */ /* Program EMIF instance */
ret = config_ddr_phy(&phyc); config_ddr_phy(&phyc);
if (ret < 0) set_sdram_timings(&tmg);
printf("Couldn't configure phyc\n"); config_sdram(&cfg);
ret = set_sdram_timings(&tmg);
if (ret < 0)
printf("Couldn't configure timings\n");
ret = config_sdram(&cfg);
if (ret < 0)
printf("Couldn't configure SDRAM\n");
} }
void config_ddr(short ddr_type) void config_ddr(short ddr_type)

12
arch/arm/include/asm/arch-am33xx/ddr_defs.h
View File

@ -82,17 +82,17 @@ struct sdram_config {
/** /**
* Configure SDRAM * Configure SDRAM
*/ */
int config_sdram(struct sdram_config *cfg); void config_sdram(struct sdram_config *cfg);
/** /**
* Set SDRAM timings * Set SDRAM timings
*/ */
int set_sdram_timings(struct sdram_timing *val); void set_sdram_timings(struct sdram_timing *val);
/** /**
* Configure DDR PHY * Configure DDR PHY
*/ */
int config_ddr_phy(struct ddr_phy_control *cfg); void config_ddr_phy(struct ddr_phy_control *cfg);
/** /**
* This structure represents the DDR registers on AM33XX devices. * This structure represents the DDR registers on AM33XX devices.
@ -183,12 +183,12 @@ struct ddr_data {
/** /**
* Configure DDR CMD control registers * Configure DDR CMD control registers
*/ */
int config_cmd_ctrl(const struct cmd_control *cmd); void config_cmd_ctrl(const struct cmd_control *cmd);
/** /**
* Configure DDR DATA registers * Configure DDR DATA registers
*/ */
int config_ddr_data(int data_macrono, const struct ddr_data *data); void config_ddr_data(int data_macrono, const struct ddr_data *data);
/** /**
* This structure represents the DDR io control on AM33XX devices. * This structure represents the DDR io control on AM33XX devices.
@ -217,7 +217,7 @@ struct ddr_ioctrl {
/** /**
* Configure DDR io control registers * Configure DDR io control registers
*/ */
int config_io_ctrl(struct ddr_ioctrl *ioctrl); void config_io_ctrl(struct ddr_ioctrl *ioctrl);
struct ddr_ctrl { struct ddr_ctrl {
unsigned int ddrioctrl; unsigned int ddrioctrl;