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arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsi 

This DT node is taken from the Rocketboard.org Linux repsitory. And
is needed to enable (configure) the Cadence DM SPI driver.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
This commit is contained in:
Stefan Roese 2014-11-07 12:37:50 +01:00 committed by Marek Vasut
parent 10e8bf88c0
commit 881f6a448f
2 changed files with 35 additions and 0 deletions
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15
arch/arm/dts/socfpga.dtsi
View File

@ -628,6 +628,21 @@
clock-names = "biu", "ciu";
};
qspi: spi@ff705000 {
compatible = "cadence,qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xff705000 0x1000>,
<0xffa00000 0x1000>;
interrupts = <0 151 4>;
clocks = <&qspi_clk>;
ext-decoder = <0>; /* external decoder */
num-chipselect = <4>;
fifo-depth = <128>;
bus-num = <2>;
status = "disabled";
};
/* Local timer */
timer@fffec600 {
compatible = "arm,cortex-a9-twd-timer";

20
arch/arm/dts/socfpga_cyclone5_socrates.dts
View File

@ -37,3 +37,23 @@
&mmc {
status = "okay";
};
&qspi {
status = "okay";
flash0: n25q00@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q00";
reg = <0>; /* chip select */
spi-max-frequency = <50000000>;
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
read-delay = <4>; /* delay value in read data capture register */
tshsl-ns = <50>;
tsd2d-ns = <50>;
tchsh-ns = <4>;
tslch-ns = <4>;
};
};