am33xx: add ti814x specific register definitions
Support the ti814x specific register definitions within arch-am33xx. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
This commit is contained in:
Matt Porter
Tom Rini
parent
b2e682f7a0
commit
8b029f22a6
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@ -98,6 +98,9 @@ int print_cpuinfo(void)
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case AM335X:
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cpu_s = "AM335X";
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break;
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case TI81XX:
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cpu_s = "TI81XX";
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break;
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default:
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cpu_s = "Unknown cpu type";
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break;
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@ -42,9 +42,10 @@
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#define HS_DEVICE 0x2
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#define GP_DEVICE 0x3
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/* cpu-id for AM33XX family */
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/* cpu-id for AM33XX and TI81XX family */
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#define AM335X 0xB944
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#define DEVICE_ID 0x44E10600
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#define TI81XX 0xB81E
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#define DEVICE_ID (CTRL_BASE + 0x0600)
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/* This gives the status of the boot mode pins on the evm */
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#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
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@ -52,9 +53,11 @@
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/* Reset control */
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#ifdef CONFIG_AM33XX
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#define PRM_RSTCTRL 0x44E00F00
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#define PRM_RSTST 0x44E00F08
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#define PRM_RSTCTRL (PRCM_BASE + 0x0F00)
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#elif defined(CONFIG_TI814X)
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#define PRM_RSTCTRL (PRCM_BASE + 0x00A0)
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#endif
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#define PRM_RSTST (PRM_RSTCTRL + 8)
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#define PRM_RSTCTRL_RESET 0x01
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#define PRM_RSTST_WARM_RESET_MASK 0x232
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@ -19,6 +19,7 @@
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#ifndef __AM33XX_HARDWARE_H
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#define __AM33XX_HARDWARE_H
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#include <config.h>
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#include <asm/arch/omap.h>
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#ifdef CONFIG_AM33XX
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#include <asm/arch/hardware_am33xx.h>
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@ -26,8 +27,9 @@
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#include <asm/arch/hardware_ti814x.h>
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#endif
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/* Module base addresses */
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#define UART0_BASE 0x44E09000
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/*
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* Common hardware definitions
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*/
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/* DM Timer base addresses */
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#define DM_TIMER0_BASE 0x4802C000
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@ -42,21 +44,10 @@
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/* GPIO Base address */
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#define GPIO0_BASE 0x48032000
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#define GPIO1_BASE 0x4804C000
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#define GPIO2_BASE 0x481AC000
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/* BCH Error Location Module */
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#define ELM_BASE 0x48080000
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/* Watchdog Timer */
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#define WDT_BASE 0x44E35000
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/* Control Module Base Address */
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#define CTRL_BASE 0x44E10000
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#define CTRL_DEVICE_BASE 0x44E10600
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/* PRCM Base Address */
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#define PRCM_BASE 0x44E00000
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/* EMIF Base address */
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#define EMIF4_0_CFG_BASE 0x4C000000
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#define EMIF4_1_CFG_BASE 0x4D000000
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@ -90,10 +81,6 @@
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/* CPSW Config space */
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#define CPSW_BASE 0x4A100000
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#define CPSW_MDIO_BASE 0x4A101000
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/* RTC base address */
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#define RTC_BASE 0x44E3E000
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/* OTG */
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#define USB0_OTG_BASE 0x47401000
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@ -19,6 +19,24 @@
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#ifndef __AM33XX_HARDWARE_AM33XX_H
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#define __AM33XX_HARDWARE_AM33XX_H
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/* Module base addresses */
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/* UART Base Address */
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#define UART0_BASE 0x44E09000
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/* GPIO Base address */
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#define GPIO2_BASE 0x481AC000
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/* Watchdog Timer */
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#define WDT_BASE 0x44E35000
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/* Control Module Base Address */
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#define CTRL_BASE 0x44E10000
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#define CTRL_DEVICE_BASE 0x44E10600
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/* PRCM Base Address */
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#define PRCM_BASE 0x44E00000
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/* VTP Base address */
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#define VTP0_CTRL_ADDR 0x44E10E0C
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@ -27,4 +45,10 @@
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#define DDR_PHY_DATA_ADDR 0x44E120C8
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#define DDR_DATA_REGS_NR 2
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/* CPSW Config space */
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#define CPSW_MDIO_BASE 0x4A101000
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/* RTC base address */
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#define RTC_BASE 0x44E3E000
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#endif /* __AM33XX_HARDWARE_AM33XX_H */
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@ -19,6 +19,23 @@
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#ifndef __AM33XX_HARDWARE_TI814X_H
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#define __AM33XX_HARDWARE_TI814X_H
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/* Module base addresses */
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/* UART Base Address */
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#define UART0_BASE 0x48020000
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/* Watchdog Timer */
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#define WDT_BASE 0x481C7000
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/* Control Module Base Address */
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#define CTRL_BASE 0x48140000
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/* PRCM Base Address */
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#define PRCM_BASE 0x48180000
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/* PLL Subsystem Base Address */
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#define PLL_SUBSYS_BASE 0x481C5000
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/* VTP Base address */
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#define VTP0_CTRL_ADDR 0x48140E0C
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@ -27,4 +44,10 @@
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#define DDR_PHY_DATA_ADDR 0x47C0C4C8
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#define DDR_DATA_REGS_NR 4
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/* CPSW Config space */
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#define CPSW_MDIO_BASE 0x4A100800
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/* RTC base address */
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#define RTC_BASE 0x480C0000
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#endif /* __AM33XX_HARDWARE_TI814X_H */
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@ -28,8 +28,13 @@
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* Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
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* at 0x40304000(EMU base) so that our code works for both EMU and GP
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*/
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#ifdef CONFIG_AM33XX
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#define NON_SECURE_SRAM_START 0x40304000
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#define NON_SECURE_SRAM_END 0x4030E000
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#elif defined(CONFIG_TI814X)
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#define NON_SECURE_SRAM_START 0x40300000
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#define NON_SECURE_SRAM_END 0x40320000
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#endif
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/* ROM code defines */
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/* Boot device */
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@ -25,8 +25,13 @@
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#define BOOT_DEVICE_XIP 2
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#define BOOT_DEVICE_NAND 5
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#ifdef CONFIG_AM33XX
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#define BOOT_DEVICE_MMC1 8
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#define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */
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#elif defined(CONFIG_TI814X)
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#define BOOT_DEVICE_MMC1 9
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#define BOOT_DEVICE_MMC2 8 /* ROM only supports 2nd instance */
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#endif
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#define BOOT_DEVICE_SPI 11
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#define BOOT_DEVICE_UART 65
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#define BOOT_DEVICE_USBETH 68
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