mpc83xx: Add PCI-E support for MPC837XEMDS boards
MPC837XEMDS boards can support PCI-E via "PCI-E riser card". The card provides two PCI-E (x2) ports. Though, only one port can be used in x2 mode. Two ports can function simultaneously in x1 mode. PCI-E x1/x2 modes can be switched via "pex_x2" environment variable. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Anton Vorontsov
Kim Phillips
parent
8f11e34b31
commit
8b34557c54
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@ -18,6 +18,7 @@
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#include <tsec.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include "pci.h"
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#include "../common/pq-mds-pib.h"
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int board_early_init_f(void)
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@ -38,14 +39,10 @@ int board_early_init_f(void)
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case SPR_8377:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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case SPR_8378:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII,
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FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V);
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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case SPR_8379:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
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@ -316,6 +313,7 @@ void ft_board_setup(void *blob, bd_t *bd)
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ft_pci_setup(blob, bd);
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if (board_pci_host_broken())
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ft_pci_fixup(blob, bd);
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ft_pcie_fixup(blob, bd);
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#endif
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}
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#endif /* CONFIG_OF_BOARD_SETUP */
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@ -16,7 +16,9 @@
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#include <mpc83xx.h>
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#include <pci.h>
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#include <i2c.h>
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#include <fdt_support.h>
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#include <asm/fsl_i2c.h>
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#include <asm/fsl_serdes.h>
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#if defined(CONFIG_PCI)
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static struct pci_region pci_regions[] = {
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@ -40,15 +42,59 @@ static struct pci_region pci_regions[] = {
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}
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};
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static struct pci_region pcie_regions_0[] = {
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{
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.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
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.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
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.size = CONFIG_SYS_PCIE1_MEM_SIZE,
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.flags = PCI_REGION_MEM,
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},
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{
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.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
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.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
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.size = CONFIG_SYS_PCIE1_IO_SIZE,
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.flags = PCI_REGION_IO,
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},
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};
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static struct pci_region pcie_regions_1[] = {
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{
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.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
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.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
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.size = CONFIG_SYS_PCIE2_MEM_SIZE,
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.flags = PCI_REGION_MEM,
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},
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{
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.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
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.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
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.size = CONFIG_SYS_PCIE2_IO_SIZE,
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.flags = PCI_REGION_IO,
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},
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};
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static int is_pex_x2(void)
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{
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const char *pex_x2 = getenv("pex_x2");
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if (pex_x2 && !strcmp(pex_x2, "yes"))
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return 1;
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return 0;
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}
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void pci_init_board(void)
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{
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile sysconf83xx_t *sysconf = &immr->sysconf;
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
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volatile law83xx_t *pcie_law = sysconf->pcielaw;
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struct pci_region *reg[] = { pci_regions };
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struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
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u32 spridr = in_be32(&immr->sysconf.spridr);
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int pex2 = is_pex_x2();
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if (board_pci_host_broken())
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return;
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goto skip_pci;
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/* Enable all 5 PCI_CLK_OUTPUTS */
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clk->occr |= 0xf8000000;
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@ -64,5 +110,46 @@ void pci_init_board(void)
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udelay(2000);
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mpc83xx_pci_init(1, reg, 0);
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skip_pci:
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/* There is no PEX in MPC8379 parts. */
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if (PARTID_NO_E(spridr) == SPR_8379)
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return;
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/* Configure the clock for PCIE controller */
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clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
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SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
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/* Deassert the resets in the control register */
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out_be32(&sysconf->pecr1, 0xE0008000);
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if (!pex2)
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out_be32(&sysconf->pecr2, 0xE0008000);
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udelay(2000);
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/* Configure PCI Express Local Access Windows */
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out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
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out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
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out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
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out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
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if (pex2)
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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else
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg, 0);
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}
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void ft_pcie_fixup(void *blob, bd_t *bd)
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{
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const char *status = "disabled (PCIE1 is x2)";
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if (!is_pex_x2())
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return;
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do_fixup_by_path(blob, "pci2", "status", status,
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strlen(status) + 1, 1);
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}
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#endif /* CONFIG_PCI */
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@ -0,0 +1,6 @@
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#ifndef __BOARD_MPC837XEMDS_PCI_H
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#define __BOARD_MPC837XEMDS_PCI_H
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extern void ft_pcie_fixup(void *blob, bd_t *bd);
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#endif /* __BOARD_MPC837XEMDS_PCI_H */
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@ -354,11 +354,32 @@
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#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
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#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
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#define CONFIG_SYS_PCIE1_BASE 0xA0000000
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#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
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#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
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#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
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#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
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#define CONFIG_SYS_PCIE2_BASE 0xC0000000
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#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
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#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
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#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
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#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
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#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
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#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
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#ifdef CONFIG_PCI
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#ifndef __ASSEMBLY__
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extern int board_pci_host_broken(void);
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#endif
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#define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */
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#define CONFIG_83XX_GENERIC_PCIE 1
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#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
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#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
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