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Pass sdrc timing values through board_sdrc_timings structure 

Instead of passing individual registers by value to board_get_mem_timings,
pass a board_mem_timings structure pointer for the board files to fill in.
Pass same structure pointer to write_sdrc_timings.  This saves about
90 bytes of space in SPL.

Signed-off-by: Peter Barada <peter.barada@logicpd.com>
This commit is contained in:
Peter Barada 2012-11-13 07:40:28 +00:00 committed by Tom Rini
parent d7aff44a00
commit 8c4445d266
9 changed files with 120 additions and 122 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
arch/arm/cpu/armv7/omap3/sdrc.c
View File

@ -113,18 +113,18 @@ u32 get_sdr_cs_offset(u32 cs)
* - Test CS to make sure it's OK for use * - Test CS to make sure it's OK for use
*/ */
static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base, static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
u32 mcfg, u32 ctrla, u32 ctrlb, u32 rfr_ctrl, u32 mr) struct board_sdrc_timings *timings)
{ {
/* Setup timings we got from the board. */ /* Setup timings we got from the board. */
writel(mcfg, &sdrc_base->cs[cs].mcfg); writel(timings->mcfg, &sdrc_base->cs[cs].mcfg);
writel(ctrla, &sdrc_actim_base->ctrla); writel(timings->ctrla, &sdrc_actim_base->ctrla);
writel(ctrlb, &sdrc_actim_base->ctrlb); writel(timings->ctrlb, &sdrc_actim_base->ctrlb);
writel(rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl); writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
writel(CMD_NOP, &sdrc_base->cs[cs].manual); writel(CMD_NOP, &sdrc_base->cs[cs].manual);
writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
writel(mr, &sdrc_base->cs[cs].mr); writel(timings->mr, &sdrc_base->cs[cs].mr);
/* /*
* Test ram in this bank * Test ram in this bank
@ -143,7 +143,7 @@ static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
void do_sdrc_init(u32 cs, u32 early) void do_sdrc_init(u32 cs, u32 early)
{ {
struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1; struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
u32 mcfg, ctrla, ctrlb, rfr_ctrl, mr; struct board_sdrc_timings timings;
sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
@ -158,7 +158,7 @@ void do_sdrc_init(u32 cs, u32 early)
* setup CS1. * setup CS1.
*/ */
#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_BUILD
get_board_mem_timings(&mcfg, &ctrla, &ctrlb, &rfr_ctrl, &mr); get_board_mem_timings(&timings);
#endif #endif
if (early) { if (early) {
/* reset sdrc controller */ /* reset sdrc controller */
@ -177,11 +177,9 @@ void do_sdrc_init(u32 cs, u32 early)
writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
sdelay(0x20000); sdelay(0x20000);
#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_BUILD
write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb, write_sdrc_timings(CS0, sdrc_actim_base0, &timings);
rfr_ctrl, mr);
make_cs1_contiguous(); make_cs1_contiguous();
write_sdrc_timings(CS1, sdrc_actim_base1, mcfg, ctrla, ctrlb, write_sdrc_timings(CS1, sdrc_actim_base1, &timings);
rfr_ctrl, mr);
#endif #endif
} }
@ -193,14 +191,12 @@ void do_sdrc_init(u32 cs, u32 early)
* so we may be asked now to setup CS1. * so we may be asked now to setup CS1.
*/ */
if (cs == CS1) { if (cs == CS1) {
mcfg = readl(&sdrc_base->cs[CS0].mcfg), timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg),
rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl); timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
ctrla = readl(&sdrc_actim_base0->ctrla), timings.ctrla = readl(&sdrc_actim_base0->ctrla);
ctrlb = readl(&sdrc_actim_base0->ctrlb); timings.ctrlb = readl(&sdrc_actim_base0->ctrlb);
mr = readl(&sdrc_base->cs[CS0].mr); timings.mr = readl(&sdrc_base->cs[CS0].mr);
write_sdrc_timings(cs, sdrc_actim_base1, mcfg, ctrla, ctrlb, write_sdrc_timings(cs, sdrc_actim_base1, &timings);
rfr_ctrl, mr);
} }
} }

13
arch/arm/include/asm/arch-omap3/sys_proto.h
View File

@ -32,6 +32,15 @@ struct emu_hal_params {
u32 param1; u32 param1;
}; };
/* Board SDRC timing values */
struct board_sdrc_timings {
u32 mcfg;
u32 ctrla;
u32 ctrlb;
u32 rfr_ctrl;
u32 mr;
};
void prcm_init(void); void prcm_init(void);
void per_clocks_enable(void); void per_clocks_enable(void);
void ehci_clocks_enable(void); void ehci_clocks_enable(void);
@ -39,8 +48,8 @@ void ehci_clocks_enable(void);
void memif_init(void); void memif_init(void);
void sdrc_init(void); void sdrc_init(void);
void do_sdrc_init(u32, u32); void do_sdrc_init(u32, u32);
void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
u32 *mr); void get_board_mem_timings(struct board_sdrc_timings *timings);
void identify_nand_chip(int *mfr, int *id); void identify_nand_chip(int *mfr, int *id);
void emif4_init(void); void emif4_init(void);
void gpmc_init(void); void gpmc_init(void);

13
board/corscience/tricorder/tricorder.c
View File

@ -91,15 +91,14 @@ int board_mmc_init(bd_t *bis)
* provides the timing values back to the function that configures * provides the timing values back to the function that configures
* the memory. We have either one or two banks of 128MB DDR. * the memory. We have either one or two banks of 128MB DDR.
*/ */
void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, void get_board_mem_timings(struct board_sdrc_timings *timings)
u32 *mr)
{ {
/* General SDRC config */ /* General SDRC config */
*mcfg = MICRON_V_MCFG_165(128 << 20); timings->mcfg = MICRON_V_MCFG_165(128 << 20);
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
/* AC timings */ /* AC timings */
*ctrla = MICRON_V_ACTIMA_165; timings->ctrla = MICRON_V_ACTIMA_165;
*ctrlb = MICRON_V_ACTIMB_165; timings->ctrlb = MICRON_V_ACTIMB_165;
*mr = MICRON_V_MR_165; timings->mr = MICRON_V_MR_165;
} }

29
board/isee/igep0020/igep0020.c
View File

@ -72,27 +72,26 @@ void omap_rev_string(void)
* Description: If we use SPL then there is no x-loader nor config header * Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on both banks. * so we have to setup the DDR timings ourself on both banks.
*/ */
void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, void get_board_mem_timings(struct board_sdrc_timings *timings)
u32 *mr)
{ {
*mr = MICRON_V_MR_165; timings->mr = MICRON_V_MR_165;
#ifdef CONFIG_BOOT_NAND #ifdef CONFIG_BOOT_NAND
*mcfg = MICRON_V_MCFG_200(256 << 20); timings->mcfg = MICRON_V_MCFG_200(256 << 20);
*ctrla = MICRON_V_ACTIMA_200; timings->ctrla = MICRON_V_ACTIMA_200;
*ctrlb = MICRON_V_ACTIMB_200; timings->ctrlb = MICRON_V_ACTIMB_200;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
#else #else
if (get_cpu_family() == CPU_OMAP34XX) { if (get_cpu_family() == CPU_OMAP34XX) {
*mcfg = NUMONYX_V_MCFG_165(256 << 20); timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
*ctrla = NUMONYX_V_ACTIMA_165; timings->ctrla = NUMONYX_V_ACTIMA_165;
*ctrlb = NUMONYX_V_ACTIMB_165; timings->ctrlb = NUMONYX_V_ACTIMB_165;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
} else { } else {
*mcfg = NUMONYX_V_MCFG_200(256 << 20); timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
*ctrla = NUMONYX_V_ACTIMA_200; timings->ctrla = NUMONYX_V_ACTIMA_200;
*ctrlb = NUMONYX_V_ACTIMB_200; timings->ctrlb = NUMONYX_V_ACTIMB_200;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
} }
#endif #endif
} }

29
board/isee/igep0030/igep0030.c
View File

@ -59,27 +59,26 @@ void omap_rev_string(void)
* Description: If we use SPL then there is no x-loader nor config header * Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on both banks. * so we have to setup the DDR timings ourself on both banks.
*/ */
void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, void get_board_mem_timings(struct board_sdrc_timings *timings)
u32 *mr)
{ {
*mr = MICRON_V_MR_165; timings->mr = MICRON_V_MR_165;
#ifdef CONFIG_BOOT_NAND #ifdef CONFIG_BOOT_NAND
*mcfg = MICRON_V_MCFG_200(256 << 20); timings->mcfg = MICRON_V_MCFG_200(256 << 20);
*ctrla = MICRON_V_ACTIMA_200; timings->ctrla = MICRON_V_ACTIMA_200;
*ctrlb = MICRON_V_ACTIMB_200; timings->ctrlb = MICRON_V_ACTIMB_200;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
#else #else
if (get_cpu_family() == CPU_OMAP34XX) { if (get_cpu_family() == CPU_OMAP34XX) {
*mcfg = NUMONYX_V_MCFG_165(256 << 20); timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
*ctrla = NUMONYX_V_ACTIMA_165; timings->ctrla = NUMONYX_V_ACTIMA_165;
*ctrlb = NUMONYX_V_ACTIMB_165; timings->ctrlb = NUMONYX_V_ACTIMB_165;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
} else { } else {
*mcfg = NUMONYX_V_MCFG_200(256 << 20); timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
*ctrla = NUMONYX_V_ACTIMA_200; timings->ctrla = NUMONYX_V_ACTIMA_200;
*ctrlb = NUMONYX_V_ACTIMB_200; timings->ctrlb = NUMONYX_V_ACTIMB_200;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
} }
#endif #endif
} }

37
board/overo/overo.c
View File

@ -147,34 +147,33 @@ int get_board_revision(void)
* Description: If we use SPL then there is no x-loader nor config header * Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on both banks. * so we have to setup the DDR timings ourself on both banks.
*/ */
void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, void get_board_mem_timings(struct board_sdrc_timings *timings)
u32 *mr)
{ {
*mr = MICRON_V_MR_165; timings->mr = MICRON_V_MR_165;
switch (get_board_revision()) { switch (get_board_revision()) {
case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
*mcfg = MICRON_V_MCFG_165(128 << 20); timings->mcfg = MICRON_V_MCFG_165(128 << 20);
*ctrla = MICRON_V_ACTIMA_165; timings->ctrla = MICRON_V_ACTIMA_165;
*ctrlb = MICRON_V_ACTIMB_165; timings->ctrlb = MICRON_V_ACTIMB_165;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
break; break;
case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
*mcfg = MICRON_V_MCFG_165(256 << 20); timings->mcfg = MICRON_V_MCFG_165(256 << 20);
*ctrla = MICRON_V_ACTIMA_165; timings->ctrla = MICRON_V_ACTIMA_165;
*ctrlb = MICRON_V_ACTIMB_165; timings->ctrlb = MICRON_V_ACTIMB_165;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
break; break;
case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
*mcfg = HYNIX_V_MCFG_165(256 << 20); timings->mcfg = HYNIX_V_MCFG_165(256 << 20);
*ctrla = HYNIX_V_ACTIMA_165; timings->ctrla = HYNIX_V_ACTIMA_165;
*ctrlb = HYNIX_V_ACTIMB_165; timings->ctrlb = HYNIX_V_ACTIMB_165;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
break; break;
default: default:
*mcfg = MICRON_V_MCFG_165(128 << 20); timings->mcfg = MICRON_V_MCFG_165(128 << 20);
*ctrla = MICRON_V_ACTIMA_165; timings->ctrla = MICRON_V_ACTIMA_165;
*ctrlb = MICRON_V_ACTIMB_165; timings->ctrlb = MICRON_V_ACTIMB_165;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
} }
} }
#endif #endif

53
board/ti/beagle/beagle.c
View File

@ -139,8 +139,7 @@ static int get_board_revision(void)
* Description: If we use SPL then there is no x-loader nor config header * Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on both banks. * so we have to setup the DDR timings ourself on both banks.
*/ */
void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, void get_board_mem_timings(struct board_sdrc_timings *timings)
u32 *mr)
{ {
int pop_mfr, pop_id; int pop_mfr, pop_id;
@ -151,29 +150,29 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
*/ */
identify_nand_chip(&pop_mfr, &pop_id); identify_nand_chip(&pop_mfr, &pop_id);
*mr = MICRON_V_MR_165; timings->mr = MICRON_V_MR_165;
switch (get_board_revision()) { switch (get_board_revision()) {
case REVISION_C4: case REVISION_C4:
if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) { if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) {
/* 512MB DDR */ /* 512MB DDR */
*mcfg = NUMONYX_V_MCFG_165(512 << 20); timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
*ctrla = NUMONYX_V_ACTIMA_165; timings->ctrla = NUMONYX_V_ACTIMA_165;
*ctrlb = NUMONYX_V_ACTIMB_165; timings->ctrlb = NUMONYX_V_ACTIMB_165;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
break; break;
} else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) { } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) {
/* Beagleboard Rev C4, 512MB Nand/256MB DDR*/ /* Beagleboard Rev C4, 512MB Nand/256MB DDR*/
*mcfg = MICRON_V_MCFG_165(128 << 20); timings->mcfg = MICRON_V_MCFG_165(128 << 20);
*ctrla = MICRON_V_ACTIMA_165; timings->ctrla = MICRON_V_ACTIMA_165;
*ctrlb = MICRON_V_ACTIMB_165; timings->ctrlb = MICRON_V_ACTIMB_165;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
break; break;
} else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) { } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) {
/* Beagleboard Rev C5, 256MB DDR */ /* Beagleboard Rev C5, 256MB DDR */
*mcfg = MICRON_V_MCFG_200(256 << 20); timings->mcfg = MICRON_V_MCFG_200(256 << 20);
*ctrla = MICRON_V_ACTIMA_200; timings->ctrla = MICRON_V_ACTIMA_200;
*ctrlb = MICRON_V_ACTIMB_200; timings->ctrlb = MICRON_V_ACTIMB_200;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
break; break;
} }
case REVISION_XM_A: case REVISION_XM_A:
@ -181,24 +180,24 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
case REVISION_XM_C: case REVISION_XM_C:
if (pop_mfr == 0) { if (pop_mfr == 0) {
/* 256MB DDR */ /* 256MB DDR */
*mcfg = MICRON_V_MCFG_200(256 << 20); timings->mcfg = MICRON_V_MCFG_200(256 << 20);
*ctrla = MICRON_V_ACTIMA_200; timings->ctrla = MICRON_V_ACTIMA_200;
*ctrlb = MICRON_V_ACTIMB_200; timings->ctrlb = MICRON_V_ACTIMB_200;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
} else { } else {
/* 512MB DDR */ /* 512MB DDR */
*mcfg = NUMONYX_V_MCFG_165(512 << 20); timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
*ctrla = NUMONYX_V_ACTIMA_165; timings->ctrla = NUMONYX_V_ACTIMA_165;
*ctrlb = NUMONYX_V_ACTIMB_165; timings->ctrlb = NUMONYX_V_ACTIMB_165;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
} }
break; break;
default: default:
/* Assume 128MB and Micron/165MHz timings to be safe */ /* Assume 128MB and Micron/165MHz timings to be safe */
*mcfg = MICRON_V_MCFG_165(128 << 20); timings->mcfg = MICRON_V_MCFG_165(128 << 20);
*ctrla = MICRON_V_ACTIMA_165; timings->ctrla = MICRON_V_ACTIMA_165;
*ctrlb = MICRON_V_ACTIMB_165; timings->ctrlb = MICRON_V_ACTIMB_165;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
} }
} }
#endif #endif

19
board/ti/evm/evm.c
View File

@ -128,8 +128,7 @@ int board_init(void)
* provides the timing values back to the function that configures * provides the timing values back to the function that configures
* the memory. * the memory.
*/ */
void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, void get_board_mem_timings(struct board_sdrc_timings *timings)
u32 *mr)
{ {
int pop_mfr, pop_id; int pop_mfr, pop_id;
@ -142,17 +141,17 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) { if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
/* 256MB DDR */ /* 256MB DDR */
*mcfg = HYNIX_V_MCFG_200(256 << 20); timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
*ctrla = HYNIX_V_ACTIMA_200; timings->ctrla = HYNIX_V_ACTIMA_200;
*ctrlb = HYNIX_V_ACTIMB_200; timings->ctrlb = HYNIX_V_ACTIMB_200;
} else { } else {
/* 128MB DDR */ /* 128MB DDR */
*mcfg = MICRON_V_MCFG_165(128 << 20); timings->mcfg = MICRON_V_MCFG_165(128 << 20);
*ctrla = MICRON_V_ACTIMA_165; timings->ctrla = MICRON_V_ACTIMA_165;
*ctrlb = MICRON_V_ACTIMB_165; timings->ctrlb = MICRON_V_ACTIMB_165;
} }
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
*mr = MICRON_V_MR_165; timings->mr = MICRON_V_MR_165;
} }
#endif #endif

13
board/timll/devkit8000/devkit8000.c
View File

@ -188,16 +188,15 @@ int spl_start_uboot(void)
* provides the timing values back to the function that configures * provides the timing values back to the function that configures
* the memory. We have either one or two banks of 128MB DDR. * the memory. We have either one or two banks of 128MB DDR.
*/ */
void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, void get_board_mem_timings(struct board_sdrc_timings *timings)
u32 *mr)
{ {
/* General SDRC config */ /* General SDRC config */
*mcfg = MICRON_V_MCFG_165(128 << 20); timings->mcfg = MICRON_V_MCFG_165(128 << 20);
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
/* AC timings */ /* AC timings */
*ctrla = MICRON_V_ACTIMA_165; timings->ctrla = MICRON_V_ACTIMA_165;
*ctrlb = MICRON_V_ACTIMB_165; timings->ctrlb = MICRON_V_ACTIMB_165;
*mr = MICRON_V_MR_165; timings->mr = MICRON_V_MR_165;
} }