ARMV7: AM3517/05: Add support for CraneBoard.
It is a low cost reference design based on Sitara AM3517 SoC from Texas Instruments Please refer to <www.craneboard.org> for more details. Signed-off-by: Srinath <srinath@mistralsolutions.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Srinath
Albert ARIBAUD
parent
ee8485fd84
commit
915162daaa
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@ -726,6 +726,10 @@ Eric Millbrandt <emillbrandt@dekaresearch.com>
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galaxy5200 mpc5200
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Nagendra T S <nagendra@mistralsolutions.com>
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am3517_crane ARM ARMV7 (AM35x SoC)
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Rolf Offermanns <rof@sysgo.de>
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shannon SA1100
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1
MAKEALL
1
MAKEALL
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@ -418,6 +418,7 @@ LIST_ARM11=" \
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## ARMV7 Systems
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#########################################################################
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LIST_ARMV7=" \
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am3517_crane \
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am3517_evm \
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ca9x4_ct_vxp \
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devkit8000 \
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@ -0,0 +1,46 @@
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#
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# Author: Srinath R <srinath@mistralsolutions.com>
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#
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# Based on logicpd/am3517evm/Makefile
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#
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# Copyright (C) 2011 Mistral Solutions Pvt Ltd
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := am3517crane.o
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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clean:
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rm -f $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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@ -0,0 +1,75 @@
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/*
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* am3517crane.c - board file for AM3517 CraneBoard
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*
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* Author: Srinath.R <srinath@mistralsolutions.com>
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*
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* Based on logicpd/am3517evm/am3517evm.c
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*
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* Copyright (C) 2011 Mistral Solutions Pvt Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-types.h>
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#include <i2c.h>
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#include "am3517crane.h"
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* board id for Linux */
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gd->bd->bi_arch_number = MACH_TYPE_CRANEBOARD;
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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return 0;
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}
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/*
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* Routine: misc_init_r
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* Description: Init i2c, ethernet, etc... (done here so udelay works)
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*/
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int misc_init_r(void)
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{
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#ifdef CONFIG_DRIVER_OMAP34XX_I2C
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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#endif
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dieid_num_r();
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return 0;
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}
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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void set_muxconf_regs(void)
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{
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MUX_AM3517CRANE();
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}
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@ -0,0 +1,395 @@
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/*
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* am3517crane.h - Header file for the AM3517 CraneBoard.
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*
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* Author: Srinath R <srinath@mistralsolutions.com>
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*
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* Based on logicpd/am3517evm/am3517evm.h
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*
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* Copyright (C) 2011 Mistral Solutions Pvt Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _AM3517CRANE_H_
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#define _AM3517CRANE_H_
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const omap3_sysinfo sysinfo = {
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DDR_DISCRETE,
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"CraneBoard",
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"NAND",
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};
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/* AM3517 specific mux configuration */
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#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08
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/* CCDC */
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#define CONTROL_PADCONF_CCDC_PCLK 0x01E4
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#define CONTROL_PADCONF_CCDC_FIELD 0x01E6
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#define CONTROL_PADCONF_CCDC_HD 0x01E8
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#define CONTROL_PADCONF_CCDC_VD 0x01EA
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#define CONTROL_PADCONF_CCDC_WEN 0x01EC
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#define CONTROL_PADCONF_CCDC_DATA0 0x01EE
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#define CONTROL_PADCONF_CCDC_DATA1 0x01F0
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#define CONTROL_PADCONF_CCDC_DATA2 0x01F2
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#define CONTROL_PADCONF_CCDC_DATA3 0x01F4
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#define CONTROL_PADCONF_CCDC_DATA4 0x01F6
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#define CONTROL_PADCONF_CCDC_DATA5 0x01F8
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#define CONTROL_PADCONF_CCDC_DATA6 0x01FA
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#define CONTROL_PADCONF_CCDC_DATA7 0x01FC
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/* RMII */
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#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE
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#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200
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#define CONTROL_PADCONF_RMII_RXD0 0x0202
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#define CONTROL_PADCONF_RMII_RXD1 0x0204
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#define CONTROL_PADCONF_RMII_CRS_DV 0x0206
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#define CONTROL_PADCONF_RMII_RXER 0x0208
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#define CONTROL_PADCONF_RMII_TXD0 0x020A
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#define CONTROL_PADCONF_RMII_TXD1 0x020C
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#define CONTROL_PADCONF_RMII_TXEN 0x020E
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#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210
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#define CONTROL_PADCONF_USB0_DRVBUS 0x0212
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/* CAN */
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#define CONTROL_PADCONF_HECC1_TXD 0x0214
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#define CONTROL_PADCONF_HECC1_RXD 0x0216
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#define CONTROL_PADCONF_SYS_BOOT7 0x0218
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#define CONTROL_PADCONF_SDRC_DQS0N 0x021A
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#define CONTROL_PADCONF_SDRC_DQS1N 0x021C
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#define CONTROL_PADCONF_SDRC_DQS2N 0x021E
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#define CONTROL_PADCONF_SDRC_DQS3N 0x0220
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#define CONTROL_PADCONF_STRBEN_DLY0 0x0222
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#define CONTROL_PADCONF_STRBEN_DLY1 0x0224
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#define CONTROL_PADCONF_SYS_BOOT8 0x0226
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/*
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* IEN - Input Enable
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* IDIS - Input Disable
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* PTD - Pull type Down
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* PTU - Pull type Up
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* DIS - Pull type selection is inactive
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* EN - Pull type selection is active
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* M0 - Mode 0
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* The commented string gives the final mux configuration for that pin
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*/
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#define MUX_AM3517CRANE()\
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/*SDRC*/\
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MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_CKE0), (M0))\
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MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0))\
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MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0))\
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MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0))\
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MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0))\
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MUX_VAL(CP(SDRC_CKE0), (M0))\
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MUX_VAL(CP(SDRC_CKE1), (M0))\
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/*sdrc_strben_dly0*/\
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MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0))\
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/*sdrc_strben_dly1*/\
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MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0))\
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/*GPMC*/\
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MUX_VAL(CP(GPMC_A1), (M7))\
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MUX_VAL(CP(GPMC_A2), (IDIS | PTU | DIS | M4))\
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MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M4))\
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MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M4))\
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MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M4))\
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MUX_VAL(CP(GPMC_A6), (M7))\
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MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M4))\
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MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4))\
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MUX_VAL(CP(GPMC_A9), (M7))\
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MUX_VAL(CP(GPMC_A10), (M7))\
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MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0))\
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MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0))\
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MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0))\
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MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0))\
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MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0))\
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MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0))\
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MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0))\
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MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0))\
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MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0))\
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MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0))\
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MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0))\
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MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0))\
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MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0))\
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MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0))\
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MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0))\
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MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0))\
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MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0))\
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MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M4))\
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MUX_VAL(CP(GPMC_NCS2), (M7))\
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MUX_VAL(CP(GPMC_NCS3), (M7))\
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MUX_VAL(CP(GPMC_NCS4), (M7))\
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MUX_VAL(CP(GPMC_NCS5), (M7))\
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MUX_VAL(CP(GPMC_NCS6), (M7))\
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MUX_VAL(CP(GPMC_NCS7), (M7))\
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MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0))/*TP*/\
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MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0))\
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MUX_VAL(CP(GPMC_NBE1), (M7))\
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MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | DIS | M0))\
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MUX_VAL(CP(GPMC_WAIT1), (M7))\
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MUX_VAL(CP(GPMC_WAIT2), (M7))\
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MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4))/*GPIO_65*/\
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/*DSS*/\
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MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0))\
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MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0))\
|
||||
/*MMC1*/\
|
||||
MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0))\
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0))\
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0))\
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0))\
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0))\
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0))\
|
||||
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | DIS | M0))\
|
||||
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | DIS | M0))\
|
||||
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | DIS | M0))\
|
||||
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | DIS | M0))\
|
||||
/*MMC2*/\
|
||||
MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0))\
|
||||
MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | DIS | M0))\
|
||||
/*McBSP*/\
|
||||
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0))\
|
||||
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0))\
|
||||
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0))\
|
||||
\
|
||||
MUX_VAL(CP(MCBSP2_FSX), (M7))\
|
||||
MUX_VAL(CP(MCBSP2_CLKX), (M7))\
|
||||
MUX_VAL(CP(MCBSP2_DR), (M7))\
|
||||
MUX_VAL(CP(MCBSP2_DX), (M7))\
|
||||
\
|
||||
MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0))\
|
||||
\
|
||||
MUX_VAL(CP(MCBSP4_CLKX), (M7))\
|
||||
MUX_VAL(CP(MCBSP4_DR), (M7))\
|
||||
MUX_VAL(CP(MCBSP4_DX), (M7))\
|
||||
MUX_VAL(CP(MCBSP4_FSX), (M7))\
|
||||
/*UART*/\
|
||||
MUX_VAL(CP(UART1_TX), (M7))\
|
||||
MUX_VAL(CP(UART1_RTS), (M7))\
|
||||
MUX_VAL(CP(UART1_CTS), (M7))\
|
||||
MUX_VAL(CP(UART1_RX), (M7))\
|
||||
\
|
||||
MUX_VAL(CP(UART2_CTS), (M7))\
|
||||
MUX_VAL(CP(UART2_RTS), (M7))\
|
||||
MUX_VAL(CP(UART2_TX), (M7))\
|
||||
MUX_VAL(CP(UART2_RX), (M7))\
|
||||
\
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0))\
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0))\
|
||||
/*I2C 1, 2, 3*/\
|
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0))\
|
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0))\
|
||||
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0))\
|
||||
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0))\
|
||||
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0))\
|
||||
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\
|
||||
/*McSPI*/\
|
||||
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4))/*GPIO_171 TP*/\
|
||||
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4))/*GPIO_172 TP*/\
|
||||
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTU | EN | M4))/*GPIO_173 TP*/\
|
||||
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTU | EN | M4))/*GPIO_174 TP*/\
|
||||
MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4))/*GPIO_175 TP*/\
|
||||
MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4))/*GPIO_176 TP*/\
|
||||
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4))/*GPIO_176 TP*/\
|
||||
\
|
||||
MUX_VAL(CP(MCSPI2_CLK), (M7))\
|
||||
MUX_VAL(CP(MCSPI2_SIMO), (M7))\
|
||||
MUX_VAL(CP(MCSPI2_SOMI), (M7))\
|
||||
MUX_VAL(CP(MCSPI2_CS0), (M7))\
|
||||
MUX_VAL(CP(MCSPI2_CS1), (M7))\
|
||||
/*CCDC*/\
|
||||
MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0))\
|
||||
MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1))/*CCDC_DATA8*/\
|
||||
MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0))\
|
||||
MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0))\
|
||||
MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1))/*CCDC_DATA9 */\
|
||||
MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0))\
|
||||
/*RMII*/\
|
||||
MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0))\
|
||||
MUX_VAL(CP(RMII_MDIO_CLK), (M0))\
|
||||
MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0))\
|
||||
MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0))\
|
||||
MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0))\
|
||||
MUX_VAL(CP(RMII_RXER), (PTD | M0))\
|
||||
MUX_VAL(CP(RMII_TXD0), (PTD | M0))\
|
||||
MUX_VAL(CP(RMII_TXD1), (PTD | M0))\
|
||||
MUX_VAL(CP(RMII_TXEN), (PTD | M0))\
|
||||
MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0))\
|
||||
/*HECC*/\
|
||||
MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0))\
|
||||
MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0))\
|
||||
/*HSUSB*/\
|
||||
MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0))\
|
||||
/*HDQ*/\
|
||||
MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4))\
|
||||
/*Control and debug*/\
|
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M4))/*GPIO_1 TPS_SLEEP*/\
|
||||
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0))\
|
||||
/*SYS_nRESWARM*/\
|
||||
MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | EN | M0))/*GPIO_30 ToExp*/\
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0))\
|
||||
MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0))\
|
||||
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))/*GPIO_10 TP*/\
|
||||
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0))\
|
||||
/*JTAG*/\
|
||||
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0))\
|
||||
/*ETK (ES2 onwards)*/\
|
||||
MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M3))\
|
||||
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3))\
|
||||
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M3))\
|
||||
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M3))\
|
||||
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3))\
|
||||
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M3))\
|
||||
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M3))\
|
||||
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M3))\
|
||||
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M3))\
|
||||
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M3))\
|
||||
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M3))\
|
||||
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M3))\
|
||||
MUX_VAL(CP(ETK_D10_ES2), (M7))\
|
||||
MUX_VAL(CP(ETK_D11_ES2), (M7))\
|
||||
MUX_VAL(CP(ETK_D12_ES2), (M7))\
|
||||
MUX_VAL(CP(ETK_D13_ES2), (M7))\
|
||||
MUX_VAL(CP(ETK_D14_ES2), (M7))\
|
||||
MUX_VAL(CP(ETK_D15_ES2), (M7))\
|
||||
/*Die to Die*/\
|
||||
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0))\
|
||||
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0))\
|
||||
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0))\
|
||||
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0))\
|
||||
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0))\
|
||||
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0))\
|
||||
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0))\
|
||||
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0))\
|
||||
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0))\
|
||||
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0))\
|
||||
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0))\
|
||||
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0))\
|
||||
|
||||
#endif /* _AM3517CRANE_H_ */
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
#
|
||||
# Author: Srinath R <srinath@mistralsolutions.com>
|
||||
#
|
||||
# Based on logicpd/am3517evm/config.mk
|
||||
#
|
||||
# Copyright (C) 2011 Mistral Solutions Pvt Ltd
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 2 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
#
|
||||
# Physical Address:
|
||||
# 8000'0000 (bank0)
|
||||
# A000/0000 (bank1)
|
||||
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
|
||||
# (mem base + reserved)
|
||||
|
||||
# For use with external or internal boots.
|
||||
CONFIG_SYS_TEXT_BASE = 0x80008000
|
||||
|
|
@ -116,6 +116,7 @@ omap3_overo arm armv7 overo -
|
|||
omap3_pandora arm armv7 pandora - omap3
|
||||
igep0020 arm armv7 igep0020 isee omap3
|
||||
igep0030 arm armv7 igep0030 isee omap3
|
||||
am3517_crane arm armv7 am3517crane ti omap3
|
||||
am3517_evm arm armv7 am3517evm logicpd omap3
|
||||
omap3_zoom1 arm armv7 zoom1 logicpd omap3
|
||||
omap3_zoom2 arm armv7 zoom2 logicpd omap3
|
||||
|
|
|
|||
|
|
@ -0,0 +1,340 @@
|
|||
/*
|
||||
* am3517_crane.h - Default configuration for AM3517 CraneBoard.
|
||||
*
|
||||
* Author: Srinath.R <srinath@mistralsolutions.com>
|
||||
*
|
||||
* Based on include/configs/am3517evm.h
|
||||
*
|
||||
* Copyright (C) 2011 Mistral Solutions pvt Ltd
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
|
||||
#define CONFIG_OMAP 1 /* in a TI OMAP core */
|
||||
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
|
||||
#define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */
|
||||
|
||||
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
|
||||
|
||||
#include <asm/arch/cpu.h> /* get chip and board defs */
|
||||
#include <asm/arch/omap3.h>
|
||||
|
||||
/*
|
||||
* Display CPU and Board information
|
||||
*/
|
||||
#define CONFIG_DISPLAY_CPUINFO 1
|
||||
#define CONFIG_DISPLAY_BOARDINFO 1
|
||||
|
||||
/* Clock Defines */
|
||||
#define V_OSCK 26000000 /* Clock output from T2 */
|
||||
#define V_SCLK (V_OSCK >> 1)
|
||||
|
||||
#undef CONFIG_USE_IRQ /* no support for IRQs */
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
#define CONFIG_REVISION_TAG 1
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
|
||||
/* initial data */
|
||||
/*
|
||||
* DDR related
|
||||
*/
|
||||
#define CONFIG_OMAP3_MICRON_DDR 1 /* Micron DDR */
|
||||
#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
|
||||
/*
|
||||
* NS16550 Configuration
|
||||
*/
|
||||
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
|
||||
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 3
|
||||
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
|
||||
#define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
|
||||
115200}
|
||||
#define CONFIG_MMC 1
|
||||
#define CONFIG_OMAP3_MMC 1
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
|
||||
/*
|
||||
* USB configuration
|
||||
* Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
|
||||
* Enable CONFIG_MUSB_UDC for Device functionalities.
|
||||
*/
|
||||
#define CONFIG_USB_AM35X 1
|
||||
#define CONFIG_MUSB_HCD 1
|
||||
|
||||
#ifdef CONFIG_USB_AM35X
|
||||
|
||||
#ifdef CONFIG_MUSB_HCD
|
||||
#define CONFIG_CMD_USB
|
||||
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONGIG_CMD_STORAGE
|
||||
#define CONFIG_CMD_FAT
|
||||
|
||||
#ifdef CONFIG_USB_KEYBOARD
|
||||
#define CONFIG_SYS_USB_EVENT_POLL
|
||||
#define CONFIG_PREBOOT "usb start"
|
||||
#endif /* CONFIG_USB_KEYBOARD */
|
||||
|
||||
#endif /* CONFIG_MUSB_HCD */
|
||||
|
||||
#ifdef CONFIG_MUSB_UDC
|
||||
/* USB device configuration */
|
||||
#define CONFIG_USB_DEVICE 1
|
||||
#define CONFIG_USB_TTY 1
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
|
||||
/* Change these to suit your needs */
|
||||
#define CONFIG_USBD_VENDORID 0x0451
|
||||
#define CONFIG_USBD_PRODUCTID 0x5678
|
||||
#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
|
||||
#define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE"
|
||||
#endif /* CONFIG_MUSB_UDC */
|
||||
|
||||
#endif /* CONFIG_USB_AM35X */
|
||||
|
||||
/* commands to include */
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_EXT2 /* EXT2 Support */
|
||||
#define CONFIG_CMD_FAT /* FAT support */
|
||||
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
|
||||
|
||||
#define CONFIG_CMD_I2C /* I2C serial bus support */
|
||||
#define CONFIG_CMD_MMC /* MMC support */
|
||||
#define CONFIG_CMD_NAND /* NAND support */
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_PING
|
||||
|
||||
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
|
||||
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
|
||||
#undef CONFIG_CMD_IMI /* iminfo */
|
||||
#undef CONFIG_CMD_IMLS /* List all found images */
|
||||
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 1
|
||||
#define CONFIG_SYS_I2C_BUS 0
|
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1
|
||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1
|
||||
|
||||
#undef CONFIG_CMD_NET
|
||||
#undef CONFIG_CMD_NFS
|
||||
/*
|
||||
* Board NAND Info.
|
||||
*/
|
||||
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
|
||||
/* to access nand */
|
||||
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
|
||||
/* to access */
|
||||
/* nand at CS0 */
|
||||
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
|
||||
/* NAND devices */
|
||||
#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
|
||||
|
||||
#define CONFIG_JFFS2_NAND
|
||||
/* nand device jffs2 lives on */
|
||||
#define CONFIG_JFFS2_DEV "nand0"
|
||||
/* start of jffs2 partition */
|
||||
#define CONFIG_JFFS2_PART_OFFSET 0x680000
|
||||
#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
|
||||
|
||||
/* Environment information */
|
||||
#define CONFIG_BOOTDELAY 10
|
||||
|
||||
#define CONFIG_BOOTFILE uImage
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"loadaddr=0x82000000\0" \
|
||||
"console=ttyS2,115200n8\0" \
|
||||
"mmcargs=setenv bootargs console=${console} " \
|
||||
"root=/dev/mmcblk0p2 rw " \
|
||||
"rootfstype=ext3 rootwait\0" \
|
||||
"nandargs=setenv bootargs console=${console} " \
|
||||
"root=/dev/mtdblock4 rw " \
|
||||
"rootfstype=jffs2\0" \
|
||||
"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source ${loadaddr}\0" \
|
||||
"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"nandboot=echo Booting from nand ...; " \
|
||||
"run nandargs; " \
|
||||
"nand read ${loadaddr} 280000 400000; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"if mmc init; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loaduimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run nandboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run nandboot; fi"
|
||||
|
||||
#define CONFIG_AUTO_COMPLETE 1
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define V_PROMPT "AM3517_CRANE # "
|
||||
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_SYS_PROMPT V_PROMPT
|
||||
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 32 /* max number of command */
|
||||
/* args */
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
|
||||
/* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
|
||||
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
|
||||
0x01F00000) /* 31MB */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
|
||||
/* address */
|
||||
|
||||
/*
|
||||
* AM3517 has 12 GP timers, they can be driven by the system clock
|
||||
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
|
||||
* This rate is divided by a local divisor.
|
||||
*/
|
||||
#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
|
||||
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Stack sizes
|
||||
*
|
||||
* The stack sizes are set up in start.S using the settings below
|
||||
*/
|
||||
#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
|
||||
#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
|
||||
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
|
||||
#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
|
||||
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
|
||||
|
||||
/* SDRAM Bank Allocation method */
|
||||
#define SDRC_R_B_C 1
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
|
||||
/* **** PISMO SUPPORT *** */
|
||||
|
||||
/* Configure the PISMO */
|
||||
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
|
||||
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
|
||||
/* on one chip */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE boot_flash_base
|
||||
|
||||
/* Monitor at start of flash */
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
|
||||
#define CONFIG_NAND_OMAP_GPMC
|
||||
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
|
||||
#define CONFIG_ENV_IS_IN_NAND 1
|
||||
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
|
||||
|
||||
#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
|
||||
#define CONFIG_ENV_OFFSET boot_flash_off
|
||||
#define CONFIG_ENV_ADDR boot_flash_env_addr
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* CFI FLASH driver setup
|
||||
*/
|
||||
/* timeout values are in ticks */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
|
||||
|
||||
/* Flash banks JFFS2 should use */
|
||||
#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
|
||||
CONFIG_SYS_MAX_NAND_DEVICE)
|
||||
#define CONFIG_SYS_JFFS2_MEM_NAND
|
||||
/* use flash_info[2] */
|
||||
#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
|
||||
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern unsigned int boot_flash_base;
|
||||
extern volatile unsigned int boot_flash_env_addr;
|
||||
extern unsigned int boot_flash_off;
|
||||
extern unsigned int boot_flash_sec;
|
||||
extern unsigned int boot_flash_type;
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue