OMAP3: Add common board, interrupt and system info
Add common board, interrupt and system info code. Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
This commit is contained in:
Dirk Behme
Jean-Christophe PLAGNIOL-VILLARD
parent
5ed3e8659e
commit
91eee54673
|
|
@ -0,0 +1,344 @@
|
|||
/*
|
||||
*
|
||||
* Common board functions for OMAP3 based boards.
|
||||
*
|
||||
* (C) Copyright 2004-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* Author :
|
||||
* Sunil Kumar <sunilsaini05@gmail.com>
|
||||
* Shashi Ranjan <shashiranjanmca05@gmail.com>
|
||||
*
|
||||
* Derived from Beagle Board and 3430 SDP code by
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
*
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/mem.h>
|
||||
|
||||
extern omap3_sysinfo sysinfo;
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: delay
|
||||
* Description: spinning delay to use before udelay works
|
||||
*****************************************************************************/
|
||||
static inline void delay(unsigned long loops)
|
||||
{
|
||||
__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
|
||||
"bne 1b":"=r" (loops):"0"(loops));
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: secure_unlock
|
||||
* Description: Setup security registers for access
|
||||
* (GP Device only)
|
||||
*****************************************************************************/
|
||||
void secure_unlock_mem(void)
|
||||
{
|
||||
pm_t *pm_rt_ape_base = (pm_t *)PM_RT_APE_BASE_ADDR_ARM;
|
||||
pm_t *pm_gpmc_base = (pm_t *)PM_GPMC_BASE_ADDR_ARM;
|
||||
pm_t *pm_ocm_ram_base = (pm_t *)PM_OCM_RAM_BASE_ADDR_ARM;
|
||||
pm_t *pm_iva2_base = (pm_t *)PM_IVA2_BASE_ADDR_ARM;
|
||||
sms_t *sms_base = (sms_t *)OMAP34XX_SMS_BASE;
|
||||
|
||||
/* Protection Module Register Target APE (PM_RT) */
|
||||
writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
|
||||
writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
|
||||
writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
|
||||
writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
|
||||
|
||||
writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
|
||||
writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
|
||||
writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
|
||||
|
||||
writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
|
||||
writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
|
||||
writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
|
||||
writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
|
||||
|
||||
/* IVA Changes */
|
||||
writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
|
||||
writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
|
||||
writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
|
||||
|
||||
/* SDRC region 0 public */
|
||||
writel(UNLOCK_1, &sms_base->rg_att0);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: secureworld_exit()
|
||||
* Description: If chip is EMU and boot type is external
|
||||
* configure secure registers and exit secure world
|
||||
* general use.
|
||||
*****************************************************************************/
|
||||
void secureworld_exit()
|
||||
{
|
||||
unsigned long i;
|
||||
|
||||
/* configrue non-secure access control register */
|
||||
__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
|
||||
/* enabling co-processor CP10 and CP11 accesses in NS world */
|
||||
__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
|
||||
/*
|
||||
* allow allocation of locked TLBs and L2 lines in NS world
|
||||
* allow use of PLE registers in NS world also
|
||||
*/
|
||||
__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
|
||||
__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
|
||||
|
||||
/* Enable ASA in ACR register */
|
||||
__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
|
||||
__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
|
||||
__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
|
||||
|
||||
/* Exiting secure world */
|
||||
__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
|
||||
__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
|
||||
__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: setup_auxcr()
|
||||
* Description: Write to AuxCR desired value using SMI.
|
||||
* general use.
|
||||
*****************************************************************************/
|
||||
void setup_auxcr()
|
||||
{
|
||||
unsigned long i;
|
||||
volatile unsigned int j;
|
||||
/* Save r0, r12 and restore them after usage */
|
||||
__asm__ __volatile__("mov %0, r12":"=r"(j));
|
||||
__asm__ __volatile__("mov %0, r0":"=r"(i));
|
||||
|
||||
/*
|
||||
* GP Device ROM code API usage here
|
||||
* r12 = AUXCR Write function and r0 value
|
||||
*/
|
||||
__asm__ __volatile__("mov r12, #0x3");
|
||||
__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
|
||||
/* Enabling ASA */
|
||||
__asm__ __volatile__("orr r0, r0, #0x10");
|
||||
/* Enable L1NEON */
|
||||
__asm__ __volatile__("orr r0, r0, #1 << 5");
|
||||
/* SMI instruction to call ROM Code API */
|
||||
__asm__ __volatile__(".word 0xE1600070");
|
||||
__asm__ __volatile__("mov r0, %0":"=r"(i));
|
||||
__asm__ __volatile__("mov r12, %0":"=r"(j));
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: try_unlock_sram()
|
||||
* Description: If chip is GP/EMU(special) type, unlock the SRAM for
|
||||
* general use.
|
||||
*****************************************************************************/
|
||||
void try_unlock_memory()
|
||||
{
|
||||
int mode;
|
||||
int in_sdram = is_running_in_sdram();
|
||||
|
||||
/*
|
||||
* if GP device unlock device SRAM for general use
|
||||
* secure code breaks for Secure/Emulation device - HS/E/T
|
||||
*/
|
||||
mode = get_device_type();
|
||||
if (mode == GP_DEVICE)
|
||||
secure_unlock_mem();
|
||||
|
||||
/*
|
||||
* If device is EMU and boot is XIP external booting
|
||||
* Unlock firewalls and disable L2 and put chip
|
||||
* out of secure world
|
||||
*
|
||||
* Assuming memories are unlocked by the demon who put us in SDRAM
|
||||
*/
|
||||
if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
|
||||
&& (!in_sdram)) {
|
||||
secure_unlock_mem();
|
||||
secureworld_exit();
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: s_init
|
||||
* Description: Does early system init of muxing and clocks.
|
||||
* - Called path is with SRAM stack.
|
||||
*****************************************************************************/
|
||||
void s_init(void)
|
||||
{
|
||||
int in_sdram = is_running_in_sdram();
|
||||
|
||||
watchdog_init();
|
||||
|
||||
try_unlock_memory();
|
||||
|
||||
/*
|
||||
* Right now flushing at low MPU speed.
|
||||
* Need to move after clock init
|
||||
*/
|
||||
v7_flush_dcache_all(get_device_type());
|
||||
#ifndef CONFIG_ICACHE_OFF
|
||||
icache_enable();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_L2_OFF
|
||||
l2cache_disable();
|
||||
#else
|
||||
l2cache_enable();
|
||||
#endif
|
||||
/*
|
||||
* Writing to AuxCR in U-boot using SMI for GP DEV
|
||||
* Currently SMI in Kernel on ES2 devices seems to have an issue
|
||||
* Once that is resolved, we can postpone this config to kernel
|
||||
*/
|
||||
if (get_device_type() == GP_DEVICE)
|
||||
setup_auxcr();
|
||||
|
||||
set_muxconf_regs();
|
||||
delay(100);
|
||||
|
||||
prcm_init();
|
||||
|
||||
per_clocks_enable();
|
||||
|
||||
if (!in_sdram)
|
||||
sdrc_init();
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: wait_for_command_complete
|
||||
* Description: Wait for posting to finish on watchdog
|
||||
*****************************************************************************/
|
||||
void wait_for_command_complete(watchdog_t *wd_base)
|
||||
{
|
||||
int pending = 1;
|
||||
do {
|
||||
pending = readl(&wd_base->wwps);
|
||||
} while (pending);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: watchdog_init
|
||||
* Description: Shut down watch dogs
|
||||
*****************************************************************************/
|
||||
void watchdog_init(void)
|
||||
{
|
||||
watchdog_t *wd2_base = (watchdog_t *)WD2_BASE;
|
||||
prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
|
||||
|
||||
/*
|
||||
* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
|
||||
* either taken care of by ROM (HS/EMU) or not accessible (GP).
|
||||
* We need to take care of WD2-MPU or take a PRCM reset. WD3
|
||||
* should not be running and does not generate a PRCM reset.
|
||||
*/
|
||||
|
||||
sr32(&prcm_base->fclken_wkup, 5, 1, 1);
|
||||
sr32(&prcm_base->iclken_wkup, 5, 1, 1);
|
||||
wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
|
||||
|
||||
writel(WD_UNLOCK1, &wd2_base->wspr);
|
||||
wait_for_command_complete(wd2_base);
|
||||
writel(WD_UNLOCK2, &wd2_base->wspr);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Routine: dram_init
|
||||
* Description: sets uboots idea of sdram size
|
||||
*****************************************************************************/
|
||||
int dram_init(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
unsigned int size0 = 0, size1 = 0;
|
||||
u32 btype;
|
||||
|
||||
btype = get_board_type();
|
||||
|
||||
display_board_info(btype);
|
||||
|
||||
/*
|
||||
* If a second bank of DDR is attached to CS1 this is
|
||||
* where it can be started. Early init code will init
|
||||
* memory on CS0.
|
||||
*/
|
||||
if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
|
||||
do_sdrc_init(CS1, NOT_EARLY);
|
||||
make_cs1_contiguous();
|
||||
}
|
||||
|
||||
size0 = get_sdr_cs_size(CS0);
|
||||
size1 = get_sdr_cs_size(CS1);
|
||||
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = size0;
|
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
|
||||
gd->bd->bi_dram[1].size = size1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Dummy function to handle errors for EABI incompatibility
|
||||
*****************************************************************************/
|
||||
void raise(void)
|
||||
{
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Dummy function to handle errors for EABI incompatibility
|
||||
*****************************************************************************/
|
||||
void abort(void)
|
||||
{
|
||||
}
|
||||
|
||||
#ifdef CONFIG_NAND_OMAP_GPMC
|
||||
/******************************************************************************
|
||||
* OMAP3 specific command to switch between NAND HW and SW ecc
|
||||
*****************************************************************************/
|
||||
static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
if (argc != 2)
|
||||
goto usage;
|
||||
if (strncmp(argv[1], "hw", 2) == 0)
|
||||
omap_nand_switch_ecc(1);
|
||||
else if (strncmp(argv[1], "sw", 2) == 0)
|
||||
omap_nand_switch_ecc(0);
|
||||
else
|
||||
goto usage;
|
||||
|
||||
return 0;
|
||||
|
||||
usage:
|
||||
printf ("Usage: nandecc %s\n", cmdtp->help);
|
||||
return 1;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
nandecc, 2, 1, do_switch_ecc,
|
||||
"nandecc - switch OMAP3 NAND ECC calculation algorithm\n",
|
||||
"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm\n"
|
||||
);
|
||||
|
||||
#endif /* CONFIG_NAND_OMAP_GPMC */
|
||||
|
|
@ -0,0 +1,297 @@
|
|||
/*
|
||||
* (C) Copyright 2008
|
||||
* Texas Instruments
|
||||
*
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Syed Moahmmed Khasim <khasim@ti.com>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
* Alex Zuepke <azu@sysgo.de>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/proc-armv/ptrace.h>
|
||||
|
||||
#define TIMER_LOAD_VAL 0
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
/* enable IRQ interrupts */
|
||||
void enable_interrupts(void)
|
||||
{
|
||||
unsigned long temp;
|
||||
__asm__ __volatile__("mrs %0, cpsr\n"
|
||||
"bic %0, %0, #0x80\n" "msr cpsr_c, %0":"=r"(temp)
|
||||
::"memory");
|
||||
}
|
||||
|
||||
/*
|
||||
* disable IRQ/FIQ interrupts
|
||||
* returns true if interrupts had been enabled before we disabled them
|
||||
*/
|
||||
int disable_interrupts(void)
|
||||
{
|
||||
unsigned long old, temp;
|
||||
__asm__ __volatile__("mrs %0, cpsr\n"
|
||||
"orr %1, %0, #0xc0\n"
|
||||
"msr cpsr_c, %1":"=r"(old), "=r"(temp)
|
||||
::"memory");
|
||||
return (old & 0x80) == 0;
|
||||
}
|
||||
#else
|
||||
void enable_interrupts(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
int disable_interrupts(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void bad_mode(void)
|
||||
{
|
||||
panic("Resetting CPU ...\n");
|
||||
reset_cpu(0);
|
||||
}
|
||||
|
||||
void show_regs(struct pt_regs *regs)
|
||||
{
|
||||
unsigned long flags;
|
||||
const char *processor_modes[] = {
|
||||
"USER_26", "FIQ_26", "IRQ_26", "SVC_26",
|
||||
"UK4_26", "UK5_26", "UK6_26", "UK7_26",
|
||||
"UK8_26", "UK9_26", "UK10_26", "UK11_26",
|
||||
"UK12_26", "UK13_26", "UK14_26", "UK15_26",
|
||||
"USER_32", "FIQ_32", "IRQ_32", "SVC_32",
|
||||
"UK4_32", "UK5_32", "UK6_32", "ABT_32",
|
||||
"UK8_32", "UK9_32", "UK10_32", "UND_32",
|
||||
"UK12_32", "UK13_32", "UK14_32", "SYS_32",
|
||||
};
|
||||
|
||||
flags = condition_codes(regs);
|
||||
|
||||
printf("pc : [<%08lx>] lr : [<%08lx>]\n"
|
||||
"sp : %08lx ip : %08lx fp : %08lx\n",
|
||||
instruction_pointer(regs),
|
||||
regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
|
||||
printf("r10: %08lx r9 : %08lx r8 : %08lx\n",
|
||||
regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
|
||||
printf("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
|
||||
regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
|
||||
printf("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
|
||||
regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
|
||||
printf("Flags: %c%c%c%c",
|
||||
flags & CC_N_BIT ? 'N' : 'n',
|
||||
flags & CC_Z_BIT ? 'Z' : 'z',
|
||||
flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
|
||||
printf(" IRQs %s FIQs %s Mode %s%s\n",
|
||||
interrupts_enabled(regs) ? "on" : "off",
|
||||
fast_interrupts_enabled(regs) ? "on" : "off",
|
||||
processor_modes[processor_mode(regs)],
|
||||
thumb_mode(regs) ? " (T)" : "");
|
||||
}
|
||||
|
||||
void do_undefined_instruction(struct pt_regs *pt_regs)
|
||||
{
|
||||
printf("undefined instruction\n");
|
||||
show_regs(pt_regs);
|
||||
bad_mode();
|
||||
}
|
||||
|
||||
void do_software_interrupt(struct pt_regs *pt_regs)
|
||||
{
|
||||
printf("software interrupt\n");
|
||||
show_regs(pt_regs);
|
||||
bad_mode();
|
||||
}
|
||||
|
||||
void do_prefetch_abort(struct pt_regs *pt_regs)
|
||||
{
|
||||
printf("prefetch abort\n");
|
||||
show_regs(pt_regs);
|
||||
bad_mode();
|
||||
}
|
||||
|
||||
void do_data_abort(struct pt_regs *pt_regs)
|
||||
{
|
||||
printf("data abort\n");
|
||||
show_regs(pt_regs);
|
||||
bad_mode();
|
||||
}
|
||||
|
||||
void do_not_used(struct pt_regs *pt_regs)
|
||||
{
|
||||
printf("not used\n");
|
||||
show_regs(pt_regs);
|
||||
bad_mode();
|
||||
}
|
||||
|
||||
void do_fiq(struct pt_regs *pt_regs)
|
||||
{
|
||||
printf("fast interrupt request\n");
|
||||
show_regs(pt_regs);
|
||||
bad_mode();
|
||||
}
|
||||
|
||||
void do_irq(struct pt_regs *pt_regs)
|
||||
{
|
||||
printf("interrupt request\n");
|
||||
show_regs(pt_regs);
|
||||
bad_mode();
|
||||
}
|
||||
|
||||
|
||||
static ulong timestamp;
|
||||
static ulong lastinc;
|
||||
static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE;
|
||||
|
||||
/* nothing really to do with interrupts, just starts up a counter. */
|
||||
int interrupt_init(void)
|
||||
{
|
||||
/* start the counter ticking up, reload value on overflow */
|
||||
writel(TIMER_LOAD_VAL, &timer_base->tldr);
|
||||
/* enable timer */
|
||||
writel((CONFIG_SYS_PVT << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
|
||||
&timer_base->tclr);
|
||||
|
||||
reset_timer_masked(); /* init the timestamp and lastinc value */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* timer without interrupts
|
||||
*/
|
||||
void reset_timer(void)
|
||||
{
|
||||
reset_timer_masked();
|
||||
}
|
||||
|
||||
ulong get_timer(ulong base)
|
||||
{
|
||||
return get_timer_masked() - base;
|
||||
}
|
||||
|
||||
void set_timer(ulong t)
|
||||
{
|
||||
timestamp = t;
|
||||
}
|
||||
|
||||
/* delay x useconds AND perserve advance timstamp value */
|
||||
void udelay(unsigned long usec)
|
||||
{
|
||||
ulong tmo, tmp;
|
||||
|
||||
/* if "big" number, spread normalization to seconds */
|
||||
if (usec >= 1000) {
|
||||
/* if "big" number, spread normalization to seconds */
|
||||
tmo = usec / 1000;
|
||||
/* find number of "ticks" to wait to achieve target */
|
||||
tmo *= CONFIG_SYS_HZ;
|
||||
tmo /= 1000; /* finish normalize. */
|
||||
} else {/* else small number, don't kill it prior to HZ multiply */
|
||||
tmo = usec * CONFIG_SYS_HZ;
|
||||
tmo /= (1000 * 1000);
|
||||
}
|
||||
|
||||
tmp = get_timer(0); /* get current timestamp */
|
||||
/* if setting this forward will roll time stamp */
|
||||
if ((tmo + tmp + 1) < tmp)
|
||||
/* reset "advancing" timestamp to 0, set lastinc value */
|
||||
reset_timer_masked();
|
||||
else
|
||||
tmo += tmp; /* else, set advancing stamp wake up time */
|
||||
while (get_timer_masked() < tmo) /* loop till event */
|
||||
/*NOP*/;
|
||||
}
|
||||
|
||||
void reset_timer_masked(void)
|
||||
{
|
||||
/* reset time, capture current incrementer value time */
|
||||
lastinc = readl(&timer_base->tcrr);
|
||||
timestamp = 0; /* start "advancing" time stamp from 0 */
|
||||
}
|
||||
|
||||
ulong get_timer_masked(void)
|
||||
{
|
||||
ulong now = readl(&timer_base->tcrr); /* current tick value */
|
||||
|
||||
if (now >= lastinc) /* normal mode (non roll) */
|
||||
/* move stamp fordward with absoulte diff ticks */
|
||||
timestamp += (now - lastinc);
|
||||
else /* we have rollover of incrementer */
|
||||
timestamp += (0xFFFFFFFF - lastinc) + now;
|
||||
lastinc = now;
|
||||
return timestamp;
|
||||
}
|
||||
|
||||
/* waits specified delay value and resets timestamp */
|
||||
void udelay_masked(unsigned long usec)
|
||||
{
|
||||
ulong tmo;
|
||||
ulong endtime;
|
||||
signed long diff;
|
||||
|
||||
/* if "big" number, spread normalization to seconds */
|
||||
if (usec >= 1000) {
|
||||
/* start to normalize for usec to ticks per sec */
|
||||
tmo = usec / 1000;
|
||||
/* find number of "ticks" to wait to achieve target */
|
||||
tmo *= CONFIG_SYS_HZ;
|
||||
tmo /= 1000; /* finish normalize. */
|
||||
} else { /* else small number, */
|
||||
/* don't kill it prior to HZ multiply */
|
||||
tmo = usec * CONFIG_SYS_HZ;
|
||||
tmo /= (1000 * 1000);
|
||||
}
|
||||
endtime = get_timer_masked() + tmo;
|
||||
|
||||
do {
|
||||
ulong now = get_timer_masked();
|
||||
diff = endtime - now;
|
||||
} while (diff >= 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (read timebase as long long).
|
||||
* On ARM it just returns the timer value.
|
||||
*/
|
||||
unsigned long long get_ticks(void)
|
||||
{
|
||||
return get_timer(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency).
|
||||
* On ARM it returns the number of timer ticks per second.
|
||||
*/
|
||||
ulong get_tbclk(void)
|
||||
{
|
||||
ulong tbclk;
|
||||
tbclk = CONFIG_SYS_HZ;
|
||||
return tbclk;
|
||||
}
|
||||
|
|
@ -0,0 +1,254 @@
|
|||
/*
|
||||
* (C) Copyright 2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* Author :
|
||||
* Manikandan Pillai <mani.pillai@ti.com>
|
||||
*
|
||||
* Derived from Beagle Board and 3430 SDP code by
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
* Syed Mohammed Khasim <khasim@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/mem.h> /* get mem tables */
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <i2c.h>
|
||||
|
||||
extern omap3_sysinfo sysinfo;
|
||||
static gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE;
|
||||
static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
|
||||
static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
|
||||
|
||||
/******************************************
|
||||
* get_cpu_rev(void) - extract version info
|
||||
******************************************/
|
||||
u32 get_cpu_rev(void)
|
||||
{
|
||||
u32 cpuid = 0;
|
||||
|
||||
/*
|
||||
* On ES1.0 the IDCODE register is not exposed on L4
|
||||
* so using CPU ID to differentiate
|
||||
* between ES2.0 and ES1.0.
|
||||
*/
|
||||
__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
|
||||
if ((cpuid & 0xf) == 0x0)
|
||||
return CPU_3430_ES1;
|
||||
else
|
||||
return CPU_3430_ES2;
|
||||
|
||||
}
|
||||
|
||||
/****************************************************
|
||||
* is_mem_sdr() - return 1 if mem type in use is SDR
|
||||
****************************************************/
|
||||
u32 is_mem_sdr(void)
|
||||
{
|
||||
if (readl(&sdrc_base->cs[CS0].mr) == SDP_SDRC_MR_0_SDR)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/***********************************************************************
|
||||
* get_cs0_size() - get size of chip select 0/1
|
||||
************************************************************************/
|
||||
u32 get_sdr_cs_size(u32 cs)
|
||||
{
|
||||
u32 size;
|
||||
|
||||
/* get ram size field */
|
||||
size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
|
||||
size &= 0x3FF; /* remove unwanted bits */
|
||||
size *= SZ_2M; /* find size in MB */
|
||||
return size;
|
||||
}
|
||||
|
||||
/***********************************************************************
|
||||
* get_sdr_cs_offset() - get offset of cs from cs0 start
|
||||
************************************************************************/
|
||||
u32 get_sdr_cs_offset(u32 cs)
|
||||
{
|
||||
u32 offset;
|
||||
|
||||
if (!cs)
|
||||
return 0;
|
||||
|
||||
offset = readl(&sdrc_base->cs_cfg);
|
||||
offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
|
||||
|
||||
return offset;
|
||||
}
|
||||
|
||||
/***********************************************************************
|
||||
* get_board_type() - get board type based on current production stats.
|
||||
* - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper info.
|
||||
* when they are available we can get info from there. This should
|
||||
* be correct of all known boards up until today.
|
||||
* - NOTE-2- EEPROMs are populated but they are updated very slowly. To
|
||||
* avoid waiting on them we will use ES version of the chip to get info.
|
||||
* A later version of the FPGA migth solve their speed issue.
|
||||
************************************************************************/
|
||||
u32 get_board_type(void)
|
||||
{
|
||||
if (get_cpu_rev() == CPU_3430_ES2)
|
||||
return sysinfo.board_type_v2;
|
||||
else
|
||||
return sysinfo.board_type_v1;
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
* get_gpmc0_base() - Return current address hardware will be
|
||||
* fetching from. The below effectively gives what is correct, its a bit
|
||||
* mis-leading compared to the TRM. For the most general case the mask
|
||||
* needs to be also taken into account this does work in practice.
|
||||
* - for u-boot we currently map:
|
||||
* -- 0 to nothing,
|
||||
* -- 4 to flash
|
||||
* -- 8 to enent
|
||||
* -- c to wifi
|
||||
****************************************************************************/
|
||||
u32 get_gpmc0_base(void)
|
||||
{
|
||||
u32 b;
|
||||
|
||||
b = readl(&gpmc_cs_base->config7);
|
||||
b &= 0x1F; /* keep base [5:0] */
|
||||
b = b << 24; /* ret 0x0b000000 */
|
||||
return b;
|
||||
}
|
||||
|
||||
/*******************************************************************
|
||||
* get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
|
||||
*******************************************************************/
|
||||
u32 get_gpmc0_width(void)
|
||||
{
|
||||
return WIDTH_16BIT;
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* get_board_rev() - setup to pass kernel board revision information
|
||||
* returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
|
||||
*************************************************************************/
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
return 0x20;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* display_board_info() - print banner with board info.
|
||||
*********************************************************************/
|
||||
void display_board_info(u32 btype)
|
||||
{
|
||||
char *mem_s, *sec_s;
|
||||
|
||||
if (is_mem_sdr())
|
||||
mem_s = "mSDR";
|
||||
else
|
||||
mem_s = "LPDDR";
|
||||
|
||||
switch (get_device_type()) {
|
||||
case TST_DEVICE:
|
||||
sec_s = "TST";
|
||||
break;
|
||||
case EMU_DEVICE:
|
||||
sec_s = "EMU";
|
||||
break;
|
||||
case HS_DEVICE:
|
||||
sec_s = "HS";
|
||||
break;
|
||||
case GP_DEVICE:
|
||||
sec_s = "GP";
|
||||
break;
|
||||
default:
|
||||
sec_s = "?";
|
||||
}
|
||||
|
||||
printf("OMAP%s-%s rev %d, CPU-OPP2 L3-165MHz\n", sysinfo.cpu_string,
|
||||
sec_s, get_cpu_rev());
|
||||
printf("%s + %s/%s\n", sysinfo.board_string,
|
||||
mem_s, sysinfo.nand_string);
|
||||
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* get_base(); get upper addr of current execution
|
||||
*******************************************************/
|
||||
u32 get_base(void)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
|
||||
val &= 0xF0000000;
|
||||
val >>= 28;
|
||||
return val;
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* is_running_in_flash() - tell if currently running in
|
||||
* FLASH.
|
||||
*******************************************************/
|
||||
u32 is_running_in_flash(void)
|
||||
{
|
||||
if (get_base() < 4)
|
||||
return 1; /* in FLASH */
|
||||
|
||||
return 0; /* running in SRAM or SDRAM */
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* is_running_in_sram() - tell if currently running in
|
||||
* SRAM.
|
||||
*******************************************************/
|
||||
u32 is_running_in_sram(void)
|
||||
{
|
||||
if (get_base() == 4)
|
||||
return 1; /* in SRAM */
|
||||
|
||||
return 0; /* running in FLASH or SDRAM */
|
||||
}
|
||||
|
||||
/********************************************************
|
||||
* is_running_in_sdram() - tell if currently running in
|
||||
* SDRAM.
|
||||
*******************************************************/
|
||||
u32 is_running_in_sdram(void)
|
||||
{
|
||||
if (get_base() > 4)
|
||||
return 1; /* in SDRAM */
|
||||
|
||||
return 0; /* running in SRAM or FLASH */
|
||||
}
|
||||
|
||||
/***************************************************************
|
||||
* get_boot_type() - Is this an XIP type device or a stream one
|
||||
* bits 4-0 specify type. Bit 5 says mem/perif
|
||||
***************************************************************/
|
||||
u32 get_boot_type(void)
|
||||
{
|
||||
return (readl(&ctrl_base->status) & SYSBOOT_MASK);
|
||||
}
|
||||
|
||||
/*************************************************************
|
||||
* get_device_type(): tell if GP/HS/EMU/TST
|
||||
*************************************************************/
|
||||
u32 get_device_type(void)
|
||||
{
|
||||
return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
|
||||
}
|
||||
|
|
@ -33,9 +33,13 @@ ifeq ($(ARCH),arm)
|
|||
ifeq ($(BOARD),omap2420h4)
|
||||
LOAD_ADDR = 0x80300000
|
||||
else
|
||||
ifeq ($(CPU),omap3)
|
||||
LOAD_ADDR = 0x80300000
|
||||
else
|
||||
LOAD_ADDR = 0xc100000
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(ARCH),mips)
|
||||
LOAD_ADDR = 0x80200000 -T mips.lds
|
||||
|
|
|
|||
Loading…
Reference in New Issue