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bitops: introduce BIT() definition 

introduce BIT() definition, used in at91_udc gadget
driver.

Signed-off-by: Heiko Schocher <hs@denx.de>
[remove all other occurrences of BIT(x) definition]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
This commit is contained in:
Heiko Schocher 2015-09-07 13:43:52 +02:00 committed by Tom Rini
parent 9d2f6a9ae7
commit 92a3188d7d
16 changed files with 2 additions and 27 deletions
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1
arch/arm/include/asm/arch-am33xx/cpu.h
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@ -17,7 +17,6 @@
#include <asm/arch/hardware.h>
#define BIT(x) (1 << x)
#define CL_BIT(x) (0 << x)
/* Timer register bits */

2
arch/arm/include/asm/arch-hi6220/gpio.h
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@ -11,8 +11,6 @@
#define HI6220_GPIO_BASE(bank) (((bank < 4) ? 0xf8011000 : \
0xf7020000 - 0x4000) + (0x1000 * bank))
#define BIT(x) (1 << (x))
#define HI6220_GPIO_PER_BANK 8
#define HI6220_GPIO_DIR 0x400

2
arch/arm/include/asm/arch-omap5/cpu.h
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@ -56,8 +56,6 @@ struct watchdog {
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
#define BIT(x) (1 << (x))
#define WD_UNLOCK1 0xAAAA
#define WD_UNLOCK2 0x5555

2
arch/arm/include/asm/arch-tegra/dc.h
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@ -364,8 +364,6 @@ struct dc_ctlr {
struct dc_winbuf_reg winbuf; /* WINBUF A/B/C 0x800 ~ 0x80d */
};
#define BIT(pos) (1U << pos)
/* DC_CMD_DISPLAY_COMMAND 0x032 */
#define CTRL_MODE_SHIFT 5
#define CTRL_MODE_MASK (0x3 << CTRL_MODE_SHIFT)

2
arch/arm/mach-davinci/cpu.c
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@ -28,8 +28,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define PLLC_PLLDIV8 0x170
#define PLLC_PLLDIV9 0x174
#define BIT(x) (1 << (x))
/* SOC-specific pll info */
#ifdef CONFIG_SOC_DM355
#define ARM_PLLDIV PLLC_PLLDIV1

2
arch/arm/mach-keystone/include/mach/clock_defs.h
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@ -11,8 +11,6 @@
#include <asm/arch/hardware.h>
#define BIT(x) (1 << (x))
/* PLL Control Registers */
struct pllctl_regs {
u32 ctl; /* 00 */

2
arch/arm/mach-keystone/include/mach/hardware.h
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@ -24,8 +24,6 @@ typedef volatile unsigned int *dv_reg_p;
#endif
#define BIT(x) (1 << (x))
#define KS2_DDRPHY_PIR_OFFSET 0x04
#define KS2_DDRPHY_PGCR0_OFFSET 0x08
#define KS2_DDRPHY_PGCR1_OFFSET 0x0C

2
arch/arm/mach-mvebu/include/mach/soc.h
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@ -11,8 +11,6 @@
#ifndef _MVEBU_SOC_H
#define _MVEBU_SOC_H
#define BIT(x) (1 << (x))
#define SOC_MV78460_ID 0x7846
#define SOC_88F6810_ID 0x6810
#define SOC_88F6820_ID 0x6820

2
arch/arm/mach-zynq/include/mach/gpio.h
View File

@ -71,6 +71,4 @@
/* GPIO upper 16 bit mask */
#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
#define BIT(x) (1<<x)
#endif /* _ZYNQ_GPIO_H */

2
drivers/ddr/marvell/a38x/ddr3_init.h
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@ -32,8 +32,6 @@
*/
#define MV_DEBUG_INIT
#define BIT(x) (1 << (x))
#ifdef MV_DEBUG_INIT
#define DEBUG_INIT_S(s) puts(s)
#define DEBUG_INIT_D(d, l) printf("%x", d)

1
drivers/mtd/nand/jz4740_nand.c
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@ -16,7 +16,6 @@
#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
#define BIT(x) (1 << (x))
#define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
#define JZ_NAND_ECC_CTRL_RS BIT(2)
#define JZ_NAND_ECC_CTRL_RESET BIT(1)

2
drivers/spi/davinci_spi.c
View File

@ -15,8 +15,6 @@
#include <asm/io.h>
#include <asm/arch/hardware.h>
#define BIT(x) (1 << (x))
/* SPIGCR0 */
#define SPIGCR0_SPIENA_MASK 0x1
#define SPIGCR0_SPIRST_MASK 0x0

2
drivers/spi/ep93xx_spi.c
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@ -16,8 +16,6 @@
#include <asm/arch/ep93xx.h>
#define BIT(x) (1<<(x))
#define SSPBASE SPI_BASE
#define SSPCR0 0x0000

2
drivers/video/anx9804.c
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@ -14,8 +14,6 @@
#include <i2c.h>
#include "anx9804.h"
#define BIT(x) (1 << (x))
/* Registers at i2c address 0x38 */
#define ANX9804_HDCP_CONTROL_0_REG 0x01

1
include/fsl-mc/fsl_mc.h
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@ -12,7 +12,6 @@
#define MC_CCSR_BASE_ADDR \
((struct mc_ccsr_registers __iomem *)0x8340000)
#define BIT(x) (1 << (x))
#define GCR1_P1_STOP BIT(31)
#define GCR1_P2_STOP BIT(30)
#define GCR1_P1_DE_RST BIT(23)

2
include/linux/bitops.h
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@ -3,6 +3,8 @@
#include <asm/types.h>
#define BIT(nr) (1UL << (nr))
/*
* ffs: find first bit set. This is defined the same way as
* the libc and compiler builtin ffs routines, therefore