From b1af67fe5e019bbfaca9ca4ec7086fbdb69c440a Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 13 Sep 2012 19:07:56 +0000 Subject: [PATCH 01/11] i2c: sh_i2c.c: support iccl and icch extension R-mobile SoC (at least SH73A0) has extension bits to store 8th bit of iccl and icch. This patch add support for the extentin bits. Acked-by: Nobuhiro Iwamatsu Signed-off-by: Tetsuyuki Kobayashi --- drivers/i2c/sh_i2c.c | 30 ++++++++++++++++++++++-------- include/configs/kzm9g.h | 1 + 2 files changed, 23 insertions(+), 8 deletions(-) diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index 3147123bba..035069f07b 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -48,7 +48,13 @@ static struct sh_i2c *base; #define SH_IC_WAIT (1 << 1) #define SH_IC_DTE (1 << 0) -static u8 iccl, icch; +#ifdef CONFIG_SH_I2C_8BIT +/* store 8th bit of iccl and icch in ICIC register */ +#define SH_I2C_ICIC_ICCLB8 (1 << 7) +#define SH_I2C_ICIC_ICCHB8 (1 << 6) +#endif + +static u16 iccl, icch; #define IRQ_WAIT 1000 @@ -76,12 +82,20 @@ static void irq_busy(struct sh_i2c *base) static void i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop) { + u8 icic = 0; + writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr); writeb(readb(&base->iccr) | SH_I2C_ICCR_ICE, &base->iccr); - writeb(iccl, &base->iccl); - writeb(icch, &base->icch); - writeb(0, &base->icic); + writeb(iccl & 0xff, &base->iccl); + writeb(icch & 0xff, &base->icch); +#ifdef CONFIG_SH_I2C_8BIT + if (iccl > 0xff) + icic |= SH_I2C_ICIC_ICCLB8; + if (icch > 0xff) + icic |= SH_I2C_ICIC_ICCHB8; +#endif + writeb(icic, &base->icic); writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); irq_dte(base); @@ -206,18 +220,18 @@ void i2c_init(int speed, int slaveaddr) denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW); tmp = num * 10 / denom; if (tmp % 10 >= 5) - iccl = (u8)((num/denom) + 1); + iccl = (u16)((num/denom) + 1); else - iccl = (u8)(num/denom); + iccl = (u16)(num/denom); /* Calculate the value for icch. From the data sheet: icch = (p clock / transfer rate) * (H / (L + H)) */ num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH; tmp = num * 10 / denom; if (tmp % 10 >= 5) - icch = (u8)((num/denom) + 1); + icch = (u16)((num/denom) + 1); else - icch = (u8)(num/denom); + icch = (u16)(num/denom); } /* diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 3a882e396b..0132e9d0df 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -154,6 +154,7 @@ /* I2C */ #define CONFIG_CMD_I2C #define CONFIG_SH_I2C 1 +#define CONFIG_SH_I2C_8BIT #define CONFIG_HARD_I2C #define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_MAX_I2C_BUS (2) From 57d7c80472d8c87f7c6d321f89a5aed47c865b5a Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 13 Sep 2012 19:07:57 +0000 Subject: [PATCH 02/11] i2c: sh_i2c.c: correct BUSY bit define in ICSR Correct BUSY bit define in ICSR from (1<<3) to (1<<4). Acked-by: Nobuhiro Iwamatsu Signed-off-by: Tetsuyuki Kobayashi --- drivers/i2c/sh_i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index 035069f07b..eced61de0b 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -43,7 +43,7 @@ static struct sh_i2c *base; #define SH_I2C_ICCR_SCP (1 << 0) /* ICSR / ICIC */ -#define SH_IC_BUSY (1 << 3) +#define SH_IC_BUSY (1 << 4) #define SH_IC_TACK (1 << 2) #define SH_IC_WAIT (1 << 1) #define SH_IC_DTE (1 << 0) From 3ce2703d8f11b0b5c28409d8335f36bef258831b Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 13 Sep 2012 19:07:58 +0000 Subject: [PATCH 03/11] i2c: sh_i2c.c: adjust for SH73A0 Adjust i2c_raw_read() in sh_i2c.c to work for SH73A0. After this patch, "i2c md" and "i2c mw" command on U-Boot work properly on KZM-A9-GT board. Acked-by: Nobuhiro Iwamatsu Signed-off-by: Tetsuyuki Kobayashi --- drivers/i2c/sh_i2c.c | 4 ++++ include/configs/kzm9g.h | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index eced61de0b..c667a1bdf0 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -135,8 +135,12 @@ static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg) { u8 ret; +#if defined(CONFIG_SH73A0) + i2c_set_addr(base, id, reg, 0); +#else i2c_set_addr(base, id, reg, 1); udelay(100); +#endif writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); irq_dte(base); diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 0132e9d0df..75b9257e1d 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -163,7 +163,7 @@ #define CONFIG_SYS_I2C_SLAVE (0x7F) #define CONFIG_SH_I2C_DATA_HIGH (4) #define CONFIG_SH_I2C_DATA_LOW (5) -#define CONFIG_SH_I2C_CLOCK (41666666) +#define CONFIG_SH_I2C_CLOCK (104000000) /* 104 MHz */ #define CONFIG_SH_I2C_BASE0 (0xE6820000) #define CONFIG_SH_I2C_BASE1 (0xE6822000) From 020ec727a6bda10f47d69926814d476c0085e8a9 Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 13 Sep 2012 19:07:59 +0000 Subject: [PATCH 04/11] i2c: sh_i2c.c: support I2C2, I2C3 and I2C4 sh_i2c.c support I2C0 and I2C1. This patch extends it to I2C4. Acked-by: Nobuhiro Iwamatsu Signed-off-by: Tetsuyuki Kobayashi --- drivers/i2c/sh_i2c.c | 15 +++++++++++++++ include/configs/kzm9g.h | 5 ++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index c667a1bdf0..d50c8eca6d 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -184,6 +184,21 @@ int i2c_set_bus_num(unsigned int bus) case 1: base = (void *)CONFIG_SH_I2C_BASE1; break; +#ifdef CONFIG_SH_I2C_BASE2 + case 2: + base = (void *)CONFIG_SH_I2C_BASE2; + break; +#endif +#ifdef CONFIG_SH_I2C_BASE3 + case 3: + base = (void *)CONFIG_SH_I2C_BASE3; + break; +#endif +#ifdef CONFIG_SH_I2C_BASE4 + case 4: + base = (void *)CONFIG_SH_I2C_BASE4; + break; +#endif default: return -1; } diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 75b9257e1d..4898fb60f4 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -157,7 +157,7 @@ #define CONFIG_SH_I2C_8BIT #define CONFIG_HARD_I2C #define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_MAX_I2C_BUS (2) +#define CONFIG_SYS_MAX_I2C_BUS (5) #define CONFIG_SYS_I2C_MODULE #define CONFIG_SYS_I2C_SPEED (100000) /* 100 kHz */ #define CONFIG_SYS_I2C_SLAVE (0x7F) @@ -166,5 +166,8 @@ #define CONFIG_SH_I2C_CLOCK (104000000) /* 104 MHz */ #define CONFIG_SH_I2C_BASE0 (0xE6820000) #define CONFIG_SH_I2C_BASE1 (0xE6822000) +#define CONFIG_SH_I2C_BASE2 (0xE6824000) +#define CONFIG_SH_I2C_BASE3 (0xE6826000) +#define CONFIG_SH_I2C_BASE4 (0xE6828000) #endif /* __KZM9G_H */ From d042d7121b13d98bd403e7b64438ce55cfefd0d9 Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 13 Sep 2012 19:08:00 +0000 Subject: [PATCH 05/11] i2c: sh_i2c: enable i2c_probe Before this patch i2c_probe() always returned 0 and "i2c probe" command did not work properly. Modify i2c_set_addr() to check TACK when waiting DTE and make i2c_probe() call this function. Acked-by: Nobuhiro Iwamatsu Signed-off-by: Tetsuyuki Kobayashi --- drivers/i2c/sh_i2c.c | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index d50c8eca6d..a7204cc1d0 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -69,6 +69,20 @@ static void irq_dte(struct sh_i2c *base) } } +static int irq_dte_with_tack(struct sh_i2c *base) +{ + int i; + + for (i = 0 ; i < IRQ_WAIT ; i++) { + if (SH_IC_DTE & readb(&base->icsr)) + break; + if (SH_IC_TACK & readb(&base->icsr)) + return -1; + udelay(10); + } + return 0; +} + static void irq_busy(struct sh_i2c *base) { int i; @@ -80,9 +94,9 @@ static void irq_busy(struct sh_i2c *base) } } -static void i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop) +static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop) { - u8 icic = 0; + u8 icic = SH_IC_TACK; writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr); writeb(readb(&base->iccr) | SH_I2C_ICCR_ICE, &base->iccr); @@ -100,14 +114,18 @@ static void i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop) writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); irq_dte(base); + writeb(readb(&base->icsr) & ~SH_IC_TACK, &base->icsr); writeb(id << 1, &base->icdr); - irq_dte(base); + if (irq_dte_with_tack(base) != 0) + return -1; writeb(reg, &base->icdr); if (stop) writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &base->iccr); - irq_dte(base); + if (irq_dte_with_tack(base) != 0) + return -1; + return 0; } static void i2c_finish(struct sh_i2c *base) @@ -305,5 +323,9 @@ int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len) */ int i2c_probe(u8 chip) { - return 0; + int ret; + + ret = i2c_set_addr(base, chip, 0, 1); + i2c_finish(base); + return ret; } From 0e5fb33cf7fa7352e9ecf88a834dd5e178f0e80f Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 13 Sep 2012 19:08:01 +0000 Subject: [PATCH 06/11] i2c: sh_i2c.c: check error in i2c_read and i2c_write Before this patch, i2c_{read,write} always returned 0. Check TACK in i2c_raw_{read,write} so that i2c_{read,write} return non-zero when error. Acked-by: Nobuhiro Iwamatsu Signed-off-by: Tetsuyuki Kobayashi --- drivers/i2c/sh_i2c.c | 50 ++++++++++++++++++++++++++++---------------- 1 file changed, 32 insertions(+), 18 deletions(-) diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index a7204cc1d0..afcb503f95 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -134,29 +134,37 @@ static void i2c_finish(struct sh_i2c *base) writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr); } -static void i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val) +static int i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val) { - i2c_set_addr(base, id, reg, 0); + int ret = -1; + if (i2c_set_addr(base, id, reg, 0) != 0) + goto exit0; udelay(10); writeb(val, &base->icdr); - irq_dte(base); + if (irq_dte_with_tack(base) != 0) + goto exit0; writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &base->iccr); - irq_dte(base); + if (irq_dte_with_tack(base) != 0) + goto exit0; irq_busy(base); - + ret = 0; +exit0: i2c_finish(base); + return ret; } -static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg) +static int i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg) { - u8 ret; + int ret = -1; #if defined(CONFIG_SH73A0) - i2c_set_addr(base, id, reg, 0); + if (i2c_set_addr(base, id, reg, 0) != 0) + goto exit0; #else - i2c_set_addr(base, id, reg, 1); + if (i2c_set_addr(base, id, reg, 1) != 0) + goto exit0; udelay(100); #endif @@ -164,17 +172,19 @@ static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg) irq_dte(base); writeb(id << 1 | 0x01, &base->icdr); - irq_dte(base); + if (irq_dte_with_tack(base) != 0) + goto exit0; writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &base->iccr); - irq_dte(base); + if (irq_dte_with_tack(base) != 0) + goto exit0; - ret = readb(&base->icdr); + ret = readb(&base->icdr) & 0xff; writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &base->iccr); readb(&base->icdr); /* Dummy read */ irq_busy(base); - +exit0: i2c_finish(base); return ret; @@ -286,10 +296,14 @@ void i2c_init(int speed, int slaveaddr) */ int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len) { + int ret; int i = 0; - for (i = 0 ; i < len ; i++) - buffer[i] = i2c_raw_read(base, chip, addr + i); - + for (i = 0 ; i < len ; i++) { + ret = i2c_raw_read(base, chip, addr + i); + if (ret < 0) + return -1; + buffer[i] = ret & 0xff; + } return 0; } @@ -310,8 +324,8 @@ int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len) { int i = 0; for (i = 0; i < len ; i++) - i2c_raw_write(base, chip, addr + i, buffer[i]); - + if (i2c_raw_write(base, chip, addr + i, buffer[i]) != 0) + return -1; return 0; } From 937b6862def9f2545f7f804441919b767be105b9 Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 13 Sep 2012 19:08:03 +0000 Subject: [PATCH 07/11] arm: rmobile: kzm9g: enable I2C1 Supply clock to I2C1 and release resetting. Acked-by: Nobuhiro Iwamatsu Signed-off-by: Tetsuyuki Kobayashi --- board/kmc/kzm9g/kzm9g.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c index 525c97aea6..4bfecb67e6 100644 --- a/board/kmc/kzm9g/kzm9g.c +++ b/board/kmc/kzm9g/kzm9g.c @@ -43,6 +43,7 @@ DECLARE_GLOBAL_DATA_PTR; #define SMSTPCR1_CMT0 (1 << 24) #define SMSTPCR1_I2C0 (1 << 16) #define SMSTPCR3_USB (1 << 22) +#define SMSTPCR3_I2C1 (1 << 23) #define PORT32CR (0xE6051020) #define PORT33CR (0xE6051021) @@ -287,8 +288,8 @@ int board_early_init_f(void) clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); - clrbits_le32(&cpg->smstpcr3, SMSTPCR3_USB); - clrbits_le32(&cpg_srcr->srcr3, SMSTPCR3_USB); + clrbits_le32(&cpg->smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); + clrbits_le32(&cpg_srcr->srcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); writel(VCLKCR1_D, &cpg->vclkcr1); /* Setup SCIF4 / workaround */ From 650f95b0c7ee4a43a3dc3e64b1074f02a6b4100e Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 13 Sep 2012 19:08:04 +0000 Subject: [PATCH 08/11] arm: rmobile: kzm9g: enable I2C2 Acked-by: Nobuhiro Iwamatsu Signed-off-by: Tetsuyuki Kobayashi --- board/kmc/kzm9g/kzm9g.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c index 4bfecb67e6..54f25e097c 100644 --- a/board/kmc/kzm9g/kzm9g.c +++ b/board/kmc/kzm9g/kzm9g.c @@ -344,6 +344,8 @@ int board_init(void) gpio_direction_output(GPIO_PORT15, 1); /* I2C */ + gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL); + gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL); gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL); gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL); From f539094f4886779432053f5ddf7bfb2f45d182e1 Mon Sep 17 00:00:00 2001 From: Tetsuyuki Kobayashi Date: Thu, 13 Sep 2012 19:08:05 +0000 Subject: [PATCH 09/11] i2c: sh_i2c: use setbits/clrbits macro Use setbits/clrbits macro when read-modify-write register. Signed-off-by: Tetsuyuki Kobayashi Acked-by: Nobuhiro Iwamatsu --- drivers/i2c/sh_i2c.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index afcb503f95..44ba90ef57 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -98,8 +98,8 @@ static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop) { u8 icic = SH_IC_TACK; - writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr); - writeb(readb(&base->iccr) | SH_I2C_ICCR_ICE, &base->iccr); + clrbits_8(&base->iccr, SH_I2C_ICCR_ICE); + setbits_8(&base->iccr, SH_I2C_ICCR_ICE); writeb(iccl & 0xff, &base->iccl); writeb(icch & 0xff, &base->icch); @@ -114,7 +114,7 @@ static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop) writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); irq_dte(base); - writeb(readb(&base->icsr) & ~SH_IC_TACK, &base->icsr); + clrbits_8(&base->icsr, SH_IC_TACK); writeb(id << 1, &base->icdr); if (irq_dte_with_tack(base) != 0) return -1; @@ -131,7 +131,7 @@ static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop) static void i2c_finish(struct sh_i2c *base) { writeb(0, &base->icsr); - writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr); + clrbits_8(&base->iccr, SH_I2C_ICCR_ICE); } static int i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val) From ff5d2dce1e8b24e9f4d85db3906c5d2e25b0cedf Mon Sep 17 00:00:00 2001 From: York Sun Date: Sun, 16 Sep 2012 08:02:30 +0000 Subject: [PATCH 10/11] common/i2c: Add i2c write command Add i2c write command to write data from memory to i2c devices. Signed-off-by: York Sun --- common/cmd_i2c.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 795814d88f..b59470e7f6 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -223,6 +223,54 @@ static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv return 0; } +static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + u_char chip; + uint devaddr, alen, length; + u_char *memaddr; + + if (argc != 5) + return cmd_usage(cmdtp); + + /* + * memaddr is the address where to store things in memory + */ + memaddr = (u_char *)simple_strtoul(argv[1], NULL, 16); + + /* + * I2C chip address + */ + chip = simple_strtoul(argv[2], NULL, 16); + + /* + * I2C data address within the chip. This can be 1 or + * 2 bytes long. Some day it might be 3 bytes long :-). + */ + devaddr = simple_strtoul(argv[3], NULL, 16); + alen = get_alen(argv[3]); + if (alen > 3) + return cmd_usage(cmdtp); + + /* + * Length is the number of objects, not number of bytes. + */ + length = simple_strtoul(argv[4], NULL, 16); + + while (length-- > 0) { + if (i2c_write(chip, devaddr++, alen, memaddr++, 1) != 0) { + puts("Error writing to the chip.\n"); + return 1; + } +/* + * No write delay with FRAM devices. + */ +#if !defined(CONFIG_SYS_I2C_FRAM) + udelay(11000); +#endif + } + return 0; +} + /* * Syntax: * i2c md {i2c_chip} {addr}{.0, .1, .2} {len} @@ -1282,6 +1330,7 @@ static cmd_tbl_t cmd_i2c_sub[] = { U_BOOT_CMD_MKENT(nm, 2, 1, do_i2c_nm, "", ""), U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""), U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""), + U_BOOT_CMD_MKENT(write, 5, 0, do_i2c_write, "", ""), U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""), #if defined(CONFIG_CMD_SDRAM) U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""), @@ -1333,6 +1382,7 @@ U_BOOT_CMD( "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n" "i2c probe - show devices on the I2C bus\n" "i2c read chip address[.0, .1, .2] length memaddress - read to memory \n" + "i2c write memaddress chip address[.0, .1, .2] length - write memory to i2c\n" "i2c reset - re-init the I2C Controller\n" #if defined(CONFIG_CMD_SDRAM) "i2c sdram chip - print SDRAM configuration information\n" From 54b99e51ab580eb6373f93994fe8f8a8edeefcf8 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Sun, 23 Sep 2012 10:12:56 +0000 Subject: [PATCH 11/11] i2c_probe: update for use in scripting Allow the use of an I2C address to test and return success if one or more devices is found. This allows device presence to alter the flow of a script. e.g. if i2c probe 0x04 ; then echo found Hannstar touch ; fi Signed-off-by: Eric Nelson --- common/cmd_i2c.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index b59470e7f6..82e63e1322 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -605,18 +605,28 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const arg /* * Syntax: - * i2c probe {addr}{.0, .1, .2} + * i2c probe {addr} + * + * Returns zero (success) if one or more I2C devices was found */ static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int j; + int addr = -1; + int found = 0; #if defined(CONFIG_SYS_I2C_NOPROBES) int k, skip; uchar bus = GET_BUS_NUM; #endif /* NOPROBES */ + if (argc == 2) + addr = simple_strtol(argv[1], 0, 16); + puts ("Valid chip addresses:"); for (j = 0; j < 128; j++) { + if ((0 <= addr) && (j != addr)) + continue; + #if defined(CONFIG_SYS_I2C_NOPROBES) skip = 0; for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) { @@ -628,8 +638,10 @@ static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv if (skip) continue; #endif - if (i2c_probe(j) == 0) + if (i2c_probe(j) == 0) { printf(" %02X", j); + found++; + } } putc ('\n'); @@ -642,7 +654,7 @@ static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv putc ('\n'); #endif - return 0; + return (0 == found); } /* @@ -1380,7 +1392,7 @@ U_BOOT_CMD( "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n" "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n" "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n" - "i2c probe - show devices on the I2C bus\n" + "i2c probe [address] - test for and show device(s) on the I2C bus\n" "i2c read chip address[.0, .1, .2] length memaddress - read to memory \n" "i2c write memaddress chip address[.0, .1, .2] length - write memory to i2c\n" "i2c reset - re-init the I2C Controller\n"