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iomux-v3: Add support for mx6sl LVE bit 

On mx6sl there is a LVE (Low Voltage Enable) bit in the IOMUXC_SW_PAD_CTL
register that can enable or disable low voltage on the pad.

LVE is bit 22 of IOMUXC_SW_PAD_CTL register, but in order to make the
calculation easier we can define it as a flag in bit 1, since this bit is unused.

Add support for it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Otavio Salvador <otavio@ossystems.com.br>
This commit is contained in:
Fabio Estevam 2014-04-29 10:15:46 -03:00 committed by Stefano Babic
parent 234d89dac6
commit 98d2cffd23
2 changed files with 13 additions and 0 deletions
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8
arch/arm/imx-common/iomux-v3.c
View File

@ -30,6 +30,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
#if defined CONFIG_MX6SL
/* Check whether LVE bit needs to be set */
if (pad_ctrl & PAD_CTL_LVE) {
pad_ctrl &= ~PAD_CTL_LVE;
pad_ctrl |= PAD_CTL_LVE_BIT;
}
#endif
if (mux_ctrl_ofs)
__raw_writel(mux_mode, base + mux_ctrl_ofs);

5
arch/arm/include/asm/imx-common/iomux-v3.h
View File

@ -111,6 +111,11 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_CTL_DSE_40ohm (6 << 3)
#define PAD_CTL_DSE_34ohm (7 << 3)
#if defined CONFIG_MX6SL
#define PAD_CTL_LVE (1 << 1)
#define PAD_CTL_LVE_BIT (1 << 22)
#endif
#elif defined(CONFIG_VF610)
#define PAD_MUX_MODE_SHIFT 20