powerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2
Corenet based SoCs have different core clocks starting from Chassis generation 2. Cores are organized into clusters. Each cluster has up to 4 cores sharing same clock, which can be chosen from one of three PLLs in the cluster group with one of the devisors /1, /2 or /4. Two clusters are put together as a cluster group. These two clusters share the PLLs but may have different divisor. For example, core 0~3 are in cluster 1. Core 4~7 are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2 are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1. PME and FMan blocks can take different PLLs, configured by RCW. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
York Sun
Andy Fleming
parent
2f1712b275
commit
9a653a9810
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@ -76,8 +76,8 @@ void get_sys_info (sys_info_t * sysInfo)
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[13] = 2, /* CC4 PPL / 2 */
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[14] = 4, /* CC4 PPL / 4 */
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};
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uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
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uint ratio[4];
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uint i, freqCC_PLL[6], rcw_tmp;
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uint ratio[6];
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unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
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uint mem_pll_rat;
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@ -97,13 +97,132 @@ void get_sys_info (sys_info_t * sysInfo)
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ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
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ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
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ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
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for (i = 0; i < 4; i++) {
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ratio[4] = (in_be32(&clk->pllc5gsr) >> 1) & 0x3f;
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ratio[5] = (in_be32(&clk->pllc6gsr) >> 1) & 0x3f;
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for (i = 0; i < 6; i++) {
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if (ratio[i] > 4)
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freqCC_PLL[i] = sysclk * ratio[i];
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else
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freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
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}
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rcw_tmp = in_be32(&gur->rcwsr[3]);
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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/*
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* Each cluster has up to 4 cores, sharing the same PLL selection.
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* The cluster assignment is fixed per SoC. There is no way identify the
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* assignment so far, presuming the "first configuration" which is to
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* fill the lower cluster group first before moving up to next group.
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* PLL1, PLL2, PLL3 are cluster group A, feeding core 0~3 on cluster 1
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* and core 4~7 on cluster 2
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* PLL4, PLL5, PLL6 are cluster group B, feeding core 8~11 on cluster 3
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* and core 12~15 on cluster 4 if existing
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*/
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for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
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u32 c_pll_sel = (in_be32(&clk->clkc0csr + (cpu / 4) * 8) >> 27)
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& 0xf;
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u32 cplx_pll = core_cplx_PLL[c_pll_sel];
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if (cplx_pll > 3)
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printf("Unsupported architecture configuration"
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" in function %s\n", __func__);
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cplx_pll += (cpu / 8) * 3;
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sysInfo->freqProcessor[cpu] =
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freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
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}
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#define PME_CLK_SEL 0xe0000000
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#define PME_CLK_SHIFT 29
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#define FM1_CLK_SEL 0x1c000000
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#define FM1_CLK_SHIFT 26
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rcw_tmp = in_be32(&gur->rcwsr[7]);
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#ifdef CONFIG_SYS_DPAA_PME
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switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
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case 1:
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sysInfo->freqPME = freqCC_PLL[0];
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break;
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case 2:
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sysInfo->freqPME = freqCC_PLL[0] / 2;
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break;
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case 3:
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sysInfo->freqPME = freqCC_PLL[0] / 3;
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break;
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case 4:
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sysInfo->freqPME = freqCC_PLL[0] / 4;
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break;
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case 6:
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sysInfo->freqPME = freqCC_PLL[1] / 2;
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break;
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case 7:
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sysInfo->freqPME = freqCC_PLL[1] / 3;
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break;
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default:
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printf("Error: Unknown PME clock select!\n");
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case 0:
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sysInfo->freqPME = sysInfo->freqSystemBus / 2;
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break;
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}
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#endif
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#ifdef CONFIG_SYS_DPAA_FMAN
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switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
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case 1:
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sysInfo->freqFMan[0] = freqCC_PLL[3];
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break;
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case 2:
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sysInfo->freqFMan[0] = freqCC_PLL[3] / 2;
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break;
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case 3:
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sysInfo->freqFMan[0] = freqCC_PLL[3] / 3;
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break;
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case 4:
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sysInfo->freqFMan[0] = freqCC_PLL[3] / 4;
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break;
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case 6:
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sysInfo->freqFMan[0] = freqCC_PLL[4] / 2;
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break;
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case 7:
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sysInfo->freqFMan[0] = freqCC_PLL[4] / 3;
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break;
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default:
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printf("Error: Unknown FMan1 clock select!\n");
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case 0:
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sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
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break;
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}
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#if (CONFIG_SYS_NUM_FMAN) == 2
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#define FM2_CLK_SEL 0x00000038
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#define FM2_CLK_SHIFT 3
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rcw_tmp = in_be32(&gur->rcwsr[15]);
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switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
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case 1:
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sysInfo->freqFMan[1] = freqCC_PLL[4];
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break;
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case 2:
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sysInfo->freqFMan[1] = freqCC_PLL[4] / 2;
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break;
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case 3:
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sysInfo->freqFMan[1] = freqCC_PLL[4] / 3;
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break;
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case 4:
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sysInfo->freqFMan[1] = freqCC_PLL[4] / 4;
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break;
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case 6:
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sysInfo->freqFMan[1] = freqCC_PLL[3] / 2;
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break;
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case 7:
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sysInfo->freqFMan[1] = freqCC_PLL[3] / 3;
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break;
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default:
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printf("Error: Unknown FMan2 clock select!\n");
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case 0:
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sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
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break;
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}
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#endif /* CONFIG_SYS_NUM_FMAN == 2 */
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#endif /* CONFIG_SYS_DPAA_FMAN */
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#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
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for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
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u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
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u32 cplx_pll = core_cplx_PLL[c_pll_sel];
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@ -111,7 +230,6 @@ void get_sys_info (sys_info_t * sysInfo)
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sysInfo->freqProcessor[cpu] =
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freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
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}
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#define PME_CLK_SEL 0x80000000
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#define FM1_CLK_SEL 0x40000000
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#define FM2_CLK_SEL 0x20000000
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@ -159,11 +277,10 @@ void get_sys_info (sys_info_t * sysInfo)
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#endif
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#endif
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#else
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uint plat_ratio,e500_ratio,half_freqSystemBus;
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#if defined(CONFIG_FSL_LBC)
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uint lcrr_div;
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#endif
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#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
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#else /* CONFIG_FSL_CORENET */
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uint plat_ratio, e500_ratio, half_freqSystemBus;
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int i;
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#ifdef CONFIG_QE
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__maybe_unused u32 qe_ratio;
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@ -210,6 +327,7 @@ void get_sys_info (sys_info_t * sysInfo)
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#endif /* CONFIG_FSL_CORENET */
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#if defined(CONFIG_FSL_LBC)
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uint lcrr_div;
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#if defined(CONFIG_SYS_LBC_LCRR)
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/* We will program LCRR to this value later */
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lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
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@ -1899,34 +1899,38 @@ typedef struct ccsr_gur {
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#define rmuliodnr rio1maintliodnr
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typedef struct ccsr_clk {
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u32 clkc0csr; /* Core 0 Clock control/status */
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u32 clkc0csr; /* 0x000 Core 0 Clock control/status */
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u8 res1[0x1c];
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u32 clkc1csr; /* Core 1 Clock control/status */
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u32 clkc1csr; /* 0x020 Core 1 Clock control/status */
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u8 res2[0x1c];
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u32 clkc2csr; /* Core 2 Clock control/status */
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u32 clkc2csr; /* 0x040 Core 2 Clock control/status */
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u8 res3[0x1c];
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u32 clkc3csr; /* Core 3 Clock control/status */
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u32 clkc3csr; /* 0x060 Core 3 Clock control/status */
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u8 res4[0x1c];
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u32 clkc4csr; /* Core 4 Clock control/status */
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u32 clkc4csr; /* 0x080 Core 4 Clock control/status */
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u8 res5[0x1c];
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u32 clkc5csr; /* Core 5 Clock control/status */
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u32 clkc5csr; /* 0x0a0 Core 5 Clock control/status */
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u8 res6[0x1c];
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u32 clkc6csr; /* Core 6 Clock control/status */
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u32 clkc6csr; /* 0x0c0 Core 6 Clock control/status */
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u8 res7[0x1c];
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u32 clkc7csr; /* Core 7 Clock control/status */
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u32 clkc7csr; /* 0x0e0 Core 7 Clock control/status */
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u8 res8[0x71c];
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u32 pllc1gsr; /* Cluster PLL 1 General Status */
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u32 pllc1gsr; /* 0x800 Cluster PLL 1 General Status */
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u8 res10[0x1c];
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u32 pllc2gsr; /* Cluster PLL 2 General Status */
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u32 pllc2gsr; /* 0x820 Cluster PLL 2 General Status */
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u8 res11[0x1c];
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u32 pllc3gsr; /* Cluster PLL 3 General Status */
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u32 pllc3gsr; /* 0x840 Cluster PLL 3 General Status */
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u8 res12[0x1c];
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u32 pllc4gsr; /* Cluster PLL 4 General Status */
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u8 res13[0x39c];
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u32 pllpgsr; /* Platform PLL General Status */
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u32 pllc4gsr; /* 0x860 Cluster PLL 4 General Status */
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u8 res13[0x1c];
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u32 pllc5gsr; /* 0x880 Cluster PLL 5 General Status */
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u8 res14[0x1c];
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u32 plldgsr; /* DDR PLL General Status */
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u8 res15[0x3dc];
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u32 pllc6gsr; /* 0x8a0 Cluster PLL 6 General Status */
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u8 res15[0x35c];
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u32 pllpgsr; /* 0xc00 Platform PLL General Status */
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u8 res16[0x1c];
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u32 plldgsr; /* 0xc20 DDR PLL General Status */
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u8 res17[0x3dc];
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} ccsr_clk_t;
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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