cpu/ppc4xx/start.S : exceptions are enabled after relocation
Patch by Cedric Vincent, 6 June 2005
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@ -2,6 +2,9 @@
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Changes since U-Boot 1.1.4:
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Changes since U-Boot 1.1.4:
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======================================================================
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======================================================================
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* cpu/ppc4xx/start.S : exceptions are enabled after relocation
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Patch by Cedric Vincent, 6 June 2005
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* au1x00_eth.c: check malloc return value and abort if it failed
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* au1x00_eth.c: check malloc return value and abort if it failed
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Patch by Andrew Dyer, 26 Jul 2005
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Patch by Andrew Dyer, 26 Jul 2005
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@ -340,23 +340,6 @@ _start:
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mtspr tcr,r0 /* disable all */
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mtspr tcr,r0 /* disable all */
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mtspr esr,r0 /* clear exception syndrome register */
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mtspr esr,r0 /* clear exception syndrome register */
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mtxer r0 /* clear integer exception register */
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mtxer r0 /* clear integer exception register */
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#if !defined(CONFIG_440GX)
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lis r1,0x0002 /* set CE bit (Critical Exceptions) */
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ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */
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mtmsr r1 /* change MSR */
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#elif !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
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bl __440gx_msr_set
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b __440gx_msr_continue
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__440gx_msr_set:
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lis r1, 0x0002 /* set CE bit (Critical Exceptions) */
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ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */
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mtspr srr1,r1
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mflr r1
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mtspr srr0,r1
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rfi
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__440gx_msr_continue:
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#endif
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/*----------------------------------------------------------------*/
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/*----------------------------------------------------------------*/
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/* Debug setup -- some (not very good) ice's need an event*/
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/* Debug setup -- some (not very good) ice's need an event*/
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@ -458,9 +441,6 @@ __440gx_msr_continue:
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mtspr esr,r0 /* clear Exception Syndrome Reg */
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mtspr esr,r0 /* clear Exception Syndrome Reg */
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mttcr r0 /* timer control register */
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mttcr r0 /* timer control register */
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mtexier r0 /* disable all interrupts */
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mtexier r0 /* disable all interrupts */
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addi r4,r0,0x1000 /* set ME bit (Machine Exceptions) */
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oris r4,r4,0x2 /* set CE bit (Critical Exceptions) */
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mtmsr r4 /* change MSR */
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addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
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addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
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ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
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ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
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mtdbsr r4 /* clear/reset the dbsr */
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mtdbsr r4 /* clear/reset the dbsr */
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@ -571,9 +551,6 @@ __440gx_msr_continue:
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mttcr r4 /* clear Timer Control Reg */
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mttcr r4 /* clear Timer Control Reg */
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mtxer r4 /* clear Fixed-Point Exception Reg */
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mtxer r4 /* clear Fixed-Point Exception Reg */
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mtevpr r4 /* clear Exception Vector Prefix Reg */
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mtevpr r4 /* clear Exception Vector Prefix Reg */
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addi r4,r0,0x1000 /* set ME bit (Machine Exceptions) */
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oris r4,r4,0x0002 /* set CE bit (Critical Exceptions) */
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mtmsr r4 /* change MSR */
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addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
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addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
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/* dbsr is cleared by setting bits to 1) */
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/* dbsr is cleared by setting bits to 1) */
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mtdbsr r4 /* clear/reset the dbsr */
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mtdbsr r4 /* clear/reset the dbsr */
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@ -1428,6 +1405,24 @@ trap_init:
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cmplw 0, r7, r8
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cmplw 0, r7, r8
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blt 4b
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blt 4b
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#if !defined(CONFIG_440_GX)
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addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
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oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
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mtmsr r7 /* change MSR */
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#else
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bl __440gx_msr_set
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b __440gx_msr_continue
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__440gx_msr_set:
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addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
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oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
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mtspr srr1,r7
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mflr r7
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mtspr srr0,r7
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rfi
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__440gx_msr_continue:
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#endif
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mtlr r4 /* restore link register */
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mtlr r4 /* restore link register */
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blr
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blr
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