sysmo-bts
/
u-boot
9
0
Fork 0
Code Pull Requests Releases Activity

Change ML401 parameters - Xilinx BSP

This commit is contained in:
Michal Simek 2007-04-21 20:53:31 +02:00
parent 342cd097be
commit 9d1d6a34d2
2 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
board/xilinx/ml401/config.mk
View File

@ -25,7 +25,7 @@
# Version: Xilinx EDK 6.3 EDK_Gmm.12.3 # Version: Xilinx EDK 6.3 EDK_Gmm.12.3
# #
TEXT_BASE = 0x12000000 TEXT_BASE = 0x29000000
PLATFORM_CPPFLAGS += -mno-xl-soft-mul PLATFORM_CPPFLAGS += -mno-xl-soft-mul
PLATFORM_CPPFLAGS += -mno-xl-soft-div PLATFORM_CPPFLAGS += -mno-xl-soft-div

24
board/xilinx/ml401/xparameters.h
View File

@ -27,41 +27,41 @@
*/ */
/* System Clock Frequency */ /* System Clock Frequency */
#define XILINX_CLOCK_FREQ 66666667 #define XILINX_CLOCK_FREQ 100000000
/* Interrupt controller is intc_0 */ /* Interrupt controller is intc_0 */
#define XILINX_INTC_BASEADDR 0xd1000fc0 #define XILINX_INTC_BASEADDR 0x41200000
#define XILINX_INTC_NUM_INTR_INPUTS 12 #define XILINX_INTC_NUM_INTR_INPUTS 4
/* Timer pheriphery is opb_timer_0 */ /* Timer pheriphery is opb_timer_0 */
#define XILINX_TIMER_BASEADDR 0xa2000000 #define XILINX_TIMER_BASEADDR 0x41c00000
#define XILINX_TIMER_IRQ 0 #define XILINX_TIMER_IRQ 0
/* Uart pheriphery is console_uart */ /* Uart pheriphery is console_uart */
#define XILINX_UART_BASEADDR 0xa0000000 #define XILINX_UART_BASEADDR 0x40600000
#define XILINX_UART_BAUDRATE 115200 #define XILINX_UART_BAUDRATE 115200
/* GPIO is opb_gpio_0*/ /* GPIO is opb_gpio_0*/
#define XILINX_GPIO_BASEADDR 0x90000000 #define XILINX_GPIO_BASEADDR 0x90000000
/* Flash Memory is opb_emc_0 */ /* Flash Memory is opb_emc_0 */
#define XILINX_FLASH_START 0x28000000 #define XILINX_FLASH_START 0x2c000000
#define XILINX_FLASH_SIZE 0x00800000 #define XILINX_FLASH_SIZE 0x00800000
/* Main Memory is plb_ddr_0 */ /* Main Memory is plb_ddr_0 */
#define XILINX_RAM_START 0x10000000 #define XILINX_RAM_START 0x28000000
#define XILINX_RAM_SIZE 0x10000000 #define XILINX_RAM_SIZE 0x04000000
/* Sysace Controller is opb_sysace_0 */ /* Sysace Controller is opb_sysace_0 */
#define XILINX_SYSACE_BASEADDR 0xCF000000 #define XILINX_SYSACE_BASEADDR 0x41800000
#define XILINX_SYSACE_HIGHADDR 0xCF0001FF #define XILINX_SYSACE_HIGHADDR 0x4180FFFF
#define XILINX_SYSACE_MEM_WIDTH 16 #define XILINX_SYSACE_MEM_WIDTH 16
/* Ethernet controller is opb_ethernet_0 */ /* Ethernet controller is opb_ethernet_0 */
#define XPAR_XEMAC_NUM_INSTANCES 1 #define XPAR_XEMAC_NUM_INSTANCES 1
#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0 #define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000 #define XPAR_OPB_ETHERNET_0_BASEADDR 0x40c00000
#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF #define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0fFFF
#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1 #define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1 #define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
#define XPAR_OPB_ETHERNET_0_MII_EXIST 1 #define XPAR_OPB_ETHERNET_0_MII_EXIST 1