mtd: nand: omap: add CONFIG_SPL_NAND_DEVICE_WIDTH to determine NAND device bus-width
This patch adds CONFIG_SPL_NAND_DEVICE_WIDTH to specify bus-width of NAND device CONFIG_SPL_NAND_DEVICE_WIDTH == 16: NAND device with x16 bus-width CONFIG_SPL_NAND_DEVICE_WIDTH == 8: NAND device with x8 bus-width Need for a separate CONFIG_xx arise from following situations. (1) SPL NAND drivers does not have framework to parse ONFI parameter page. (2) if !defined(CONFIG_SYS_NAND_SELF_INIT) |- board_nand_init() |- nand_scan() |- nand_scan_ident() |- nand_scan_tail() This means board_nand_init() is called before nand_scan_ident(). So NAND controller is initialized before the actual probing of NAND device. However some controller (like GPMC) need to be specifically configured for bus-width of NAND device. In such cases, bus-width of the NAND device should be known in advance of actual device probing. Hence, CONFIG_SPL_NAND_DEVICE_WIDTH is useful. (3) Non-ONFI compliant devices need some mechanism to specify device bus-width to driver. Signed-off-by: Pekon Gupta <pekon@ti.com>
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@ -180,6 +180,15 @@ Configuration Options:
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This is used by SoC platforms which do not have built-in ELM
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hardware engine required for BCH ECC correction.
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CONFIG_SPL_NAND_DEVICE_WIDTH
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Specifies bus-width of the default NAND device connected to SoC.
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This config is useful for driver which cannot self initialize or
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parse ONFI parameter (like SPL drivers), or for supporting non-ONFI
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compliant devices.
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This config can take following values:
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- 8: x8 NAND devices is connected
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- 16: x16 NAND device is connected
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Platform specific options
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=========================
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@ -856,13 +856,19 @@ int board_nand_init(struct nand_chip *nand)
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nand->priv = &bch_priv;
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nand->cmd_ctrl = omap_nand_hwcontrol;
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nand->options |= NAND_NO_PADDING | NAND_CACHEPRG;
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/* If we are 16 bit dev, our gpmc config tells us that */
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if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000)
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nand->options |= NAND_BUSWIDTH_16;
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nand->chip_delay = 100;
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nand->ecc.layout = &omap_ecclayout;
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/* configure driver and controller based on NAND device bus-width */
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gpmc_config = readl(&gpmc_cfg->cs[cs].config1);
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if (CONFIG_SPL_NAND_DEVICE_WIDTH == 16) {
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nand->options |= NAND_BUSWIDTH_16;
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writel(gpmc_config | (0x1 << 12), &gpmc_cfg->cs[cs].config1);
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} else {
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nand->options &= ~NAND_BUSWIDTH_16;
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writel(gpmc_config & ~(0x1 << 12), &gpmc_cfg->cs[cs].config1);
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}
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/* select ECC scheme */
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#if defined(CONFIG_NAND_OMAP_ECCSCHEME)
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err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,
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@ -206,6 +206,7 @@
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SPL_NAND_DEVICE_WIDTH 8
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
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CONFIG_SYS_NAND_PAGE_SIZE)
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@ -335,6 +335,7 @@
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SPL_NAND_DEVICE_WIDTH 16
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
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10, 11, 12, 13}
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@ -329,6 +329,7 @@
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SPL_NAND_DEVICE_WIDTH 8
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
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10, 11, 12, 13}
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@ -211,6 +211,7 @@
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#define CONFIG_SYS_NAND_PAGE_SIZE 4096
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#define CONFIG_SYS_NAND_OOBSIZE 224
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#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
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#define CONFIG_SPL_NAND_DEVICE_WIDTH 8
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
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CONFIG_SYS_NAND_PAGE_SIZE)
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@ -166,6 +166,7 @@
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/* CS0 */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
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/* devices */
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#define CONFIG_SPL_NAND_DEVICE_WIDTH 8
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/* Environment information */
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#define CONFIG_BOOTDELAY 10
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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@ -320,6 +320,7 @@
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SPL_NAND_DEVICE_WIDTH 16
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
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10, 11, 12, 13}
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@ -143,6 +143,7 @@
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#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
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/* to access nand at */
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/* CS0 */
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#define CONFIG_SPL_NAND_DEVICE_WIDTH 16
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
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#if defined(CONFIG_CMD_NET)
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@ -103,6 +103,7 @@
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SPL_NAND_DEVICE_WIDTH 16
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/* NAND: driver related configs */
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#define CONFIG_NAND_OMAP_GPMC
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#define CONFIG_NAND_OMAP_ELM
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@ -253,6 +253,7 @@
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SPL_NAND_DEVICE_WIDTH 8
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
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10, 11, 12, 13, 14, 15, 16, 17, \
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@ -357,6 +357,7 @@
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SPL_NAND_DEVICE_WIDTH 8
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
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10, 11, 12, 13}
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@ -387,6 +387,7 @@
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SPL_NAND_DEVICE_WIDTH 8
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
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@ -426,6 +426,7 @@
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SPL_NAND_DEVICE_WIDTH 16
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
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10, 11, 12, 13}
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@ -122,7 +122,7 @@
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/* Max number of NAND devices */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SPL_NAND_DEVICE_WIDTH 16
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/* Timeout values (in ticks) */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
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#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
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@ -298,6 +298,7 @@
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#if defined(CONFIG_CMD_NAND)
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#define CONFIG_NAND_OMAP_GPMC
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#define CONFIG_SPL_NAND_DEVICE_WIDTH 16
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
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#endif
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@ -319,6 +319,7 @@
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SPL_NAND_DEVICE_WIDTH 16
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
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10, 11, 12, 13}
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@ -133,7 +133,7 @@
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/* at CS0 */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
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/* devices */
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#define CONFIG_SPL_NAND_DEVICE_WIDTH 8
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_MTD_PARTITIONS
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@ -140,6 +140,7 @@
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/* CS0 */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
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/* devices */
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#define CONFIG_SPL_NAND_DEVICE_WIDTH 16
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#define CONFIG_JFFS2_NAND
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/* nand device jffs2 lives on */
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#define CONFIG_JFFS2_DEV "nand0"
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@ -159,6 +159,7 @@
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/* to access nand at */
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/* CS0 */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SPL_NAND_DEVICE_WIDTH 16
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/* Environment information */
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#define CONFIG_BOOTDELAY 10
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@ -187,6 +187,7 @@
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SPL_NAND_DEVICE_WIDTH 8
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
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10, 11, 12, 13, 14, 15, 16, 17, \
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@ -254,6 +254,7 @@
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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#define CONFIG_SPL_NAND_DEVICE_WIDTH 16
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
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@ -286,6 +286,7 @@
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SPL_NAND_DEVICE_WIDTH 8
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SYS_NAND_ECCPOS {12, 13, 14, 15, 16, 17, 18, 19, 20,\
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21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\
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