ppc4xx: Coding style cleanup
Wrap long lines etc. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Matthias Fuchs
Stefan Roese
parent
17e65c21ad
commit
9ec367aa2c
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@ -57,7 +57,7 @@
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
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#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
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#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */
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#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
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@ -168,11 +168,10 @@
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#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
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/*-----------------------------------------------------------------------
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/*
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* NAND-FLASH stuff
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*-----------------------------------------------------------------------
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*/
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#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
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#define CFG_NAND_BASE_LIST {CFG_NAND_BASE}
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#define NAND_MAX_CHIPS 1
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#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define NAND_BIG_DELAY_US 25
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@ -185,9 +184,8 @@
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#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
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#define CFG_NAND_QUIET 1
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/*-----------------------------------------------------------------------
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/*
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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@ -212,55 +210,56 @@
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#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
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#define CFG_PCI_PTM2PCI 0x08000000 /* Host: use this pci address */
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/*-----------------------------------------------------------------------
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/*
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* IDE/ATA stuff
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*-----------------------------------------------------------------------
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*/
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#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
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#undef CONFIG_IDE_LED /* no led for ide supported */
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#define CONFIG_IDE_RESET 1 /* reset for ide supported */
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#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
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#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
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/* max. 1 drives per IDE bus */
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#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1)
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#define CFG_ATA_BASE_ADDR 0xF0100000
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#define CFG_ATA_IDE0_OFFSET 0x0000
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#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
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#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
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#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
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#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
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#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register access */
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#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* FLASH organization
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*/
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#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
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#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
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#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
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#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
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#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
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#define CFG_FLASH_ADDR0 0x5555 /* 1st addr for flash config cycles */
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#define CFG_FLASH_ADDR1 0x2AAA /* 2nd addr for flash config cycles */
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/*
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* The following defines are added for buggy IOP480 byte interface.
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* All other boards should use the standard values (CPCI405 etc.)
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*/
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#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
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#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
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#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
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#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
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#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
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#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
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/*-----------------------------------------------------------------------
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/*
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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@ -268,76 +267,73 @@
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0xFFFA0000
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 256 kB for Monitor */
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#define CFG_MALLOC_LEN (384 * 1024) /* Reserve 256 kB for malloc() */
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#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384kB for Monitor */
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#define CFG_MALLOC_LEN (384 * 1024) /* Reserve 384kB for malloc() */
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#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
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# define CFG_RAMBOOT 1
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#else
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# undef CFG_RAMBOOT
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#endif
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/*-----------------------------------------------------------------------
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/*
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* Environment Variable setup
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*/
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#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
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#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
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#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
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/* total size of a CAT24WC16 is 2048 bytes */
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#define CFG_ENV_OFFSET 0x100 /* reseve 0x100 bytes for strapping */
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#define CFG_ENV_SIZE 0x700
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/*-----------------------------------------------------------------------
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* I2C EEPROM (CAT24WC16) for environment
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/*
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* I2C EEPROM (24WC16) for environment
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*/
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#define CONFIG_HARD_I2C /* I2c with hardware support */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
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#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM 24WC16 */
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#define CFG_EEPROM_WREN 1
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/* CAT24WC08/16... */
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/* 24WC16 */
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#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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/* mask of address bits that overflow into the "EEPROM chip address" */
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/* mask of address bits that overflow into the "EEPROM chip address" */
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#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
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#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
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/* 16 byte page write mode using*/
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/* last 4 bits of the address */
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#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The 24WC16 has */
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/* 16 byte page write mode using */
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/* last 4 bits of the address */
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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#define CFG_EEPROM_PAGE_WRITE_ENABLE
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/*-----------------------------------------------------------------------
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/*
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* External Bus Controller (EBC) Setup
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*/
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#define CAN_BA 0xF0000000 /* CAN Base Address */
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#define DUART0_BA 0xF0000400 /* DUART Base Address */
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#define DUART1_BA 0xF0000408 /* DUART Base Address */
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#define RTC_BA 0xF0000500 /* RTC Base Address */
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#define VGA_BA 0xF1000000 /* Epson VGA Base Address */
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#define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
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#define CAN_BA 0xF0000000 /* CAN Base Address */
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#define DUART0_BA 0xF0000400 /* DUART Base Address */
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#define DUART1_BA 0xF0000408 /* DUART Base Address */
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#define RTC_BA 0xF0000500 /* RTC Base Address */
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#define VGA_BA 0xF1000000 /* Epson VGA Base Address */
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#define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
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/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
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/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
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/* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
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#define CFG_EBC_PB0AP 0x92015480
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/*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
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#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
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/* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
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#define CFG_EBC_PB0CR 0xFFC5A000
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/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
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/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
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#define CFG_EBC_PB1AP 0x92015480
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#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
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/* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
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#define CFG_EBC_PB1CR 0xF4018000
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/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
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#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
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#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
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/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
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/* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
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#define CFG_EBC_PB2AP 0x010053C0
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/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
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#define CFG_EBC_PB2CR 0xF0018000
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/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
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#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
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#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
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/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
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/* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
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#define CFG_EBC_PB3AP 0x010053C0
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/* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
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#define CFG_EBC_PB3CR 0xF011A000
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/*-----------------------------------------------------------------------
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/*
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* FPGA stuff
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*/
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#define CFG_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
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#define CFG_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
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/* FPGA internal regs */
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#define CFG_FPGA_CTRL 0x000
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@ -347,17 +343,17 @@
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#define CFG_FPGA_CTRL_WDI 0x0002
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#define CFG_FPGA_CTRL_PS2_RESET 0x0020
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#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
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#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
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#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
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/* FPGA program pin configuration */
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#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
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#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
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#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
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#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
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#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
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#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
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#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
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#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
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#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
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/*-----------------------------------------------------------------------
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/*
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* Definitions for initial stack pointer and data area (in data cache)
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*/
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/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
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@ -366,14 +362,14 @@
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/* On Chip Memory location */
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#define CFG_OCM_DATA_ADDR 0xF8000000
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#define CFG_OCM_DATA_SIZE 0x1000
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#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
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#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
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#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
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#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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/*
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* Definitions for GPIO setup (PPC405EP specific)
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*
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* GPIO0[0] - External Bus Controller BLAST output
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@ -401,11 +397,11 @@
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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/*
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* Default speed selection (cpu_plb_opb_ebc) in mhz.
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* Default speed selection (cpu_plb_opb_ebc) in MHz.
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* This value will be set if iic boot eprom is disabled.
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*/
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#if 1
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