From 2ee93246bd9efc928d4cced0f3e94be5365de892 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Majewski?= Date: Wed, 9 Apr 2014 10:44:33 +0200 Subject: [PATCH 01/12] trats2: config: fix: Set default console to ttySAC2 During providing device tree support for Exynos4 based boards, a tiny mistake has creeped in the 1ecab0f commit. This commit restores proper setting of default console for the trats2 board. Signed-off-by: Lukasz Majewski Signed-off-by: Minkyu Kang --- include/configs/trats2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 53d449c291..50d529b132 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -52,7 +52,7 @@ #define CONFIG_BOOTARGS "Please use defined boot" #define CONFIG_BOOTCOMMAND "run mmcboot" -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - GENERATED_GBL_DATA_SIZE) From 6afc3f6e118bd7a59741261c73613625f575482f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Majewski?= Date: Wed, 9 Apr 2014 10:44:34 +0200 Subject: [PATCH 02/12] trats: config: fix: Set default console to ttySAC2 During providing device tree support for Exynos4 based boards, a tiny mistake has creeped in the fe60164 commit. This commit restores proper setting of default console for the trats board. Signed-off-by: Lukasz Majewski Signed-off-by: Minkyu Kang --- include/configs/trats.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/trats.h b/include/configs/trats.h index 5d8bd60583..1b74adbc17 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -59,7 +59,7 @@ #define CONFIG_BOOTARGS "Please use defined boot" #define CONFIG_BOOTCOMMAND "run mmcboot" -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - GENERATED_GBL_DATA_SIZE) From 188c42b33557787128f50e3a5a751747f58dd68f Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Wed, 30 Apr 2014 09:09:15 +0900 Subject: [PATCH 03/12] ARM: exynos: remove the unused code "mmc boot" command didn't use anywhere. It can be replace "mmc dev" command. Signed-off-by: Jaehoon Chung Signed-off-by: Minkyu Kang --- include/configs/s5pc210_universal.h | 7 ++----- include/configs/trats.h | 7 ++----- include/configs/trats2.h | 11 +++-------- 3 files changed, 7 insertions(+), 18 deletions(-) diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 2da887109d..db5561ab8c 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -111,12 +111,9 @@ "onenand write 0x41008000 0xc00000 0x500000\0" \ "bootk=" \ "run loaduimage; bootm 0x40007FC0\0" \ - "updatemmc=" \ - "mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \ - "mmc boot 0 1 1 0\0" \ "updatebackup=" \ - "mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \ - "mmc boot 0 1 1 0\0" \ + "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \ + "mmc dev 0 0\0" \ "updatebootb=" \ "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \ "lpj=lpj=3981312\0" \ diff --git a/include/configs/trats.h b/include/configs/trats.h index 1b74adbc17..815948bbff 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -121,12 +121,9 @@ "bootm 0x40007FC0 - ${fdtaddr};" \ "fi;" \ "bootm 0x40007FC0;\0" \ - "updatemmc=" \ - "mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \ - "mmc boot 0 1 1 0\0" \ "updatebackup=" \ - "mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \ - "mmc boot 0 1 1 0\0" \ + "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \ + "mmc dev 0 0\0" \ "updatebootb=" \ "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \ "lpj=lpj=3981312\0" \ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 50d529b132..30a4b8cd8d 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -111,16 +111,11 @@ "bootm 0x40007FC0 - ${fdtaddr};" \ "fi;" \ "bootm 0x40007FC0;\0" \ - "updatemmc=" \ - "mmc boot 0 1 1 1; mmc write 0x42008000 0 0x200;" \ - "mmc boot 0 1 1 0\0" \ "updatebackup=" \ - "mmc boot 0 1 1 2; mmc write 0x42100000 0 0x200;" \ - " mmc boot 0 1 1 0\0" \ + "mmc dev 0 2; mmc write 0x51000000 0 0x800;" \ + " mmc dev 0 0\0" \ "updatebootb=" \ - "mmc read 0x51000000 0x80 0x200; run updatebackup\0" \ - "updateuboot=" \ - "mmc write 0x50000000 0x80 0x400\0" \ + "mmc read 0x51000000 0x80 0x800; run updatebackup\0" \ "mmcboot=" \ "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ From e6bfe79f31a042cfbd2dd9ee159cdd1209535727 Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Wed, 30 Apr 2014 13:28:06 +0200 Subject: [PATCH 04/12] samsung: misc: allows using environmental macros as args in menu commands Function cmd_process() runs commands with directly given list of arguments but it doesn't expand given environmental variables names as macros. Command "gpt" as one of arguments expects expanded macro e.g. $partitions so it needs to be called by function run_command(). Changes: - extend array mode_name by lower case commands names - used by find_cmd() - put each command arguments into one string - used by run_command() - use run_command() instead of cmd_process() Signed-off-by: Przemyslaw Marczak Cc: Minkyu Kang Signed-off-by: Minkyu Kang --- board/samsung/common/misc.c | 49 +++++++++++++++++-------------------- 1 file changed, 22 insertions(+), 27 deletions(-) diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index 3ff4289780..95d1758f7a 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -116,12 +116,12 @@ static int check_keys(void) * 4 BOOT_MODE_EXIT */ static char * -mode_name[BOOT_MODE_EXIT + 1] = { - "DEVICE", - "THOR", - "UMS", - "DFU", - "EXIT" +mode_name[BOOT_MODE_EXIT + 1][2] = { + {"DEVICE", ""}, + {"THOR", "thor"}, + {"UMS", "ums"}, + {"DFU", "dfu"}, + {"EXIT", ""}, }; static char * @@ -133,15 +133,13 @@ mode_info[BOOT_MODE_EXIT + 1] = { "and run normal boot" }; -#define MODE_CMD_ARGC 4 - static char * -mode_cmd[BOOT_MODE_EXIT + 1][MODE_CMD_ARGC] = { - {"", "", "", ""}, - {"thor", "0", "mmc", "0"}, - {"ums", "0", "mmc", "0"}, - {"dfu", "0", "mmc", "0"}, - {"", "", "", ""}, +mode_cmd[BOOT_MODE_EXIT + 1] = { + "", + "thor 0 mmc 0", + "ums 0 mmc 0", + "dfu 0 mmc 0", + "", }; static void display_board_info(void) @@ -182,11 +180,10 @@ static void display_board_info(void) static int mode_leave_menu(int mode) { char *exit_option; - char *exit_boot = "boot"; + char *exit_reset = "reset"; char *exit_back = "back"; cmd_tbl_t *cmd; int cmd_result; - int cmd_repeatable; int leave; lcd_clear(); @@ -200,31 +197,29 @@ static int mode_leave_menu(int mode) leave = 0; break; default: - cmd = find_cmd(mode_cmd[mode][0]); + cmd = find_cmd(mode_name[mode][1]); if (cmd) { - printf("Enter: %s %s\n", mode_name[mode], + printf("Enter: %s %s\n", mode_name[mode][0], mode_info[mode]); - lcd_printf("\n\n\t%s %s\n", mode_name[mode], + lcd_printf("\n\n\t%s %s\n", mode_name[mode][0], mode_info[mode]); lcd_puts("\n\tDo not turn off device before finish!\n"); - cmd_result = cmd_process(0, MODE_CMD_ARGC, - *(mode_cmd + mode), - &cmd_repeatable, NULL); + cmd_result = run_command(mode_cmd[mode], 0); if (cmd_result == CMD_RET_SUCCESS) { printf("Command finished\n"); lcd_clear(); lcd_printf("\n\n\t%s finished\n", - mode_name[mode]); + mode_name[mode][0]); - exit_option = exit_boot; + exit_option = exit_reset; leave = 1; } else { printf("Command error\n"); lcd_clear(); lcd_printf("\n\n\t%s command error\n", - mode_name[mode]); + mode_name[mode][0]); exit_option = exit_back; leave = 0; @@ -264,7 +259,7 @@ static void display_download_menu(int mode) for (i = 0; i <= BOOT_MODE_EXIT; i++) lcd_printf("\t%s %s - %s\n\n", selection[i], - mode_name[i], + mode_name[i][0], mode_info[i]); } @@ -305,7 +300,7 @@ static void download_menu(void) if (run) { if (mode_leave_menu(mode)) - break; + run_command("reset", 0); display_download_menu(mode); } From 5c7b8a379fbd9b069c95332204c359f61a7f1594 Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Wed, 30 Apr 2014 13:28:07 +0200 Subject: [PATCH 05/12] samsung: misc: add gpt restore option to lcd menu This menu option allows restore gpt. This is usefull and no needs access to the u-boot console. For proper operation: - each partition uuid should be set in environment or - CONFIG_RANDOM_UUID should be defined for automatically uuid setting After operation success device is going to be reset. Signed-off-by: Przemyslaw Marczak Cc: Minkyu Kang Signed-off-by: Minkyu Kang --- board/samsung/common/misc.c | 3 +++ include/samsung/misc.h | 1 + 2 files changed, 4 insertions(+) diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index 95d1758f7a..2fd104d0fe 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -121,6 +121,7 @@ mode_name[BOOT_MODE_EXIT + 1][2] = { {"THOR", "thor"}, {"UMS", "ums"}, {"DFU", "dfu"}, + {"GPT", "gpt"}, {"EXIT", ""}, }; @@ -130,6 +131,7 @@ mode_info[BOOT_MODE_EXIT + 1] = { "downloader", "mass storage", "firmware update", + "restore", "and run normal boot" }; @@ -139,6 +141,7 @@ mode_cmd[BOOT_MODE_EXIT + 1] = { "thor 0 mmc 0", "ums 0 mmc 0", "dfu 0 mmc 0", + "gpt write mmc 0 $partitions", "", }; diff --git a/include/samsung/misc.h b/include/samsung/misc.h index ede6c1583a..c3d844bc10 100644 --- a/include/samsung/misc.h +++ b/include/samsung/misc.h @@ -15,6 +15,7 @@ enum { BOOT_MODE_THOR, BOOT_MODE_UMS, BOOT_MODE_DFU, + BOOT_MODE_GPT, BOOT_MODE_EXIT, }; From 0954dd61baebcd2de627803ed8e00cc70d9e8b0c Mon Sep 17 00:00:00 2001 From: Inha Song Date: Wed, 30 Apr 2014 13:28:08 +0200 Subject: [PATCH 06/12] samsung: misc: add env default option to lcd menu This change allows reset device environment to default without using u-boot console, which is useful for system developers. Signed-off-by: Inha Song Acked-by: Przemyslaw Marczak Cc: Minkyu Kang Signed-off-by: Minkyu Kang --- board/samsung/common/misc.c | 3 +++ include/samsung/misc.h | 1 + 2 files changed, 4 insertions(+) diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index 2fd104d0fe..65b5c3052e 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -122,6 +122,7 @@ mode_name[BOOT_MODE_EXIT + 1][2] = { {"UMS", "ums"}, {"DFU", "dfu"}, {"GPT", "gpt"}, + {"ENV", "env"}, {"EXIT", ""}, }; @@ -132,6 +133,7 @@ mode_info[BOOT_MODE_EXIT + 1] = { "mass storage", "firmware update", "restore", + "default", "and run normal boot" }; @@ -142,6 +144,7 @@ mode_cmd[BOOT_MODE_EXIT + 1] = { "ums 0 mmc 0", "dfu 0 mmc 0", "gpt write mmc 0 $partitions", + "env default -a; saveenv", "", }; diff --git a/include/samsung/misc.h b/include/samsung/misc.h index c3d844bc10..10653a1b17 100644 --- a/include/samsung/misc.h +++ b/include/samsung/misc.h @@ -16,6 +16,7 @@ enum { BOOT_MODE_UMS, BOOT_MODE_DFU, BOOT_MODE_GPT, + BOOT_MODE_ENV, BOOT_MODE_EXIT, }; From f418a1cfc84e19d82730876594806931bf48e24a Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Wed, 30 Apr 2014 13:28:09 +0200 Subject: [PATCH 07/12] samsung: misc: menu: increase delay in menu main loop Increase menu loop delay to 200 ms helps choose the right menu option by user. Before this, each time key was pressed the current menu option was changed few times. Now it changes only once and also changes few times if key is pressed for a longer time. Signed-off-by: Przemyslaw Marczak Cc: Minkyu Kang Signed-off-by: Minkyu Kang --- board/samsung/common/misc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index 65b5c3052e..2ea275ee7a 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -285,7 +285,7 @@ static void download_menu(void) display_download_menu(mode); last_mode = mode; - mdelay(100); + mdelay(200); key = check_keys(); switch (key) { From 605d7e2af76fd0f28555685e6b8718d956c1da63 Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Wed, 30 Apr 2014 13:28:10 +0200 Subject: [PATCH 08/12] samsung: misc: remove download mode info screen This change removes LCD menu download mode info screen. Now key press timeout is checked in function download_menu() and menu options are displayed directly after PWR + VOLUP keys. Signed-off-by: Przemyslaw Marczak Cc: Minkyu Kang Signed-off-by: Minkyu Kang --- board/samsung/common/misc.c | 73 ++++++++++++++++--------------------- 1 file changed, 31 insertions(+), 42 deletions(-) diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index 2ea275ee7a..03106fdb9f 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -261,7 +261,7 @@ static void display_download_menu(int mode) selection[mode] = "[=>]"; lcd_clear(); - lcd_printf("\n\t\tDownload Mode Menu\n"); + lcd_printf("\n\n\t\tDownload Mode Menu\n\n"); for (i = 0; i <= BOOT_MODE_EXIT; i++) lcd_printf("\t%s %s - %s\n\n", selection[i], @@ -274,10 +274,38 @@ static void download_menu(void) int mode = 0; int last_mode = 0; int run; - int key; + int key = 0; + int timeout = 15; /* sec */ + int i; display_download_menu(mode); + lcd_puts("\n"); + + /* Start count if no key is pressed */ + while (check_keys()) + continue; + + while (timeout--) { + lcd_printf("\r\tNormal boot will start in: %2.d seconds.", + timeout); + + /* about 1000 ms in for loop */ + for (i = 0; i < 10; i++) { + mdelay(100); + key = check_keys(); + if (key) + break; + } + if (key) + break; + } + + if (!key) { + lcd_clear(); + return; + } + while (1) { run = 0; @@ -315,45 +343,6 @@ static void download_menu(void) lcd_clear(); } -static void display_mode_info(void) -{ - lcd_position_cursor(4, 4); - lcd_printf("%s\n", U_BOOT_VERSION); - lcd_puts("\nDownload Mode Menu\n"); -#ifdef CONFIG_SYS_BOARD - lcd_printf("Board name: %s\n", CONFIG_SYS_BOARD); -#endif - lcd_printf("Press POWER KEY to display MENU options."); -} - -static int boot_menu(void) -{ - int key = 0; - int timeout = 10; - - display_mode_info(); - - while (timeout--) { - lcd_printf("\rNormal boot will start in: %d seconds.", timeout); - mdelay(1000); - - key = key_pressed(KEY_POWER); - if (key) - break; - } - - lcd_clear(); - - /* If PWR pressed - show download menu */ - if (key) { - printf("Power pressed - go to download menu\n"); - download_menu(); - printf("Download mode exit.\n"); - } - - return 0; -} - void check_boot_mode(void) { int pwr_key; @@ -366,7 +355,7 @@ void check_boot_mode(void) power_key_pressed(KEY_PWR_INTERRUPT_REG); if (key_pressed(KEY_VOLUMEUP)) - boot_menu(); + download_menu(); else if (key_pressed(KEY_VOLUMEDOWN)) mode_leave_menu(BOOT_MODE_THOR); } From e6fe968b821c3762ad6d7b68ef7ecabf4b40c6a3 Mon Sep 17 00:00:00 2001 From: Akshay Saraswat Date: Tue, 6 May 2014 20:07:04 +0530 Subject: [PATCH 09/12] Exynos5: config: Enable FIT Adding two configs: * CONFIG_FIT - Enable FIT image support. * CONFIG_FIT_BEST_MATCH - Enable fetching correct DTB from FIT image by comparing compatibles. Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Signed-off-by: Minkyu Kang --- include/configs/smdk5250.h | 4 ++++ include/configs/smdk5420.h | 4 ++++ include/configs/snow.h | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 183aae726d..66fa1799e7 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -14,4 +14,8 @@ #undef CONFIG_DEFAULT_DEVICE_TREE #define CONFIG_DEFAULT_DEVICE_TREE exynos5250-smdk5250 +/* Enable FIT support and comparison */ +#define CONFIG_FIT +#define CONFIG_FIT_BEST_MATCH + #endif /* __CONFIG_SMDK_H */ diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index b96eea8890..58f706a3a7 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -51,4 +51,8 @@ #define CONFIG_MAX_I2C_NUM 11 +/* Enable FIT support and comparison */ +#define CONFIG_FIT +#define CONFIG_FIT_BEST_MATCH + #endif /* __CONFIG_5420_H */ diff --git a/include/configs/snow.h b/include/configs/snow.h index ed5c0b614f..673fa1469b 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -14,4 +14,8 @@ #undef CONFIG_DEFAULT_DEVICE_TREE #define CONFIG_DEFAULT_DEVICE_TREE exynos5250-snow +/* Enable FIT support and comparison */ +#define CONFIG_FIT +#define CONFIG_FIT_BEST_MATCH + #endif /* __CONFIG_SNOW_H */ From bfbc47cc9fcbdb67067c20164aece775c2e2603b Mon Sep 17 00:00:00 2001 From: Mateusz Zalega Date: Tue, 29 Apr 2014 20:16:22 +0200 Subject: [PATCH 10/12] ARM: Samsung: s5p_goni: maintainer update Because I'm leaving Samsung Electronics, I won't have access to their developer hardware anymore. Przemyslaw Marczak will take over my responsibilities. Signed-off-by: Mateusz Zalega Acked-by: Przemyslaw Marczak Signed-off-by: Minkyu Kang --- boards.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards.cfg b/boards.cfg index 0b63c5a833..89334f6585 100644 --- a/boards.cfg +++ b/boards.cfg @@ -370,7 +370,7 @@ Active arm armv7 rmobile renesas koelsch Active arm armv7 rmobile renesas koelsch koelsch_nor koelsch:NORFLASH Nobuhiro Iwamatsu Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu -Active arm armv7 s5pc1xx samsung goni s5p_goni - Mateusz Zalega +Active arm armv7 s5pc1xx samsung goni s5p_goni - Przemyslaw Marczak Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier From f6ae1ca05839f92b103aaa0743d1d0012ba9773d Mon Sep 17 00:00:00 2001 From: Akshay Saraswat Date: Tue, 13 May 2014 10:30:14 +0530 Subject: [PATCH 11/12] S5P: Exynos: Add GPIO pin numbering and rename definitions This patch includes following changes : * Adds gpio pin numbering support for EXYNOS SOCs. To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them. * Rename GPIO definitions from GPIO_... to S5P_GPIO_... These changes were done to enable cmd_gpio for EXYNOS and cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence getting a error during compilation. * Adds support for name to gpio conversion in s5p_gpio to enable gpio command EXYNOS SoCs. Function has been added to asm/gpio.h to decode the input gpio name to gpio number. Example: SMDK5420 # gpio set gpa00 Signed-off-by: Leela Krishna Amudala Signed-off-by: Rajeshwari Shinde Signed-off-by: Akshay Saraswat Acked-by: Przemyslaw Marczak Signed-off-by: Minkyu Kang --- arch/arm/cpu/armv7/exynos/pinmux.c | 561 +++--- arch/arm/dts/exynos4210-origen.dts | 4 +- arch/arm/dts/exynos4210-trats.dts | 6 +- arch/arm/dts/exynos4210-universal_c210.dts | 4 +- arch/arm/dts/exynos4412-trats2.dts | 4 +- arch/arm/include/asm/arch-exynos/cpu.h | 17 +- arch/arm/include/asm/arch-exynos/gpio.h | 1787 ++++++++++++++++---- arch/arm/include/asm/arch-s5pc1xx/gpio.h | 960 +++++++++-- board/samsung/arndale/arndale.c | 11 +- board/samsung/goni/goni.c | 32 +- board/samsung/smdk5250/exynos5-dt.c | 20 +- board/samsung/smdk5250/smdk5250.c | 19 +- board/samsung/smdk5420/smdk5420.c | 15 +- board/samsung/smdkc100/smdkc100.c | 5 +- board/samsung/smdkv310/smdkv310.c | 19 +- board/samsung/trats/trats.c | 39 +- board/samsung/trats2/trats2.c | 74 +- board/samsung/universal_c210/universal.c | 51 +- drivers/gpio/s5p_gpio.c | 204 ++- 19 files changed, 2918 insertions(+), 914 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 9edb47502c..ee7c2e5a4b 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -13,30 +13,23 @@ static void exynos5_uart_config(int peripheral) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - struct s5p_gpio_bank *bank; int i, start, count; switch (peripheral) { case PERIPH_ID_UART0: - bank = &gpio1->a0; - start = 0; + start = EXYNOS5_GPIO_A00; count = 4; break; case PERIPH_ID_UART1: - bank = &gpio1->d0; - start = 0; + start = EXYNOS5_GPIO_D00; count = 4; break; case PERIPH_ID_UART2: - bank = &gpio1->a1; - start = 0; + start = EXYNOS5_GPIO_A10; count = 4; break; case PERIPH_ID_UART3: - bank = &gpio1->a1; - start = 4; + start = EXYNOS5_GPIO_A14; count = 2; break; default: @@ -44,37 +37,30 @@ static void exynos5_uart_config(int peripheral) return; } for (i = start; i < start + count; i++) { - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); } } static void exynos5420_uart_config(int peripheral) { - struct exynos5420_gpio_part1 *gpio1 = - (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1(); - struct s5p_gpio_bank *bank; int i, start, count; switch (peripheral) { case PERIPH_ID_UART0: - bank = &gpio1->a0; - start = 0; + start = EXYNOS5420_GPIO_A00; count = 4; break; case PERIPH_ID_UART1: - bank = &gpio1->a0; - start = 4; + start = EXYNOS5420_GPIO_A04; count = 4; break; case PERIPH_ID_UART2: - bank = &gpio1->a1; - start = 0; + start = EXYNOS5420_GPIO_A10; count = 4; break; case PERIPH_ID_UART3: - bank = &gpio1->a1; - start = 4; + start = EXYNOS5420_GPIO_A14; count = 2; break; default: @@ -83,64 +69,59 @@ static void exynos5420_uart_config(int peripheral) } for (i = start; i < start + count; i++) { - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); } } static int exynos5_mmc_config(int peripheral, int flags) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - struct s5p_gpio_bank *bank, *bank_ext; - int i, start = 0, gpio_func = 0; + int i, start, start_ext, gpio_func = 0; switch (peripheral) { case PERIPH_ID_SDMMC0: - bank = &gpio1->c0; - bank_ext = &gpio1->c1; - start = 0; - gpio_func = GPIO_FUNC(0x2); + start = EXYNOS5_GPIO_C00; + start_ext = EXYNOS5_GPIO_C10; + gpio_func = S5P_GPIO_FUNC(0x2); break; case PERIPH_ID_SDMMC1: - bank = &gpio1->c2; - bank_ext = NULL; + start = EXYNOS5_GPIO_C20; + start_ext = 0; break; case PERIPH_ID_SDMMC2: - bank = &gpio1->c3; - bank_ext = &gpio1->c4; - start = 3; - gpio_func = GPIO_FUNC(0x3); + start = EXYNOS5_GPIO_C30; + start_ext = EXYNOS5_GPIO_C43; + gpio_func = S5P_GPIO_FUNC(0x3); break; case PERIPH_ID_SDMMC3: - bank = &gpio1->c4; - bank_ext = NULL; + start = EXYNOS5_GPIO_C40; + start_ext = 0; break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; } - if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { + if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { debug("SDMMC device %d does not support 8bit mode", peripheral); return -1; } if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = start; i <= (start + 3); i++) { - s5p_gpio_cfg_pin(bank_ext, i, gpio_func); - s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + for (i = start_ext; i <= (start_ext + 3); i++) { + gpio_cfg_pin(i, gpio_func); + gpio_set_pull(i, S5P_GPIO_PULL_UP); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } } - for (i = 0; i < 2; i++) { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + for (i = start; i < (start + 2); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } - for (i = 3; i <= 6; i++) { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + for (i = (start + 3); i <= (start + 6); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_UP); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } return 0; @@ -148,26 +129,20 @@ static int exynos5_mmc_config(int peripheral, int flags) static int exynos5420_mmc_config(int peripheral, int flags) { - struct exynos5420_gpio_part3 *gpio3 = - (struct exynos5420_gpio_part3 *)samsung_get_base_gpio_part3(); - struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL; - int i, start; + int i, start = 0, start_ext = 0; switch (peripheral) { case PERIPH_ID_SDMMC0: - bank = &gpio3->c0; - bank_ext = &gpio3->c3; - start = 0; + start = EXYNOS5420_GPIO_C00; + start_ext = EXYNOS5420_GPIO_C30; break; case PERIPH_ID_SDMMC1: - bank = &gpio3->c1; - bank_ext = &gpio3->d1; - start = 4; + start = EXYNOS5420_GPIO_C10; + start_ext = EXYNOS5420_GPIO_D14; break; case PERIPH_ID_SDMMC2: - bank = &gpio3->c2; - bank_ext = NULL; - start = 0; + start = EXYNOS5420_GPIO_C20; + start_ext = 0; break; default: start = 0; @@ -175,41 +150,41 @@ static int exynos5420_mmc_config(int peripheral, int flags) return -1; } - if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { + if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { debug("SDMMC device %d does not support 8bit mode", peripheral); return -1; } if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = start; i <= (start + 3); i++) { - s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + for (i = start_ext; i <= (start_ext + 3); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_UP); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } } - for (i = 0; i < 3; i++) { + for (i = start; i < (start + 3); i++) { /* * MMC0 is intended to be used for eMMC. The * card detect pin is used as a VDDEN signal to * power on the eMMC. The 5420 iROM makes * this same assumption. */ - if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) { - s5p_gpio_set_value(bank, i, 1); - s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT); + if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) { + gpio_set_value(i, 1); + gpio_cfg_pin(i, S5P_GPIO_OUTPUT); } else { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); } - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } - for (i = 3; i <= 6; i++) { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + for (i = (start + 3); i <= (start + 6); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_UP); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } return 0; @@ -217,8 +192,6 @@ static int exynos5420_mmc_config(int peripheral, int flags) static void exynos5_sromc_config(int flags) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); int i; /* @@ -236,13 +209,13 @@ static void exynos5_sromc_config(int flags) * GPY1[2] SROM_WAIT(2) * GPY1[3] EBI_DATA_RDn(2) */ - s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK), - GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK), + S5P_GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS5_GPIO_Y04, S5P_GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS5_GPIO_Y05, S5P_GPIO_FUNC(2)); for (i = 0; i < 4; i++) - s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, S5P_GPIO_FUNC(2)); /* * EBI: 8 Addrss Lines @@ -277,108 +250,101 @@ static void exynos5_sromc_config(int flags) * GPY6[7] EBI_DATA[15](2) */ for (i = 0; i < 8; i++) { - s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP); + gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_FUNC(2)); + gpio_set_pull(EXYNOS5_GPIO_Y30 + i, S5P_GPIO_PULL_UP); - s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP); + gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_FUNC(2)); + gpio_set_pull(EXYNOS5_GPIO_Y50 + i, S5P_GPIO_PULL_UP); - s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP); + gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_FUNC(2)); + gpio_set_pull(EXYNOS5_GPIO_Y60 + i, S5P_GPIO_PULL_UP); } } static void exynos5_i2c_config(int peripheral, int flags) { - - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - switch (peripheral) { case PERIPH_ID_I2C0: - s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C1: - s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C2: - s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C3: - s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C4: - s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A21, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C5: - s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A22, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_A23, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C6: - s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5_GPIO_B13, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5_GPIO_B14, S5P_GPIO_FUNC(0x4)); break; case PERIPH_ID_I2C7: - s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_B22, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_B23, S5P_GPIO_FUNC(0x3)); break; } } static void exynos5420_i2c_config(int peripheral) { - struct exynos5420_gpio_part1 *gpio1 = - (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1(); - switch (peripheral) { case PERIPH_ID_I2C0: - s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B30, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B31, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C1: - s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B32, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B33, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C2: - s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A06, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A07, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C3: - s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A12, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A13, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C4: - s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A20, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A21, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C5: - s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A22, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_A23, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C6: - s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5420_GPIO_B13, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5420_GPIO_B14, S5P_GPIO_FUNC(0x4)); break; case PERIPH_ID_I2C7: - s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_B22, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_B23, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C8: - s5p_gpio_cfg_pin(&gpio1->b3, 4, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 5, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B34, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B35, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C9: - s5p_gpio_cfg_pin(&gpio1->b3, 6, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b3, 7, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B36, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B37, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C10: - s5p_gpio_cfg_pin(&gpio1->b4, 0, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->b4, 1, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B40, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS5420_GPIO_B41, S5P_GPIO_FUNC(0x2)); break; } } @@ -386,19 +352,15 @@ static void exynos5420_i2c_config(int peripheral) static void exynos5_i2s_config(int peripheral) { int i; - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1(); - struct exynos5_gpio_part4 *gpio4 = - (struct exynos5_gpio_part4 *)samsung_get_base_gpio_part4(); switch (peripheral) { case PERIPH_ID_I2S0: for (i = 0; i < 5; i++) - s5p_gpio_cfg_pin(&gpio4->z, i, GPIO_FUNC(0x02)); + gpio_cfg_pin(EXYNOS5_GPIO_Z0 + i, S5P_GPIO_FUNC(0x02)); break; case PERIPH_ID_I2S1: for (i = 0; i < 5; i++) - s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02)); + gpio_cfg_pin(EXYNOS5_GPIO_B00 + i, S5P_GPIO_FUNC(0x02)); break; } } @@ -406,75 +368,57 @@ static void exynos5_i2s_config(int peripheral) void exynos5_spi_config(int peripheral) { int cfg = 0, pin = 0, i; - struct s5p_gpio_bank *bank = NULL; - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - struct exynos5_gpio_part2 *gpio2 = - (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2(); switch (peripheral) { case PERIPH_ID_SPI0: - bank = &gpio1->a2; - cfg = GPIO_FUNC(0x2); - pin = 0; + cfg = S5P_GPIO_FUNC(0x2); + pin = EXYNOS5_GPIO_A20; break; case PERIPH_ID_SPI1: - bank = &gpio1->a2; - cfg = GPIO_FUNC(0x2); - pin = 4; + cfg = S5P_GPIO_FUNC(0x2); + pin = EXYNOS5_GPIO_A24; break; case PERIPH_ID_SPI2: - bank = &gpio1->b1; - cfg = GPIO_FUNC(0x5); - pin = 1; + cfg = S5P_GPIO_FUNC(0x5); + pin = EXYNOS5_GPIO_B11; break; case PERIPH_ID_SPI3: - bank = &gpio2->f1; - cfg = GPIO_FUNC(0x2); - pin = 0; + cfg = S5P_GPIO_FUNC(0x2); + pin = EXYNOS5_GPIO_F10; break; case PERIPH_ID_SPI4: for (i = 0; i < 2; i++) { - s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, S5P_GPIO_FUNC(0x4)); } break; } if (peripheral != PERIPH_ID_SPI4) { for (i = pin; i < pin + 4; i++) - s5p_gpio_cfg_pin(bank, i, cfg); + gpio_cfg_pin(i, cfg); } } void exynos5420_spi_config(int peripheral) { int cfg, pin, i; - struct s5p_gpio_bank *bank = NULL; - struct exynos5420_gpio_part1 *gpio1 = - (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1(); - struct exynos5420_gpio_part4 *gpio4 = - (struct exynos5420_gpio_part4 *)samsung_get_base_gpio_part4(); switch (peripheral) { case PERIPH_ID_SPI0: - bank = &gpio1->a2; - cfg = GPIO_FUNC(0x2); - pin = 0; + pin = EXYNOS5420_GPIO_A20; + cfg = S5P_GPIO_FUNC(0x2); break; case PERIPH_ID_SPI1: - bank = &gpio1->a2; - cfg = GPIO_FUNC(0x2); - pin = 4; + pin = EXYNOS5420_GPIO_A24; + cfg = S5P_GPIO_FUNC(0x2); break; case PERIPH_ID_SPI2: - bank = &gpio1->b1; - cfg = GPIO_FUNC(0x5); - pin = 1; + pin = EXYNOS5420_GPIO_B11; + cfg = S5P_GPIO_FUNC(0x5); break; case PERIPH_ID_SPI3: - bank = &gpio4->f1; - cfg = GPIO_FUNC(0x2); - pin = 0; + pin = EXYNOS5420_GPIO_F10; + cfg = S5P_GPIO_FUNC(0x2); break; case PERIPH_ID_SPI4: cfg = 0; @@ -489,11 +433,13 @@ void exynos5420_spi_config(int peripheral) if (peripheral != PERIPH_ID_SPI4) { for (i = pin; i < pin + 4; i++) - s5p_gpio_cfg_pin(bank, i, cfg); + gpio_cfg_pin(i, cfg); } else { for (i = 0; i < 2; i++) { - s5p_gpio_cfg_pin(&gpio4->f0, i + 2, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio4->e0, i + 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5420_GPIO_F02 + i, + S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS5420_GPIO_E04 + i, + S5P_GPIO_FUNC(0x4)); } } } @@ -588,76 +534,70 @@ static int exynos5420_pinmux_config(int peripheral, int flags) static void exynos4_i2c_config(int peripheral, int flags) { - struct exynos4_gpio_part1 *gpio1 = - (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1(); - switch (peripheral) { case PERIPH_ID_I2C0: - s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4_GPIO_D10, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4_GPIO_D11, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C1: - s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2)); - s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4_GPIO_D12, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4_GPIO_D13, S5P_GPIO_FUNC(0x2)); break; case PERIPH_ID_I2C2: - s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_A06, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_A07, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C3: - s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_A12, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_A13, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C4: - s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_B2, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_B3, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C5: - s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_B6, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_B7, S5P_GPIO_FUNC(0x3)); break; case PERIPH_ID_I2C6: - s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4)); - s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS4_GPIO_C13, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS4_GPIO_C14, S5P_GPIO_FUNC(0x4)); break; case PERIPH_ID_I2C7: - s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3)); - s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_D02, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4_GPIO_D03, S5P_GPIO_FUNC(0x3)); break; } } static int exynos4_mmc_config(int peripheral, int flags) { - struct exynos4_gpio_part2 *gpio2 = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - struct s5p_gpio_bank *bank, *bank_ext; - int i; + int i, start = 0, start_ext = 0; switch (peripheral) { case PERIPH_ID_SDMMC0: - bank = &gpio2->k0; - bank_ext = &gpio2->k1; + start = EXYNOS4_GPIO_K00; + start_ext = EXYNOS4_GPIO_K13; break; case PERIPH_ID_SDMMC2: - bank = &gpio2->k2; - bank_ext = &gpio2->k3; + start = EXYNOS4_GPIO_K20; + start_ext = EXYNOS4_GPIO_K33; break; default: return -1; } - for (i = 0; i < 7; i++) { - if (i == 2) + for (i = start; i < (start + 7); i++) { + if (i == (start + 2)) continue; - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = 3; i < 7; i++) { - s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3)); - s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + for (i = start_ext; i < (start_ext + 4); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x3)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } } @@ -666,41 +606,138 @@ static int exynos4_mmc_config(int peripheral, int flags) static void exynos4_uart_config(int peripheral) { - struct exynos4_gpio_part1 *gpio1 = - (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); - struct s5p_gpio_bank *bank; int i, start, count; switch (peripheral) { case PERIPH_ID_UART0: - bank = &gpio1->a0; - start = 0; + start = EXYNOS4_GPIO_A00; count = 4; break; case PERIPH_ID_UART1: - bank = &gpio1->a0; - start = 4; + start = EXYNOS4_GPIO_A04; count = 4; break; case PERIPH_ID_UART2: - bank = &gpio1->a1; - start = 0; + start = EXYNOS4_GPIO_A10; count = 4; break; case PERIPH_ID_UART3: - bank = &gpio1->a1; - start = 4; + start = EXYNOS4_GPIO_A14; count = 2; break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return; } - for (i = start; i < start + count; i++) { - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + for (i = start; i < (start + count); i++) { + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); } } + +static void exynos4x12_i2c_config(int peripheral, int flags) +{ + switch (peripheral) { + case PERIPH_ID_I2C0: + gpio_cfg_pin(EXYNOS4X12_GPIO_D10, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4X12_GPIO_D11, S5P_GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C1: + gpio_cfg_pin(EXYNOS4X12_GPIO_D12, S5P_GPIO_FUNC(0x2)); + gpio_cfg_pin(EXYNOS4X12_GPIO_D13, S5P_GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C2: + gpio_cfg_pin(EXYNOS4X12_GPIO_A06, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_A07, S5P_GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C3: + gpio_cfg_pin(EXYNOS4X12_GPIO_A12, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_A13, S5P_GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C4: + gpio_cfg_pin(EXYNOS4X12_GPIO_B2, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_B3, S5P_GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C5: + gpio_cfg_pin(EXYNOS4X12_GPIO_B6, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_B7, S5P_GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C6: + gpio_cfg_pin(EXYNOS4X12_GPIO_C13, S5P_GPIO_FUNC(0x4)); + gpio_cfg_pin(EXYNOS4X12_GPIO_C14, S5P_GPIO_FUNC(0x4)); + break; + case PERIPH_ID_I2C7: + gpio_cfg_pin(EXYNOS4X12_GPIO_D02, S5P_GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS4X12_GPIO_D03, S5P_GPIO_FUNC(0x3)); + break; + } +} + +static int exynos4x12_mmc_config(int peripheral, int flags) +{ + int i, start = 0, start_ext = 0; + + switch (peripheral) { + case PERIPH_ID_SDMMC0: + start = EXYNOS4X12_GPIO_K00; + start_ext = EXYNOS4X12_GPIO_K13; + break; + case PERIPH_ID_SDMMC2: + start = EXYNOS4X12_GPIO_K20; + start_ext = EXYNOS4X12_GPIO_K33; + break; + default: + return -1; + } + for (i = start; i < (start + 7); i++) { + if (i == (start + 2)) + continue; + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); + } + if (flags & PINMUX_FLAG_8BIT_MODE) { + for (i = start_ext; i < (start_ext + 4); i++) { + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x3)); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_set_drv(i, S5P_GPIO_DRV_4X); + } + } + + return 0; +} + +static void exynos4x12_uart_config(int peripheral) +{ + int i, start, count; + + switch (peripheral) { + case PERIPH_ID_UART0: + start = EXYNOS4X12_GPIO_A00; + count = 4; + break; + case PERIPH_ID_UART1: + start = EXYNOS4X12_GPIO_A04; + count = 4; + break; + case PERIPH_ID_UART2: + start = EXYNOS4X12_GPIO_A10; + count = 4; + break; + case PERIPH_ID_UART3: + start = EXYNOS4X12_GPIO_A14; + count = 2; + break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return; + } + for (i = start; i < (start + count); i++) { + gpio_set_pull(i, S5P_GPIO_PULL_NONE); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); + } +} + static int exynos4_pinmux_config(int peripheral, int flags) { switch (peripheral) { @@ -736,6 +773,41 @@ static int exynos4_pinmux_config(int peripheral, int flags) return 0; } +static int exynos4x12_pinmux_config(int peripheral, int flags) +{ + switch (peripheral) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + exynos4x12_uart_config(peripheral); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + exynos4x12_i2c_config(peripheral, flags); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC2: + return exynos4x12_mmc_config(peripheral, flags); + case PERIPH_ID_SDMMC1: + case PERIPH_ID_SDMMC3: + case PERIPH_ID_SDMMC4: + debug("SDMMC device %d not implemented\n", peripheral); + return -1; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + } + + return 0; +} + int exynos_pinmux_config(int peripheral, int flags) { if (cpu_is_exynos5()) { @@ -744,11 +816,14 @@ int exynos_pinmux_config(int peripheral, int flags) else if (proid_is_exynos5250()) return exynos5_pinmux_config(peripheral, flags); } else if (cpu_is_exynos4()) { - return exynos4_pinmux_config(peripheral, flags); - } else { - debug("pinmux functionality not supported\n"); + if (proid_is_exynos4412()) + return exynos4x12_pinmux_config(peripheral, flags); + else + return exynos4_pinmux_config(peripheral, flags); } + debug("pinmux functionality not supported\n"); + return -1; } @@ -787,7 +862,7 @@ int pinmux_decode_periph_id(const void *blob, int node) return exynos5_pinmux_decode_periph_id(blob, node); else if (cpu_is_exynos4()) return exynos4_pinmux_decode_periph_id(blob, node); - else - return PERIPH_ID_NONE; + + return PERIPH_ID_NONE; } #endif diff --git a/arch/arm/dts/exynos4210-origen.dts b/arch/arm/dts/exynos4210-origen.dts index 5c9d2aed68..15059d2202 100644 --- a/arch/arm/dts/exynos4210-origen.dts +++ b/arch/arm/dts/exynos4210-origen.dts @@ -36,10 +36,10 @@ sdhci@12530000 { samsung,bus-width = <4>; samsung,timing = <1 2 3>; - cd-gpios = <&gpio 0x2008002 0>; + cd-gpios = <&gpio 0xA2 0>; }; sdhci@12540000 { status = "disabled"; }; -}; \ No newline at end of file +}; diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts index 992e0234c9..0ff69393b7 100644 --- a/arch/arm/dts/exynos4210-trats.dts +++ b/arch/arm/dts/exynos4210-trats.dts @@ -101,7 +101,7 @@ sdhci@12510000 { samsung,bus-width = <8>; samsung,timing = <1 3 3>; - pwr-gpios = <&gpio 0x2008002 0>; + pwr-gpios = <&gpio 0xA2 0>; }; sdhci@12520000 { @@ -111,10 +111,10 @@ sdhci@12530000 { samsung,bus-width = <4>; samsung,timing = <1 2 3>; - cd-gpios = <&gpio 0x20c6004 0>; + cd-gpios = <&gpio 0x39C 0>; }; sdhci@12540000 { status = "disabled"; }; -}; \ No newline at end of file +}; diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts index 1cdd981d6d..6941906aaa 100644 --- a/arch/arm/dts/exynos4210-universal_c210.dts +++ b/arch/arm/dts/exynos4210-universal_c210.dts @@ -24,7 +24,7 @@ sdhci@12510000 { samsung,bus-width = <8>; samsung,timing = <1 3 3>; - pwr-gpios = <&gpio 0x2008002 0>; + pwr-gpios = <&gpio 0xA2 0>; }; sdhci@12520000 { @@ -34,7 +34,7 @@ sdhci@12530000 { samsung,bus-width = <4>; samsung,timing = <1 2 3>; - cd-gpios = <&gpio 0x20c6004 0>; + cd-gpios = <&gpio 0x39C 0>; }; sdhci@12540000 { diff --git a/arch/arm/dts/exynos4412-trats2.dts b/arch/arm/dts/exynos4412-trats2.dts index 7d32067fdd..1596f8328a 100644 --- a/arch/arm/dts/exynos4412-trats2.dts +++ b/arch/arm/dts/exynos4412-trats2.dts @@ -415,7 +415,7 @@ sdhci@12510000 { samsung,bus-width = <8>; samsung,timing = <1 3 3>; - pwr-gpios = <&gpio 0x2004002 0>; + pwr-gpios = <&gpio 0xB2 0>; }; sdhci@12520000 { @@ -425,7 +425,7 @@ sdhci@12530000 { samsung,bus-width = <4>; samsung,timing = <1 2 3>; - cd-gpios = <&gpio 0x20C6004 0>; + cd-gpios = <&gpio 0x3BC 0>; }; sdhci@12540000 { diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index fdf73b507a..ba717146f5 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -98,7 +98,7 @@ #define EXYNOS5_I2C_SPACING 0x10000 #define EXYNOS5_AUDIOSS_BASE 0x03810000 -#define EXYNOS5_GPIO_PART4_BASE 0x03860000 +#define EXYNOS5_GPIO_PART8_BASE 0x03860000 #define EXYNOS5_PRO_ID 0x10000000 #define EXYNOS5_CLOCK_BASE 0x10010000 #define EXYNOS5_POWER_BASE 0x10040000 @@ -108,9 +108,13 @@ #define EXYNOS5_WATCHDOG_BASE 0x101D0000 #define EXYNOS5_ACE_SFR_BASE 0x10830000 #define EXYNOS5_DMC_PHY_BASE 0x10C00000 -#define EXYNOS5_GPIO_PART3_BASE 0x10D10000 +#define EXYNOS5_GPIO_PART5_BASE 0x10D10000 +#define EXYNOS5_GPIO_PART6_BASE 0x10D10060 +#define EXYNOS5_GPIO_PART7_BASE 0x10D100C0 #define EXYNOS5_DMC_CTRL_BASE 0x10DD0000 #define EXYNOS5_GPIO_PART1_BASE 0x11400000 +#define EXYNOS5_GPIO_PART2_BASE 0x114002E0 +#define EXYNOS5_GPIO_PART3_BASE 0x11400C00 #define EXYNOS5_MIPI_DSIM_BASE 0x11D00000 #define EXYNOS5_USB_HOST_XHCI_BASE 0x12000000 #define EXYNOS5_USB3PHY_BASE 0x12100000 @@ -125,7 +129,7 @@ #define EXYNOS5_I2S_BASE 0x12D60000 #define EXYNOS5_PWMTIMER_BASE 0x12DD0000 #define EXYNOS5_SPI_ISP_BASE 0x131A0000 -#define EXYNOS5_GPIO_PART2_BASE 0x13400000 +#define EXYNOS5_GPIO_PART4_BASE 0x13400000 #define EXYNOS5_FIMD_BASE 0x14400000 #define EXYNOS5_DP_BASE 0x145B0000 @@ -135,7 +139,7 @@ /* EXYNOS5420 */ #define EXYNOS5420_AUDIOSS_BASE 0x03810000 -#define EXYNOS5420_GPIO_PART5_BASE 0x03860000 +#define EXYNOS5420_GPIO_PART6_BASE 0x03860000 #define EXYNOS5420_PRO_ID 0x10000000 #define EXYNOS5420_CLOCK_BASE 0x10010000 #define EXYNOS5420_POWER_BASE 0x10040000 @@ -158,8 +162,9 @@ #define EXYNOS5420_PWMTIMER_BASE 0x12DD0000 #define EXYNOS5420_SPI_ISP_BASE 0x131A0000 #define EXYNOS5420_GPIO_PART2_BASE 0x13400000 -#define EXYNOS5420_GPIO_PART3_BASE 0x13410000 -#define EXYNOS5420_GPIO_PART4_BASE 0x14000000 +#define EXYNOS5420_GPIO_PART3_BASE 0x13400C00 +#define EXYNOS5420_GPIO_PART4_BASE 0x13410000 +#define EXYNOS5420_GPIO_PART5_BASE 0x14000000 #define EXYNOS5420_GPIO_PART1_BASE 0x14010000 #define EXYNOS5420_MIPI_DSIM_BASE 0x14500000 #define EXYNOS5420_DP_BASE 0x145B0000 diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index d6868fa25d..be5113f0e2 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -19,328 +19,1515 @@ struct s5p_gpio_bank { unsigned char res1[8]; }; -struct exynos4_gpio_part1 { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank b; - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank d0; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank e0; - struct s5p_gpio_bank e1; - struct s5p_gpio_bank e2; - struct s5p_gpio_bank e3; - struct s5p_gpio_bank e4; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank f2; - struct s5p_gpio_bank f3; -}; - -struct exynos4_gpio_part2 { - struct s5p_gpio_bank j0; - struct s5p_gpio_bank j1; - struct s5p_gpio_bank k0; - struct s5p_gpio_bank k1; - struct s5p_gpio_bank k2; - struct s5p_gpio_bank k3; - struct s5p_gpio_bank l0; - struct s5p_gpio_bank l1; - struct s5p_gpio_bank l2; - struct s5p_gpio_bank y0; - struct s5p_gpio_bank y1; - struct s5p_gpio_bank y2; - struct s5p_gpio_bank y3; - struct s5p_gpio_bank y4; - struct s5p_gpio_bank y5; - struct s5p_gpio_bank y6; - struct s5p_gpio_bank res1[80]; - struct s5p_gpio_bank x0; - struct s5p_gpio_bank x1; - struct s5p_gpio_bank x2; - struct s5p_gpio_bank x3; -}; - -struct exynos4_gpio_part3 { - struct s5p_gpio_bank z; -}; - -struct exynos4x12_gpio_part1 { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank b; - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank d0; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank res1[0x5]; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank f2; - struct s5p_gpio_bank f3; - struct s5p_gpio_bank res2[0x2]; - struct s5p_gpio_bank j0; - struct s5p_gpio_bank j1; -}; - -struct exynos4x12_gpio_part2 { - struct s5p_gpio_bank res1[0x2]; - struct s5p_gpio_bank k0; - struct s5p_gpio_bank k1; - struct s5p_gpio_bank k2; - struct s5p_gpio_bank k3; - struct s5p_gpio_bank l0; - struct s5p_gpio_bank l1; - struct s5p_gpio_bank l2; - struct s5p_gpio_bank y0; - struct s5p_gpio_bank y1; - struct s5p_gpio_bank y2; - struct s5p_gpio_bank y3; - struct s5p_gpio_bank y4; - struct s5p_gpio_bank y5; - struct s5p_gpio_bank y6; - struct s5p_gpio_bank res2[0x3]; - struct s5p_gpio_bank m0; - struct s5p_gpio_bank m1; - struct s5p_gpio_bank m2; - struct s5p_gpio_bank m3; - struct s5p_gpio_bank m4; - struct s5p_gpio_bank res3[0x48]; - struct s5p_gpio_bank x0; - struct s5p_gpio_bank x1; - struct s5p_gpio_bank x2; - struct s5p_gpio_bank x3; -}; - -struct exynos4x12_gpio_part3 { - struct s5p_gpio_bank z; -}; - -struct exynos4x12_gpio_part4 { - struct s5p_gpio_bank v0; - struct s5p_gpio_bank v1; - struct s5p_gpio_bank res1[0x1]; - struct s5p_gpio_bank v2; - struct s5p_gpio_bank v3; - struct s5p_gpio_bank res2[0x1]; - struct s5p_gpio_bank v4; -}; - -struct exynos5420_gpio_part1 { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank a2; - struct s5p_gpio_bank b0; - struct s5p_gpio_bank b1; - struct s5p_gpio_bank b2; - struct s5p_gpio_bank b3; - struct s5p_gpio_bank b4; - struct s5p_gpio_bank h0; -}; - -struct exynos5420_gpio_part2 { - struct s5p_gpio_bank y7; /* 0x1340_0000 */ - struct s5p_gpio_bank res[0x5f]; /* */ - struct s5p_gpio_bank x0; /* 0x1340_0C00 */ - struct s5p_gpio_bank x1; /* 0x1340_0C20 */ - struct s5p_gpio_bank x2; /* 0x1340_0C40 */ - struct s5p_gpio_bank x3; /* 0x1340_0C60 */ -}; - -struct exynos5420_gpio_part3 { - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank c2; - struct s5p_gpio_bank c3; - struct s5p_gpio_bank c4; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank y0; - struct s5p_gpio_bank y1; - struct s5p_gpio_bank y2; - struct s5p_gpio_bank y3; - struct s5p_gpio_bank y4; - struct s5p_gpio_bank y5; - struct s5p_gpio_bank y6; -}; - -struct exynos5420_gpio_part4 { - struct s5p_gpio_bank e0; /* 0x1400_0000 */ - struct s5p_gpio_bank e1; /* 0x1400_0020 */ - struct s5p_gpio_bank f0; /* 0x1400_0040 */ - struct s5p_gpio_bank f1; /* 0x1400_0060 */ - struct s5p_gpio_bank g0; /* 0x1400_0080 */ - struct s5p_gpio_bank g1; /* 0x1400_00A0 */ - struct s5p_gpio_bank g2; /* 0x1400_00C0 */ - struct s5p_gpio_bank j4; /* 0x1400_00E0 */ -}; - -struct exynos5420_gpio_part5 { - struct s5p_gpio_bank z0; /* 0x0386_0000 */ -}; - -struct exynos5_gpio_part1 { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank a2; - struct s5p_gpio_bank b0; - struct s5p_gpio_bank b1; - struct s5p_gpio_bank b2; - struct s5p_gpio_bank b3; - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank c2; - struct s5p_gpio_bank c3; - struct s5p_gpio_bank d0; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank y0; - struct s5p_gpio_bank y1; - struct s5p_gpio_bank y2; - struct s5p_gpio_bank y3; - struct s5p_gpio_bank y4; - struct s5p_gpio_bank y5; - struct s5p_gpio_bank y6; - struct s5p_gpio_bank res1[0x3]; - struct s5p_gpio_bank c4; - struct s5p_gpio_bank res2[0x48]; - struct s5p_gpio_bank x0; - struct s5p_gpio_bank x1; - struct s5p_gpio_bank x2; - struct s5p_gpio_bank x3; -}; - -struct exynos5_gpio_part2 { - struct s5p_gpio_bank e0; - struct s5p_gpio_bank e1; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank g0; - struct s5p_gpio_bank g1; - struct s5p_gpio_bank g2; - struct s5p_gpio_bank h0; - struct s5p_gpio_bank h1; -}; - -struct exynos5_gpio_part3 { - struct s5p_gpio_bank v0; - struct s5p_gpio_bank v1; - struct s5p_gpio_bank res1[0x1]; - struct s5p_gpio_bank v2; - struct s5p_gpio_bank v3; - struct s5p_gpio_bank res2[0x1]; - struct s5p_gpio_bank v4; -}; - -struct exynos5_gpio_part4 { - struct s5p_gpio_bank z; -}; - -/* functions */ -void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg); -void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en); -void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio); -void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en); -unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio); -void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode); -void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode); -void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); - /* GPIO pins per bank */ #define GPIO_PER_BANK 8 -#define S5P_GPIO_PART_SHIFT (24) -#define S5P_GPIO_PART_MASK (0xff) -#define S5P_GPIO_BANK_SHIFT (8) -#define S5P_GPIO_BANK_MASK (0xffff) -#define S5P_GPIO_PIN_MASK (0xff) -#define S5P_GPIO_SET_PART(x) \ - (((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT) +/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */ +enum exynos4_gpio_pin { + /* GPIO_PART1_STARTS */ + EXYNOS4_GPIO_A00, /* 0 */ + EXYNOS4_GPIO_A01, + EXYNOS4_GPIO_A02, + EXYNOS4_GPIO_A03, + EXYNOS4_GPIO_A04, + EXYNOS4_GPIO_A05, + EXYNOS4_GPIO_A06, + EXYNOS4_GPIO_A07, + EXYNOS4_GPIO_A10, /* 8 */ + EXYNOS4_GPIO_A11, + EXYNOS4_GPIO_A12, + EXYNOS4_GPIO_A13, + EXYNOS4_GPIO_A14, + EXYNOS4_GPIO_A15, + EXYNOS4_GPIO_A16, + EXYNOS4_GPIO_A17, + EXYNOS4_GPIO_B0, /* 16 0x10 */ + EXYNOS4_GPIO_B1, + EXYNOS4_GPIO_B2, + EXYNOS4_GPIO_B3, + EXYNOS4_GPIO_B4, + EXYNOS4_GPIO_B5, + EXYNOS4_GPIO_B6, + EXYNOS4_GPIO_B7, + EXYNOS4_GPIO_C00, /* 24 0x18 */ + EXYNOS4_GPIO_C01, + EXYNOS4_GPIO_C02, + EXYNOS4_GPIO_C03, + EXYNOS4_GPIO_C04, + EXYNOS4_GPIO_C05, + EXYNOS4_GPIO_C06, + EXYNOS4_GPIO_C07, + EXYNOS4_GPIO_C10, /* 32 0x20*/ + EXYNOS4_GPIO_C11, + EXYNOS4_GPIO_C12, + EXYNOS4_GPIO_C13, + EXYNOS4_GPIO_C14, + EXYNOS4_GPIO_C15, + EXYNOS4_GPIO_C16, + EXYNOS4_GPIO_C17, + EXYNOS4_GPIO_D00, /* 40 0x28 */ + EXYNOS4_GPIO_D01, + EXYNOS4_GPIO_D02, + EXYNOS4_GPIO_D03, + EXYNOS4_GPIO_D04, + EXYNOS4_GPIO_D05, + EXYNOS4_GPIO_D06, + EXYNOS4_GPIO_D07, + EXYNOS4_GPIO_D10, /* 48 0x30 */ + EXYNOS4_GPIO_D11, + EXYNOS4_GPIO_D12, + EXYNOS4_GPIO_D13, + EXYNOS4_GPIO_D14, + EXYNOS4_GPIO_D15, + EXYNOS4_GPIO_D16, + EXYNOS4_GPIO_D17, + EXYNOS4_GPIO_E00, /* 56 0x38 */ + EXYNOS4_GPIO_E01, + EXYNOS4_GPIO_E02, + EXYNOS4_GPIO_E03, + EXYNOS4_GPIO_E04, + EXYNOS4_GPIO_E05, + EXYNOS4_GPIO_E06, + EXYNOS4_GPIO_E07, + EXYNOS4_GPIO_E10, /* 64 0x40 */ + EXYNOS4_GPIO_E11, + EXYNOS4_GPIO_E12, + EXYNOS4_GPIO_E13, + EXYNOS4_GPIO_E14, + EXYNOS4_GPIO_E15, + EXYNOS4_GPIO_E16, + EXYNOS4_GPIO_E17, + EXYNOS4_GPIO_E20, /* 72 0x48 */ + EXYNOS4_GPIO_E21, + EXYNOS4_GPIO_E22, + EXYNOS4_GPIO_E23, + EXYNOS4_GPIO_E24, + EXYNOS4_GPIO_E25, + EXYNOS4_GPIO_E26, + EXYNOS4_GPIO_E27, + EXYNOS4_GPIO_E30, /* 80 0x50 */ + EXYNOS4_GPIO_E31, + EXYNOS4_GPIO_E32, + EXYNOS4_GPIO_E33, + EXYNOS4_GPIO_E34, + EXYNOS4_GPIO_E35, + EXYNOS4_GPIO_E36, + EXYNOS4_GPIO_E37, + EXYNOS4_GPIO_E40, /* 88 0x58 */ + EXYNOS4_GPIO_E41, + EXYNOS4_GPIO_E42, + EXYNOS4_GPIO_E43, + EXYNOS4_GPIO_E44, + EXYNOS4_GPIO_E45, + EXYNOS4_GPIO_E46, + EXYNOS4_GPIO_E47, + EXYNOS4_GPIO_F00, /* 96 0x60 */ + EXYNOS4_GPIO_F01, + EXYNOS4_GPIO_F02, + EXYNOS4_GPIO_F03, + EXYNOS4_GPIO_F04, + EXYNOS4_GPIO_F05, + EXYNOS4_GPIO_F06, + EXYNOS4_GPIO_F07, + EXYNOS4_GPIO_F10, /* 104 0x68 */ + EXYNOS4_GPIO_F11, + EXYNOS4_GPIO_F12, + EXYNOS4_GPIO_F13, + EXYNOS4_GPIO_F14, + EXYNOS4_GPIO_F15, + EXYNOS4_GPIO_F16, + EXYNOS4_GPIO_F17, + EXYNOS4_GPIO_F20, /* 112 0x70 */ + EXYNOS4_GPIO_F21, + EXYNOS4_GPIO_F22, + EXYNOS4_GPIO_F23, + EXYNOS4_GPIO_F24, + EXYNOS4_GPIO_F25, + EXYNOS4_GPIO_F26, + EXYNOS4_GPIO_F27, + EXYNOS4_GPIO_F30, /* 120 0x78 */ + EXYNOS4_GPIO_F31, + EXYNOS4_GPIO_F32, + EXYNOS4_GPIO_F33, + EXYNOS4_GPIO_F34, + EXYNOS4_GPIO_F35, + EXYNOS4_GPIO_F36, + EXYNOS4_GPIO_F37, -#define S5P_GPIO_GET_PART(x) \ - (((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK) + /* GPIO_PART2_STARTS */ + EXYNOS4_GPIO_MAX_PORT_PART_1, /* 128 0x80 */ + EXYNOS4_GPIO_J00 = EXYNOS4_GPIO_MAX_PORT_PART_1, + EXYNOS4_GPIO_J01, + EXYNOS4_GPIO_J02, + EXYNOS4_GPIO_J03, + EXYNOS4_GPIO_J04, + EXYNOS4_GPIO_J05, + EXYNOS4_GPIO_J06, + EXYNOS4_GPIO_J07, + EXYNOS4_GPIO_J10, /* 136 0x88 */ + EXYNOS4_GPIO_J11, + EXYNOS4_GPIO_J12, + EXYNOS4_GPIO_J13, + EXYNOS4_GPIO_J14, + EXYNOS4_GPIO_J15, + EXYNOS4_GPIO_J16, + EXYNOS4_GPIO_J17, + EXYNOS4_GPIO_K00, /* 144 0x90 */ + EXYNOS4_GPIO_K01, + EXYNOS4_GPIO_K02, + EXYNOS4_GPIO_K03, + EXYNOS4_GPIO_K04, + EXYNOS4_GPIO_K05, + EXYNOS4_GPIO_K06, + EXYNOS4_GPIO_K07, + EXYNOS4_GPIO_K10, /* 152 0x98 */ + EXYNOS4_GPIO_K11, + EXYNOS4_GPIO_K12, + EXYNOS4_GPIO_K13, + EXYNOS4_GPIO_K14, + EXYNOS4_GPIO_K15, + EXYNOS4_GPIO_K16, + EXYNOS4_GPIO_K17, + EXYNOS4_GPIO_K20, /* 160 0xA0 */ + EXYNOS4_GPIO_K21, + EXYNOS4_GPIO_K22, + EXYNOS4_GPIO_K23, + EXYNOS4_GPIO_K24, + EXYNOS4_GPIO_K25, + EXYNOS4_GPIO_K26, + EXYNOS4_GPIO_K27, + EXYNOS4_GPIO_K30, /* 168 0xA8 */ + EXYNOS4_GPIO_K31, + EXYNOS4_GPIO_K32, + EXYNOS4_GPIO_K33, + EXYNOS4_GPIO_K34, + EXYNOS4_GPIO_K35, + EXYNOS4_GPIO_K36, + EXYNOS4_GPIO_K37, + EXYNOS4_GPIO_L00, /* 176 0xB0 */ + EXYNOS4_GPIO_L01, + EXYNOS4_GPIO_L02, + EXYNOS4_GPIO_L03, + EXYNOS4_GPIO_L04, + EXYNOS4_GPIO_L05, + EXYNOS4_GPIO_L06, + EXYNOS4_GPIO_L07, + EXYNOS4_GPIO_L10, /* 184 0xB8 */ + EXYNOS4_GPIO_L11, + EXYNOS4_GPIO_L12, + EXYNOS4_GPIO_L13, + EXYNOS4_GPIO_L14, + EXYNOS4_GPIO_L15, + EXYNOS4_GPIO_L16, + EXYNOS4_GPIO_L17, + EXYNOS4_GPIO_L20, /* 192 0xC0 */ + EXYNOS4_GPIO_L21, + EXYNOS4_GPIO_L22, + EXYNOS4_GPIO_L23, + EXYNOS4_GPIO_L24, + EXYNOS4_GPIO_L25, + EXYNOS4_GPIO_L26, + EXYNOS4_GPIO_L27, + EXYNOS4_GPIO_Y00, /* 200 0xC8 */ + EXYNOS4_GPIO_Y01, + EXYNOS4_GPIO_Y02, + EXYNOS4_GPIO_Y03, + EXYNOS4_GPIO_Y04, + EXYNOS4_GPIO_Y05, + EXYNOS4_GPIO_Y06, + EXYNOS4_GPIO_Y07, + EXYNOS4_GPIO_Y10, /* 208 0xD0 */ + EXYNOS4_GPIO_Y11, + EXYNOS4_GPIO_Y12, + EXYNOS4_GPIO_Y13, + EXYNOS4_GPIO_Y14, + EXYNOS4_GPIO_Y15, + EXYNOS4_GPIO_Y16, + EXYNOS4_GPIO_Y17, + EXYNOS4_GPIO_Y20, /* 216 0xD8 */ + EXYNOS4_GPIO_Y21, + EXYNOS4_GPIO_Y22, + EXYNOS4_GPIO_Y23, + EXYNOS4_GPIO_Y24, + EXYNOS4_GPIO_Y25, + EXYNOS4_GPIO_Y26, + EXYNOS4_GPIO_Y27, + EXYNOS4_GPIO_Y30, /* 224 0xE0 */ + EXYNOS4_GPIO_Y31, + EXYNOS4_GPIO_Y32, + EXYNOS4_GPIO_Y33, + EXYNOS4_GPIO_Y34, + EXYNOS4_GPIO_Y35, + EXYNOS4_GPIO_Y36, + EXYNOS4_GPIO_Y37, + EXYNOS4_GPIO_Y40, /* 232 0xE8 */ + EXYNOS4_GPIO_Y41, + EXYNOS4_GPIO_Y42, + EXYNOS4_GPIO_Y43, + EXYNOS4_GPIO_Y44, + EXYNOS4_GPIO_Y45, + EXYNOS4_GPIO_Y46, + EXYNOS4_GPIO_Y47, + EXYNOS4_GPIO_Y50, /* 240 0xF0 */ + EXYNOS4_GPIO_Y51, + EXYNOS4_GPIO_Y52, + EXYNOS4_GPIO_Y53, + EXYNOS4_GPIO_Y54, + EXYNOS4_GPIO_Y55, + EXYNOS4_GPIO_Y56, + EXYNOS4_GPIO_Y57, + EXYNOS4_GPIO_Y60, /* 248 0xF8 */ + EXYNOS4_GPIO_Y61, + EXYNOS4_GPIO_Y62, + EXYNOS4_GPIO_Y63, + EXYNOS4_GPIO_Y64, + EXYNOS4_GPIO_Y65, + EXYNOS4_GPIO_Y66, + EXYNOS4_GPIO_Y67, + EXYNOS4_GPIO_X00 = 896, /* 896 0x380 */ + EXYNOS4_GPIO_X01, + EXYNOS4_GPIO_X02, + EXYNOS4_GPIO_X03, + EXYNOS4_GPIO_X04, + EXYNOS4_GPIO_X05, + EXYNOS4_GPIO_X06, + EXYNOS4_GPIO_X07, + EXYNOS4_GPIO_X10, /* 904 0x388 */ + EXYNOS4_GPIO_X11, + EXYNOS4_GPIO_X12, + EXYNOS4_GPIO_X13, + EXYNOS4_GPIO_X14, + EXYNOS4_GPIO_X15, + EXYNOS4_GPIO_X16, + EXYNOS4_GPIO_X17, + EXYNOS4_GPIO_X20, /* 912 0x390 */ + EXYNOS4_GPIO_X21, + EXYNOS4_GPIO_X22, + EXYNOS4_GPIO_X23, + EXYNOS4_GPIO_X24, + EXYNOS4_GPIO_X25, + EXYNOS4_GPIO_X26, + EXYNOS4_GPIO_X27, + EXYNOS4_GPIO_X30, /* 920 0x398 */ + EXYNOS4_GPIO_X31, + EXYNOS4_GPIO_X32, + EXYNOS4_GPIO_X33, + EXYNOS4_GPIO_X34, + EXYNOS4_GPIO_X35, + EXYNOS4_GPIO_X36, + EXYNOS4_GPIO_X37, -#define S5P_GPIO_SET_PIN(x) \ - ((x) & S5P_GPIO_PIN_MASK) + /* GPIO_PART3_STARTS */ + EXYNOS4_GPIO_MAX_PORT_PART_2, /* 928 0x3A0 */ + EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2, + EXYNOS4_GPIO_Z1, + EXYNOS4_GPIO_Z2, + EXYNOS4_GPIO_Z3, + EXYNOS4_GPIO_Z4, + EXYNOS4_GPIO_Z5, + EXYNOS4_GPIO_Z6, + EXYNOS4_GPIO_Z7, -#define EXYNOS4_GPIO_SET_BANK(part, bank) \ - ((((unsigned)&(((struct exynos4_gpio_part##part *) \ - EXYNOS4_GPIO_PART##part##_BASE)->bank) \ - - EXYNOS4_GPIO_PART##part##_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) + EXYNOS4_GPIO_MAX_PORT +}; -#define EXYNOS4X12_GPIO_SET_BANK(part, bank) \ - ((((unsigned)&(((struct exynos4x12_gpio_part##part *) \ - EXYNOS4X12_GPIO_PART##part##_BASE)->bank) \ - - EXYNOS4X12_GPIO_PART##part##_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) +enum exynos4X12_gpio_pin { + /* GPIO_PART1_STARTS */ + EXYNOS4X12_GPIO_A00, /* 0 */ + EXYNOS4X12_GPIO_A01, + EXYNOS4X12_GPIO_A02, + EXYNOS4X12_GPIO_A03, + EXYNOS4X12_GPIO_A04, + EXYNOS4X12_GPIO_A05, + EXYNOS4X12_GPIO_A06, + EXYNOS4X12_GPIO_A07, + EXYNOS4X12_GPIO_A10, /* 8 */ + EXYNOS4X12_GPIO_A11, + EXYNOS4X12_GPIO_A12, + EXYNOS4X12_GPIO_A13, + EXYNOS4X12_GPIO_A14, + EXYNOS4X12_GPIO_A15, + EXYNOS4X12_GPIO_A16, + EXYNOS4X12_GPIO_A17, + EXYNOS4X12_GPIO_B0, /* 16 0x10 */ + EXYNOS4X12_GPIO_B1, + EXYNOS4X12_GPIO_B2, + EXYNOS4X12_GPIO_B3, + EXYNOS4X12_GPIO_B4, + EXYNOS4X12_GPIO_B5, + EXYNOS4X12_GPIO_B6, + EXYNOS4X12_GPIO_B7, + EXYNOS4X12_GPIO_C00, /* 24 0x18 */ + EXYNOS4X12_GPIO_C01, + EXYNOS4X12_GPIO_C02, + EXYNOS4X12_GPIO_C03, + EXYNOS4X12_GPIO_C04, + EXYNOS4X12_GPIO_C05, + EXYNOS4X12_GPIO_C06, + EXYNOS4X12_GPIO_C07, + EXYNOS4X12_GPIO_C10, /* 32 0x20 */ + EXYNOS4X12_GPIO_C11, + EXYNOS4X12_GPIO_C12, + EXYNOS4X12_GPIO_C13, + EXYNOS4X12_GPIO_C14, + EXYNOS4X12_GPIO_C15, + EXYNOS4X12_GPIO_C16, + EXYNOS4X12_GPIO_C17, + EXYNOS4X12_GPIO_D00, /* 40 0x28 */ + EXYNOS4X12_GPIO_D01, + EXYNOS4X12_GPIO_D02, + EXYNOS4X12_GPIO_D03, + EXYNOS4X12_GPIO_D04, + EXYNOS4X12_GPIO_D05, + EXYNOS4X12_GPIO_D06, + EXYNOS4X12_GPIO_D07, + EXYNOS4X12_GPIO_D10, /* 48 0x30 */ + EXYNOS4X12_GPIO_D11, + EXYNOS4X12_GPIO_D12, + EXYNOS4X12_GPIO_D13, + EXYNOS4X12_GPIO_D14, + EXYNOS4X12_GPIO_D15, + EXYNOS4X12_GPIO_D16, + EXYNOS4X12_GPIO_D17, + EXYNOS4X12_GPIO_F00 = 96, /* 96 0x60 */ + EXYNOS4X12_GPIO_F01, + EXYNOS4X12_GPIO_F02, + EXYNOS4X12_GPIO_F03, + EXYNOS4X12_GPIO_F04, + EXYNOS4X12_GPIO_F05, + EXYNOS4X12_GPIO_F06, + EXYNOS4X12_GPIO_F07, + EXYNOS4X12_GPIO_F10, /* 104 0x68 */ + EXYNOS4X12_GPIO_F11, + EXYNOS4X12_GPIO_F12, + EXYNOS4X12_GPIO_F13, + EXYNOS4X12_GPIO_F14, + EXYNOS4X12_GPIO_F15, + EXYNOS4X12_GPIO_F16, + EXYNOS4X12_GPIO_F17, + EXYNOS4X12_GPIO_F20, /* 112 0x70 */ + EXYNOS4X12_GPIO_F21, + EXYNOS4X12_GPIO_F22, + EXYNOS4X12_GPIO_F23, + EXYNOS4X12_GPIO_F24, + EXYNOS4X12_GPIO_F25, + EXYNOS4X12_GPIO_F26, + EXYNOS4X12_GPIO_F27, + EXYNOS4X12_GPIO_F30, /* 120 0x78 */ + EXYNOS4X12_GPIO_F31, + EXYNOS4X12_GPIO_F32, + EXYNOS4X12_GPIO_F33, + EXYNOS4X12_GPIO_F34, + EXYNOS4X12_GPIO_F35, + EXYNOS4X12_GPIO_F36, + EXYNOS4X12_GPIO_F37, + EXYNOS4X12_GPIO_J00 = 144, /* 144 0x90 */ + EXYNOS4X12_GPIO_J01, + EXYNOS4X12_GPIO_J02, + EXYNOS4X12_GPIO_J03, + EXYNOS4X12_GPIO_J04, + EXYNOS4X12_GPIO_J05, + EXYNOS4X12_GPIO_J06, + EXYNOS4X12_GPIO_J07, + EXYNOS4X12_GPIO_J10, /* 152 0x98 */ + EXYNOS4X12_GPIO_J11, + EXYNOS4X12_GPIO_J12, + EXYNOS4X12_GPIO_J13, + EXYNOS4X12_GPIO_J14, + EXYNOS4X12_GPIO_J15, + EXYNOS4X12_GPIO_J16, + EXYNOS4X12_GPIO_J17, -#define EXYNOS5_GPIO_SET_BANK(part, bank) \ - ((((unsigned)&(((struct exynos5420_gpio_part##part *) \ - EXYNOS5420_GPIO_PART##part##_BASE)->bank) \ - - EXYNOS5_GPIO_PART##part##_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) + /* GPIO_PART2_STARTS */ + EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 160 0xA0 */ + EXYNOS4X12_GPIO_K00 = 176, /* 176 0xB0 */ + EXYNOS4X12_GPIO_K01, + EXYNOS4X12_GPIO_K02, + EXYNOS4X12_GPIO_K03, + EXYNOS4X12_GPIO_K04, + EXYNOS4X12_GPIO_K05, + EXYNOS4X12_GPIO_K06, + EXYNOS4X12_GPIO_K07, + EXYNOS4X12_GPIO_K10, /* 184 0xB8 */ + EXYNOS4X12_GPIO_K11, + EXYNOS4X12_GPIO_K12, + EXYNOS4X12_GPIO_K13, + EXYNOS4X12_GPIO_K14, + EXYNOS4X12_GPIO_K15, + EXYNOS4X12_GPIO_K16, + EXYNOS4X12_GPIO_K17, + EXYNOS4X12_GPIO_K20, /* 192 0xC0 */ + EXYNOS4X12_GPIO_K21, + EXYNOS4X12_GPIO_K22, + EXYNOS4X12_GPIO_K23, + EXYNOS4X12_GPIO_K24, + EXYNOS4X12_GPIO_K25, + EXYNOS4X12_GPIO_K26, + EXYNOS4X12_GPIO_K27, + EXYNOS4X12_GPIO_K30, /* 200 0xC8 */ + EXYNOS4X12_GPIO_K31, + EXYNOS4X12_GPIO_K32, + EXYNOS4X12_GPIO_K33, + EXYNOS4X12_GPIO_K34, + EXYNOS4X12_GPIO_K35, + EXYNOS4X12_GPIO_K36, + EXYNOS4X12_GPIO_K37, + EXYNOS4X12_GPIO_L00, /* 208 0xD0 */ + EXYNOS4X12_GPIO_L01, + EXYNOS4X12_GPIO_L02, + EXYNOS4X12_GPIO_L03, + EXYNOS4X12_GPIO_L04, + EXYNOS4X12_GPIO_L05, + EXYNOS4X12_GPIO_L06, + EXYNOS4X12_GPIO_L07, + EXYNOS4X12_GPIO_L10, /* 216 0xD8 */ + EXYNOS4X12_GPIO_L11, + EXYNOS4X12_GPIO_L12, + EXYNOS4X12_GPIO_L13, + EXYNOS4X12_GPIO_L14, + EXYNOS4X12_GPIO_L15, + EXYNOS4X12_GPIO_L16, + EXYNOS4X12_GPIO_L17, + EXYNOS4X12_GPIO_L20, /* 224 0xE0 */ + EXYNOS4X12_GPIO_L21, + EXYNOS4X12_GPIO_L22, + EXYNOS4X12_GPIO_L23, + EXYNOS4X12_GPIO_L24, + EXYNOS4X12_GPIO_L25, + EXYNOS4X12_GPIO_L26, + EXYNOS4X12_GPIO_L27, + EXYNOS4X12_GPIO_Y00, /* 232 0xE8 */ + EXYNOS4X12_GPIO_Y01, + EXYNOS4X12_GPIO_Y02, + EXYNOS4X12_GPIO_Y03, + EXYNOS4X12_GPIO_Y04, + EXYNOS4X12_GPIO_Y05, + EXYNOS4X12_GPIO_Y06, + EXYNOS4X12_GPIO_Y07, + EXYNOS4X12_GPIO_Y10, /* 240 0xF0 */ + EXYNOS4X12_GPIO_Y11, + EXYNOS4X12_GPIO_Y12, + EXYNOS4X12_GPIO_Y13, + EXYNOS4X12_GPIO_Y14, + EXYNOS4X12_GPIO_Y15, + EXYNOS4X12_GPIO_Y16, + EXYNOS4X12_GPIO_Y17, + EXYNOS4X12_GPIO_Y20, /* 248 0xF8 */ + EXYNOS4X12_GPIO_Y21, + EXYNOS4X12_GPIO_Y22, + EXYNOS4X12_GPIO_Y23, + EXYNOS4X12_GPIO_Y24, + EXYNOS4X12_GPIO_Y25, + EXYNOS4X12_GPIO_Y26, + EXYNOS4X12_GPIO_Y27, + EXYNOS4X12_GPIO_Y30, /* 256 0x100 */ + EXYNOS4X12_GPIO_Y31, + EXYNOS4X12_GPIO_Y32, + EXYNOS4X12_GPIO_Y33, + EXYNOS4X12_GPIO_Y34, + EXYNOS4X12_GPIO_Y35, + EXYNOS4X12_GPIO_Y36, + EXYNOS4X12_GPIO_Y37, + EXYNOS4X12_GPIO_Y40, /* 264 0x108 */ + EXYNOS4X12_GPIO_Y41, + EXYNOS4X12_GPIO_Y42, + EXYNOS4X12_GPIO_Y43, + EXYNOS4X12_GPIO_Y44, + EXYNOS4X12_GPIO_Y45, + EXYNOS4X12_GPIO_Y46, + EXYNOS4X12_GPIO_Y47, + EXYNOS4X12_GPIO_Y50, /* 272 0x110 */ + EXYNOS4X12_GPIO_Y51, + EXYNOS4X12_GPIO_Y52, + EXYNOS4X12_GPIO_Y53, + EXYNOS4X12_GPIO_Y54, + EXYNOS4X12_GPIO_Y55, + EXYNOS4X12_GPIO_Y56, + EXYNOS4X12_GPIO_Y57, + EXYNOS4X12_GPIO_Y60, /* 280 0x118 */ + EXYNOS4X12_GPIO_Y61, + EXYNOS4X12_GPIO_Y62, + EXYNOS4X12_GPIO_Y63, + EXYNOS4X12_GPIO_Y64, + EXYNOS4X12_GPIO_Y65, + EXYNOS4X12_GPIO_Y66, + EXYNOS4X12_GPIO_Y67, + EXYNOS4X12_GPIO_M00 = 312, /* 312 0xF0 */ + EXYNOS4X12_GPIO_M01, + EXYNOS4X12_GPIO_M02, + EXYNOS4X12_GPIO_M03, + EXYNOS4X12_GPIO_M04, + EXYNOS4X12_GPIO_M05, + EXYNOS4X12_GPIO_M06, + EXYNOS4X12_GPIO_M07, + EXYNOS4X12_GPIO_M10, /* 320 0xF8 */ + EXYNOS4X12_GPIO_M11, + EXYNOS4X12_GPIO_M12, + EXYNOS4X12_GPIO_M13, + EXYNOS4X12_GPIO_M14, + EXYNOS4X12_GPIO_M15, + EXYNOS4X12_GPIO_M16, + EXYNOS4X12_GPIO_M17, + EXYNOS4X12_GPIO_M20, /* 328 0x100 */ + EXYNOS4X12_GPIO_M21, + EXYNOS4X12_GPIO_M22, + EXYNOS4X12_GPIO_M23, + EXYNOS4X12_GPIO_M24, + EXYNOS4X12_GPIO_M25, + EXYNOS4X12_GPIO_M26, + EXYNOS4X12_GPIO_M27, + EXYNOS4X12_GPIO_M30, /* 336 0x108 */ + EXYNOS4X12_GPIO_M31, + EXYNOS4X12_GPIO_M32, + EXYNOS4X12_GPIO_M33, + EXYNOS4X12_GPIO_M34, + EXYNOS4X12_GPIO_M35, + EXYNOS4X12_GPIO_M36, + EXYNOS4X12_GPIO_M37, + EXYNOS4X12_GPIO_M40, /* 344 0x110 */ + EXYNOS4X12_GPIO_M41, + EXYNOS4X12_GPIO_M42, + EXYNOS4X12_GPIO_M43, + EXYNOS4X12_GPIO_M44, + EXYNOS4X12_GPIO_M45, + EXYNOS4X12_GPIO_M46, + EXYNOS4X12_GPIO_M47, + EXYNOS4X12_GPIO_X00 = 928, /* 928 0x3A0 */ + EXYNOS4X12_GPIO_X01, + EXYNOS4X12_GPIO_X02, + EXYNOS4X12_GPIO_X03, + EXYNOS4X12_GPIO_X04, + EXYNOS4X12_GPIO_X05, + EXYNOS4X12_GPIO_X06, + EXYNOS4X12_GPIO_X07, + EXYNOS4X12_GPIO_X10, /* 936 0x3A8 */ + EXYNOS4X12_GPIO_X11, + EXYNOS4X12_GPIO_X12, + EXYNOS4X12_GPIO_X13, + EXYNOS4X12_GPIO_X14, + EXYNOS4X12_GPIO_X15, + EXYNOS4X12_GPIO_X16, + EXYNOS4X12_GPIO_X17, + EXYNOS4X12_GPIO_X20, /* 944 0x3B0 */ + EXYNOS4X12_GPIO_X21, + EXYNOS4X12_GPIO_X22, + EXYNOS4X12_GPIO_X23, + EXYNOS4X12_GPIO_X24, + EXYNOS4X12_GPIO_X25, + EXYNOS4X12_GPIO_X26, + EXYNOS4X12_GPIO_X27, + EXYNOS4X12_GPIO_X30, /* 952 0x3B8 */ + EXYNOS4X12_GPIO_X31, + EXYNOS4X12_GPIO_X32, + EXYNOS4X12_GPIO_X33, + EXYNOS4X12_GPIO_X34, + EXYNOS4X12_GPIO_X35, + EXYNOS4X12_GPIO_X36, + EXYNOS4X12_GPIO_X37, -#define EXYNOS5420_GPIO_SET_BANK(part, bank) \ - ((((unsigned)&(((struct exynos5420_gpio_part##part *) \ - EXYNOS5420_GPIO_PART##part##_BASE)->bank) \ - - EXYNOS5420_GPIO_PART##part##_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) + /* GPIO_PART3_STARTS */ + EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 960 0x3C0 */ + EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2, + EXYNOS4X12_GPIO_Z1, + EXYNOS4X12_GPIO_Z2, + EXYNOS4X12_GPIO_Z3, + EXYNOS4X12_GPIO_Z4, + EXYNOS4X12_GPIO_Z5, + EXYNOS4X12_GPIO_Z6, + EXYNOS4X12_GPIO_Z7, -#define exynos4_gpio_get(part, bank, pin) \ - (S5P_GPIO_SET_PART(part) | \ - EXYNOS4_GPIO_SET_BANK(part, bank) | \ - S5P_GPIO_SET_PIN(pin)) + /* GPIO_PART4_STARTS */ + EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 968 0x3C8 */ + EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3, + EXYNOS4X12_GPIO_V01, + EXYNOS4X12_GPIO_V02, + EXYNOS4X12_GPIO_V03, + EXYNOS4X12_GPIO_V04, + EXYNOS4X12_GPIO_V05, + EXYNOS4X12_GPIO_V06, + EXYNOS4X12_GPIO_V07, + EXYNOS4X12_GPIO_V10, /* 976 0x3D0 */ + EXYNOS4X12_GPIO_V11, + EXYNOS4X12_GPIO_V12, + EXYNOS4X12_GPIO_V13, + EXYNOS4X12_GPIO_V14, + EXYNOS4X12_GPIO_V15, + EXYNOS4X12_GPIO_V16, + EXYNOS4X12_GPIO_V17, + EXYNOS4X12_GPIO_V20 = 992, /* 992 0x3E0 */ + EXYNOS4X12_GPIO_V21, + EXYNOS4X12_GPIO_V22, + EXYNOS4X12_GPIO_V23, + EXYNOS4X12_GPIO_V24, + EXYNOS4X12_GPIO_V25, + EXYNOS4X12_GPIO_V26, + EXYNOS4X12_GPIO_V27, + EXYNOS4X12_GPIO_V30 = 1000, /* 1000 0x3E8 */ + EXYNOS4X12_GPIO_V31, + EXYNOS4X12_GPIO_V32, + EXYNOS4X12_GPIO_V33, + EXYNOS4X12_GPIO_V34, + EXYNOS4X12_GPIO_V35, + EXYNOS4X12_GPIO_V36, + EXYNOS4X12_GPIO_V37, + EXYNOS4X12_GPIO_V40 = 1016, /* 1016 0x3F8 */ + EXYNOS4X12_GPIO_V41, + EXYNOS4X12_GPIO_V42, + EXYNOS4X12_GPIO_V43, + EXYNOS4X12_GPIO_V44, + EXYNOS4X12_GPIO_V45, + EXYNOS4X12_GPIO_V46, + EXYNOS4X12_GPIO_V47, -#define exynos4x12_gpio_get(part, bank, pin) \ - (S5P_GPIO_SET_PART(part) | \ - EXYNOS4X12_GPIO_SET_BANK(part, bank) | \ - S5P_GPIO_SET_PIN(pin)) + EXYNOS4X12_GPIO_MAX_PORT +}; -#define exynos5420_gpio_get(part, bank, pin) \ - (S5P_GPIO_SET_PART(part) | \ - EXYNOS5420_GPIO_SET_BANK(part, bank) | \ - S5P_GPIO_SET_PIN(pin)) +enum exynos5_gpio_pin { + /* GPIO_PART1_STARTS */ + EXYNOS5_GPIO_A00, /* 0 */ + EXYNOS5_GPIO_A01, + EXYNOS5_GPIO_A02, + EXYNOS5_GPIO_A03, + EXYNOS5_GPIO_A04, + EXYNOS5_GPIO_A05, + EXYNOS5_GPIO_A06, + EXYNOS5_GPIO_A07, + EXYNOS5_GPIO_A10, /* 8 */ + EXYNOS5_GPIO_A11, + EXYNOS5_GPIO_A12, + EXYNOS5_GPIO_A13, + EXYNOS5_GPIO_A14, + EXYNOS5_GPIO_A15, + EXYNOS5_GPIO_A16, + EXYNOS5_GPIO_A17, + EXYNOS5_GPIO_A20, /* 16 0x10 */ + EXYNOS5_GPIO_A21, + EXYNOS5_GPIO_A22, + EXYNOS5_GPIO_A23, + EXYNOS5_GPIO_A24, + EXYNOS5_GPIO_A25, + EXYNOS5_GPIO_A26, + EXYNOS5_GPIO_A27, + EXYNOS5_GPIO_B00, /* 24 0x18 */ + EXYNOS5_GPIO_B01, + EXYNOS5_GPIO_B02, + EXYNOS5_GPIO_B03, + EXYNOS5_GPIO_B04, + EXYNOS5_GPIO_B05, + EXYNOS5_GPIO_B06, + EXYNOS5_GPIO_B07, + EXYNOS5_GPIO_B10, /* 32 0x20 */ + EXYNOS5_GPIO_B11, + EXYNOS5_GPIO_B12, + EXYNOS5_GPIO_B13, + EXYNOS5_GPIO_B14, + EXYNOS5_GPIO_B15, + EXYNOS5_GPIO_B16, + EXYNOS5_GPIO_B17, + EXYNOS5_GPIO_B20, /* 40 0x28 */ + EXYNOS5_GPIO_B21, + EXYNOS5_GPIO_B22, + EXYNOS5_GPIO_B23, + EXYNOS5_GPIO_B24, + EXYNOS5_GPIO_B25, + EXYNOS5_GPIO_B26, + EXYNOS5_GPIO_B27, + EXYNOS5_GPIO_B30, /* 48 0x39 */ + EXYNOS5_GPIO_B31, + EXYNOS5_GPIO_B32, + EXYNOS5_GPIO_B33, + EXYNOS5_GPIO_B34, + EXYNOS5_GPIO_B35, + EXYNOS5_GPIO_B36, + EXYNOS5_GPIO_B37, + EXYNOS5_GPIO_C00, /* 56 0x38 */ + EXYNOS5_GPIO_C01, + EXYNOS5_GPIO_C02, + EXYNOS5_GPIO_C03, + EXYNOS5_GPIO_C04, + EXYNOS5_GPIO_C05, + EXYNOS5_GPIO_C06, + EXYNOS5_GPIO_C07, + EXYNOS5_GPIO_C10, /* 64 0x40 */ + EXYNOS5_GPIO_C11, + EXYNOS5_GPIO_C12, + EXYNOS5_GPIO_C13, + EXYNOS5_GPIO_C14, + EXYNOS5_GPIO_C15, + EXYNOS5_GPIO_C16, + EXYNOS5_GPIO_C17, + EXYNOS5_GPIO_C20, /* 72 0x48 */ + EXYNOS5_GPIO_C21, + EXYNOS5_GPIO_C22, + EXYNOS5_GPIO_C23, + EXYNOS5_GPIO_C24, + EXYNOS5_GPIO_C25, + EXYNOS5_GPIO_C26, + EXYNOS5_GPIO_C27, + EXYNOS5_GPIO_C30, /* 80 0x50 */ + EXYNOS5_GPIO_C31, + EXYNOS5_GPIO_C32, + EXYNOS5_GPIO_C33, + EXYNOS5_GPIO_C34, + EXYNOS5_GPIO_C35, + EXYNOS5_GPIO_C36, + EXYNOS5_GPIO_C37, + EXYNOS5_GPIO_D00, /* 88 0x58 */ + EXYNOS5_GPIO_D01, + EXYNOS5_GPIO_D02, + EXYNOS5_GPIO_D03, + EXYNOS5_GPIO_D04, + EXYNOS5_GPIO_D05, + EXYNOS5_GPIO_D06, + EXYNOS5_GPIO_D07, + EXYNOS5_GPIO_D10, /* 96 0x60 */ + EXYNOS5_GPIO_D11, + EXYNOS5_GPIO_D12, + EXYNOS5_GPIO_D13, + EXYNOS5_GPIO_D14, + EXYNOS5_GPIO_D15, + EXYNOS5_GPIO_D16, + EXYNOS5_GPIO_D17, + EXYNOS5_GPIO_Y00, /* 104 0x68 */ + EXYNOS5_GPIO_Y01, + EXYNOS5_GPIO_Y02, + EXYNOS5_GPIO_Y03, + EXYNOS5_GPIO_Y04, + EXYNOS5_GPIO_Y05, + EXYNOS5_GPIO_Y06, + EXYNOS5_GPIO_Y07, + EXYNOS5_GPIO_Y10, /* 112 0x70 */ + EXYNOS5_GPIO_Y11, + EXYNOS5_GPIO_Y12, + EXYNOS5_GPIO_Y13, + EXYNOS5_GPIO_Y14, + EXYNOS5_GPIO_Y15, + EXYNOS5_GPIO_Y16, + EXYNOS5_GPIO_Y17, + EXYNOS5_GPIO_Y20, /* 120 0x78 */ + EXYNOS5_GPIO_Y21, + EXYNOS5_GPIO_Y22, + EXYNOS5_GPIO_Y23, + EXYNOS5_GPIO_Y24, + EXYNOS5_GPIO_Y25, + EXYNOS5_GPIO_Y26, + EXYNOS5_GPIO_Y27, + EXYNOS5_GPIO_Y30, /* 128 0x80 */ + EXYNOS5_GPIO_Y31, + EXYNOS5_GPIO_Y32, + EXYNOS5_GPIO_Y33, + EXYNOS5_GPIO_Y34, + EXYNOS5_GPIO_Y35, + EXYNOS5_GPIO_Y36, + EXYNOS5_GPIO_Y37, + EXYNOS5_GPIO_Y40, /* 136 0x88 */ + EXYNOS5_GPIO_Y41, + EXYNOS5_GPIO_Y42, + EXYNOS5_GPIO_Y43, + EXYNOS5_GPIO_Y44, + EXYNOS5_GPIO_Y45, + EXYNOS5_GPIO_Y46, + EXYNOS5_GPIO_Y47, + EXYNOS5_GPIO_Y50, /* 144 0x90 */ + EXYNOS5_GPIO_Y51, + EXYNOS5_GPIO_Y52, + EXYNOS5_GPIO_Y53, + EXYNOS5_GPIO_Y54, + EXYNOS5_GPIO_Y55, + EXYNOS5_GPIO_Y56, + EXYNOS5_GPIO_Y57, + EXYNOS5_GPIO_Y60, /* 152 0x98 */ + EXYNOS5_GPIO_Y61, + EXYNOS5_GPIO_Y62, + EXYNOS5_GPIO_Y63, + EXYNOS5_GPIO_Y64, + EXYNOS5_GPIO_Y65, + EXYNOS5_GPIO_Y66, + EXYNOS5_GPIO_Y67, -#define exynos5_gpio_get(part, bank, pin) \ - (S5P_GPIO_SET_PART(part) | \ - EXYNOS5_GPIO_SET_BANK(part, bank) | \ - S5P_GPIO_SET_PIN(pin)) + /* GPIO_PART2_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_1, /* 160 0xa0 */ + EXYNOS5_GPIO_C40 = EXYNOS5_GPIO_MAX_PORT_PART_1, + EXYNOS5_GPIO_C41, + EXYNOS5_GPIO_C42, + EXYNOS5_GPIO_C43, + EXYNOS5_GPIO_C44, + EXYNOS5_GPIO_C45, + EXYNOS5_GPIO_C46, + EXYNOS5_GPIO_C47, -static inline unsigned int s5p_gpio_base(int gpio) + /* GPIO_PART3_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_2, /* 168 0xa8 */ + EXYNOS5_GPIO_X00 = EXYNOS5_GPIO_MAX_PORT_PART_2, + EXYNOS5_GPIO_X01, + EXYNOS5_GPIO_X02, + EXYNOS5_GPIO_X03, + EXYNOS5_GPIO_X04, + EXYNOS5_GPIO_X05, + EXYNOS5_GPIO_X06, + EXYNOS5_GPIO_X07, + EXYNOS5_GPIO_X10, /* 176 0xb0 */ + EXYNOS5_GPIO_X11, + EXYNOS5_GPIO_X12, + EXYNOS5_GPIO_X13, + EXYNOS5_GPIO_X14, + EXYNOS5_GPIO_X15, + EXYNOS5_GPIO_X16, + EXYNOS5_GPIO_X17, + EXYNOS5_GPIO_X20, /* 184 0xb8 */ + EXYNOS5_GPIO_X21, + EXYNOS5_GPIO_X22, + EXYNOS5_GPIO_X23, + EXYNOS5_GPIO_X24, + EXYNOS5_GPIO_X25, + EXYNOS5_GPIO_X26, + EXYNOS5_GPIO_X27, + EXYNOS5_GPIO_X30, /* 192 0xc0 */ + EXYNOS5_GPIO_X31, + EXYNOS5_GPIO_X32, + EXYNOS5_GPIO_X33, + EXYNOS5_GPIO_X34, + EXYNOS5_GPIO_X35, + EXYNOS5_GPIO_X36, + EXYNOS5_GPIO_X37, + + /* GPIO_PART4_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_3, /* 200 0xc8 */ + EXYNOS5_GPIO_E00 = EXYNOS5_GPIO_MAX_PORT_PART_3, + EXYNOS5_GPIO_E01, + EXYNOS5_GPIO_E02, + EXYNOS5_GPIO_E03, + EXYNOS5_GPIO_E04, + EXYNOS5_GPIO_E05, + EXYNOS5_GPIO_E06, + EXYNOS5_GPIO_E07, + EXYNOS5_GPIO_E10, /* 208 0xd0 */ + EXYNOS5_GPIO_E11, + EXYNOS5_GPIO_E12, + EXYNOS5_GPIO_E13, + EXYNOS5_GPIO_E14, + EXYNOS5_GPIO_E15, + EXYNOS5_GPIO_E16, + EXYNOS5_GPIO_E17, + EXYNOS5_GPIO_F00, /* 216 0xd8 */ + EXYNOS5_GPIO_F01, + EXYNOS5_GPIO_F02, + EXYNOS5_GPIO_F03, + EXYNOS5_GPIO_F04, + EXYNOS5_GPIO_F05, + EXYNOS5_GPIO_F06, + EXYNOS5_GPIO_F07, + EXYNOS5_GPIO_F10, /* 224 0xe0 */ + EXYNOS5_GPIO_F11, + EXYNOS5_GPIO_F12, + EXYNOS5_GPIO_F13, + EXYNOS5_GPIO_F14, + EXYNOS5_GPIO_F15, + EXYNOS5_GPIO_F16, + EXYNOS5_GPIO_F17, + EXYNOS5_GPIO_G00, /* 232 0xe8 */ + EXYNOS5_GPIO_G01, + EXYNOS5_GPIO_G02, + EXYNOS5_GPIO_G03, + EXYNOS5_GPIO_G04, + EXYNOS5_GPIO_G05, + EXYNOS5_GPIO_G06, + EXYNOS5_GPIO_G07, + EXYNOS5_GPIO_G10, /* 240 0xf0 */ + EXYNOS5_GPIO_G11, + EXYNOS5_GPIO_G12, + EXYNOS5_GPIO_G13, + EXYNOS5_GPIO_G14, + EXYNOS5_GPIO_G15, + EXYNOS5_GPIO_G16, + EXYNOS5_GPIO_G17, + EXYNOS5_GPIO_G20, /* 248 0xf8 */ + EXYNOS5_GPIO_G21, + EXYNOS5_GPIO_G22, + EXYNOS5_GPIO_G23, + EXYNOS5_GPIO_G24, + EXYNOS5_GPIO_G25, + EXYNOS5_GPIO_G26, + EXYNOS5_GPIO_G27, + EXYNOS5_GPIO_H00, /* 256 0x100 */ + EXYNOS5_GPIO_H01, + EXYNOS5_GPIO_H02, + EXYNOS5_GPIO_H03, + EXYNOS5_GPIO_H04, + EXYNOS5_GPIO_H05, + EXYNOS5_GPIO_H06, + EXYNOS5_GPIO_H07, + EXYNOS5_GPIO_H10, /* 264 0x108 */ + EXYNOS5_GPIO_H11, + EXYNOS5_GPIO_H12, + EXYNOS5_GPIO_H13, + EXYNOS5_GPIO_H14, + EXYNOS5_GPIO_H15, + EXYNOS5_GPIO_H16, + EXYNOS5_GPIO_H17, + + /* GPIO_PART4_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_4, /* 272 0x110 */ + EXYNOS5_GPIO_V00 = EXYNOS5_GPIO_MAX_PORT_PART_4, + EXYNOS5_GPIO_V01, + EXYNOS5_GPIO_V02, + EXYNOS5_GPIO_V03, + EXYNOS5_GPIO_V04, + EXYNOS5_GPIO_V05, + EXYNOS5_GPIO_V06, + EXYNOS5_GPIO_V07, + EXYNOS5_GPIO_V10, /* 280 0x118 */ + EXYNOS5_GPIO_V11, + EXYNOS5_GPIO_V12, + EXYNOS5_GPIO_V13, + EXYNOS5_GPIO_V14, + EXYNOS5_GPIO_V15, + EXYNOS5_GPIO_V16, + EXYNOS5_GPIO_V17, + + /* GPIO_PART5_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_5, /* 288 0x120 */ + EXYNOS5_GPIO_V20 = EXYNOS5_GPIO_MAX_PORT_PART_5, + EXYNOS5_GPIO_V21, + EXYNOS5_GPIO_V22, + EXYNOS5_GPIO_V23, + EXYNOS5_GPIO_V24, + EXYNOS5_GPIO_V25, + EXYNOS5_GPIO_V26, + EXYNOS5_GPIO_V27, + EXYNOS5_GPIO_V30, /* 296 0x128 */ + EXYNOS5_GPIO_V31, + EXYNOS5_GPIO_V32, + EXYNOS5_GPIO_V33, + EXYNOS5_GPIO_V34, + EXYNOS5_GPIO_V35, + EXYNOS5_GPIO_V36, + EXYNOS5_GPIO_V37, + + /* GPIO_PART6_STARTS */ + EXYNOS5_GPIO_MAX_PORT_PART_6, /* 304 0x130 */ + EXYNOS5_GPIO_V40 = EXYNOS5_GPIO_MAX_PORT_PART_6, + EXYNOS5_GPIO_V41, + EXYNOS5_GPIO_V42, + EXYNOS5_GPIO_V43, + EXYNOS5_GPIO_V44, + EXYNOS5_GPIO_V45, + EXYNOS5_GPIO_V46, + EXYNOS5_GPIO_V47, + + /* GPIO_PART7_STARTS */ /* 312 0x138 */ + EXYNOS5_GPIO_MAX_PORT_PART_7, + EXYNOS5_GPIO_Z0 = EXYNOS5_GPIO_MAX_PORT_PART_7, + EXYNOS5_GPIO_Z1, + EXYNOS5_GPIO_Z2, + EXYNOS5_GPIO_Z3, + EXYNOS5_GPIO_Z4, + EXYNOS5_GPIO_Z5, + EXYNOS5_GPIO_Z6, + EXYNOS5_GPIO_MAX_PORT +}; + +enum exynos5420_gpio_pin { + /* GPIO_PART1_STARTS */ + EXYNOS5420_GPIO_A00, /* 0 */ + EXYNOS5420_GPIO_A01, + EXYNOS5420_GPIO_A02, + EXYNOS5420_GPIO_A03, + EXYNOS5420_GPIO_A04, + EXYNOS5420_GPIO_A05, + EXYNOS5420_GPIO_A06, + EXYNOS5420_GPIO_A07, + EXYNOS5420_GPIO_A10, /* 8 */ + EXYNOS5420_GPIO_A11, + EXYNOS5420_GPIO_A12, + EXYNOS5420_GPIO_A13, + EXYNOS5420_GPIO_A14, + EXYNOS5420_GPIO_A15, + EXYNOS5420_GPIO_A16, + EXYNOS5420_GPIO_A17, + EXYNOS5420_GPIO_A20, /* 16 0x10 */ + EXYNOS5420_GPIO_A21, + EXYNOS5420_GPIO_A22, + EXYNOS5420_GPIO_A23, + EXYNOS5420_GPIO_A24, + EXYNOS5420_GPIO_A25, + EXYNOS5420_GPIO_A26, + EXYNOS5420_GPIO_A27, + EXYNOS5420_GPIO_B00, /* 24 0x18 */ + EXYNOS5420_GPIO_B01, + EXYNOS5420_GPIO_B02, + EXYNOS5420_GPIO_B03, + EXYNOS5420_GPIO_B04, + EXYNOS5420_GPIO_B05, + EXYNOS5420_GPIO_B06, + EXYNOS5420_GPIO_B07, + EXYNOS5420_GPIO_B10, /* 32 0x20 */ + EXYNOS5420_GPIO_B11, + EXYNOS5420_GPIO_B12, + EXYNOS5420_GPIO_B13, + EXYNOS5420_GPIO_B14, + EXYNOS5420_GPIO_B15, + EXYNOS5420_GPIO_B16, + EXYNOS5420_GPIO_B17, + EXYNOS5420_GPIO_B20, /* 40 0x28 */ + EXYNOS5420_GPIO_B21, + EXYNOS5420_GPIO_B22, + EXYNOS5420_GPIO_B23, + EXYNOS5420_GPIO_B24, + EXYNOS5420_GPIO_B25, + EXYNOS5420_GPIO_B26, + EXYNOS5420_GPIO_B27, + EXYNOS5420_GPIO_B30, /* 48 0x30 */ + EXYNOS5420_GPIO_B31, + EXYNOS5420_GPIO_B32, + EXYNOS5420_GPIO_B33, + EXYNOS5420_GPIO_B34, + EXYNOS5420_GPIO_B35, + EXYNOS5420_GPIO_B36, + EXYNOS5420_GPIO_B37, + EXYNOS5420_GPIO_B40, /* 56 0x38 */ + EXYNOS5420_GPIO_B41, + EXYNOS5420_GPIO_B42, + EXYNOS5420_GPIO_B43, + EXYNOS5420_GPIO_B44, + EXYNOS5420_GPIO_B45, + EXYNOS5420_GPIO_B46, + EXYNOS5420_GPIO_B47, + EXYNOS5420_GPIO_H00, /* 64 0x40 */ + EXYNOS5420_GPIO_H01, + EXYNOS5420_GPIO_H02, + EXYNOS5420_GPIO_H03, + EXYNOS5420_GPIO_H04, + EXYNOS5420_GPIO_H05, + EXYNOS5420_GPIO_H06, + EXYNOS5420_GPIO_H07, + + /* GPIO PART 2 STARTS*/ + EXYNOS5420_GPIO_MAX_PORT_PART_1,/* 72 0x48 */ + EXYNOS5420_GPIO_Y70 = EXYNOS5420_GPIO_MAX_PORT_PART_1, + EXYNOS5420_GPIO_Y71, + EXYNOS5420_GPIO_Y72, + EXYNOS5420_GPIO_Y73, + EXYNOS5420_GPIO_Y74, + EXYNOS5420_GPIO_Y75, + EXYNOS5420_GPIO_Y76, + EXYNOS5420_GPIO_Y77, + + /* GPIO PART 3 STARTS*/ + EXYNOS5420_GPIO_MAX_PORT_PART_2,/* 80 0x50 */ + EXYNOS5420_GPIO_X00 = EXYNOS5420_GPIO_MAX_PORT_PART_2, + EXYNOS5420_GPIO_X01, + EXYNOS5420_GPIO_X02, + EXYNOS5420_GPIO_X03, + EXYNOS5420_GPIO_X04, + EXYNOS5420_GPIO_X05, + EXYNOS5420_GPIO_X06, + EXYNOS5420_GPIO_X07, + EXYNOS5420_GPIO_X10, /* 88 0x58 */ + EXYNOS5420_GPIO_X11, + EXYNOS5420_GPIO_X12, + EXYNOS5420_GPIO_X13, + EXYNOS5420_GPIO_X14, + EXYNOS5420_GPIO_X15, + EXYNOS5420_GPIO_X16, + EXYNOS5420_GPIO_X17, + EXYNOS5420_GPIO_X20, /* 96 0x60 */ + EXYNOS5420_GPIO_X21, + EXYNOS5420_GPIO_X22, + EXYNOS5420_GPIO_X23, + EXYNOS5420_GPIO_X24, + EXYNOS5420_GPIO_X25, + EXYNOS5420_GPIO_X26, + EXYNOS5420_GPIO_X27, + EXYNOS5420_GPIO_X30, /* 104 0x68 */ + EXYNOS5420_GPIO_X31, + EXYNOS5420_GPIO_X32, + EXYNOS5420_GPIO_X33, + EXYNOS5420_GPIO_X34, + EXYNOS5420_GPIO_X35, + EXYNOS5420_GPIO_X36, + EXYNOS5420_GPIO_X37, + + /* GPIO PART 4 STARTS*/ + EXYNOS5420_GPIO_MAX_PORT_PART_3,/* 112 0x70 */ + EXYNOS5420_GPIO_C00 = EXYNOS5420_GPIO_MAX_PORT_PART_3, + EXYNOS5420_GPIO_C01, + EXYNOS5420_GPIO_C02, + EXYNOS5420_GPIO_C03, + EXYNOS5420_GPIO_C04, + EXYNOS5420_GPIO_C05, + EXYNOS5420_GPIO_C06, + EXYNOS5420_GPIO_C07, + EXYNOS5420_GPIO_C10, /* 120 0x78 */ + EXYNOS5420_GPIO_C11, + EXYNOS5420_GPIO_C12, + EXYNOS5420_GPIO_C13, + EXYNOS5420_GPIO_C14, + EXYNOS5420_GPIO_C15, + EXYNOS5420_GPIO_C16, + EXYNOS5420_GPIO_C17, + EXYNOS5420_GPIO_C20, /* 128 0x80 */ + EXYNOS5420_GPIO_C21, + EXYNOS5420_GPIO_C22, + EXYNOS5420_GPIO_C23, + EXYNOS5420_GPIO_C24, + EXYNOS5420_GPIO_C25, + EXYNOS5420_GPIO_C26, + EXYNOS5420_GPIO_C27, + EXYNOS5420_GPIO_C30, /* 136 0x88 */ + EXYNOS5420_GPIO_C31, + EXYNOS5420_GPIO_C32, + EXYNOS5420_GPIO_C33, + EXYNOS5420_GPIO_C34, + EXYNOS5420_GPIO_C35, + EXYNOS5420_GPIO_C36, + EXYNOS5420_GPIO_C37, + EXYNOS5420_GPIO_C40, /* 144 0x90 */ + EXYNOS5420_GPIO_C41, + EXYNOS5420_GPIO_C42, + EXYNOS5420_GPIO_C43, + EXYNOS5420_GPIO_C44, + EXYNOS5420_GPIO_C45, + EXYNOS5420_GPIO_C46, + EXYNOS5420_GPIO_C47, + EXYNOS5420_GPIO_D10, /* 152 0x98 */ + EXYNOS5420_GPIO_D11, + EXYNOS5420_GPIO_D12, + EXYNOS5420_GPIO_D13, + EXYNOS5420_GPIO_D14, + EXYNOS5420_GPIO_D15, + EXYNOS5420_GPIO_D16, + EXYNOS5420_GPIO_D17, + EXYNOS5420_GPIO_Y00, /* 160 0xa0 */ + EXYNOS5420_GPIO_Y01, + EXYNOS5420_GPIO_Y02, + EXYNOS5420_GPIO_Y03, + EXYNOS5420_GPIO_Y04, + EXYNOS5420_GPIO_Y05, + EXYNOS5420_GPIO_Y06, + EXYNOS5420_GPIO_Y07, + EXYNOS5420_GPIO_Y10, /* 168 0xa8 */ + EXYNOS5420_GPIO_Y11, + EXYNOS5420_GPIO_Y12, + EXYNOS5420_GPIO_Y13, + EXYNOS5420_GPIO_Y14, + EXYNOS5420_GPIO_Y15, + EXYNOS5420_GPIO_Y16, + EXYNOS5420_GPIO_Y17, + EXYNOS5420_GPIO_Y20, /* 176 0xb0 */ + EXYNOS5420_GPIO_Y21, + EXYNOS5420_GPIO_Y22, + EXYNOS5420_GPIO_Y23, + EXYNOS5420_GPIO_Y24, + EXYNOS5420_GPIO_Y25, + EXYNOS5420_GPIO_Y26, + EXYNOS5420_GPIO_Y27, + EXYNOS5420_GPIO_Y30, /* 184 0xb8 */ + EXYNOS5420_GPIO_Y31, + EXYNOS5420_GPIO_Y32, + EXYNOS5420_GPIO_Y33, + EXYNOS5420_GPIO_Y34, + EXYNOS5420_GPIO_Y35, + EXYNOS5420_GPIO_Y36, + EXYNOS5420_GPIO_Y37, + EXYNOS5420_GPIO_Y40, /* 192 0xc0 */ + EXYNOS5420_GPIO_Y41, + EXYNOS5420_GPIO_Y42, + EXYNOS5420_GPIO_Y43, + EXYNOS5420_GPIO_Y44, + EXYNOS5420_GPIO_Y45, + EXYNOS5420_GPIO_Y46, + EXYNOS5420_GPIO_Y47, + EXYNOS5420_GPIO_Y50, /* 200 0xc8 */ + EXYNOS5420_GPIO_Y51, + EXYNOS5420_GPIO_Y52, + EXYNOS5420_GPIO_Y53, + EXYNOS5420_GPIO_Y54, + EXYNOS5420_GPIO_Y55, + EXYNOS5420_GPIO_Y56, + EXYNOS5420_GPIO_Y57, + EXYNOS5420_GPIO_Y60, /* 208 0xd0 */ + EXYNOS5420_GPIO_Y61, + EXYNOS5420_GPIO_Y62, + EXYNOS5420_GPIO_Y63, + EXYNOS5420_GPIO_Y64, + EXYNOS5420_GPIO_Y65, + EXYNOS5420_GPIO_Y66, + EXYNOS5420_GPIO_Y67, + + /* GPIO_PART5_STARTS */ + EXYNOS5420_GPIO_MAX_PORT_PART_4,/* 216 0xd8 */ + EXYNOS5420_GPIO_E00 = EXYNOS5420_GPIO_MAX_PORT_PART_4, + EXYNOS5420_GPIO_E01, + EXYNOS5420_GPIO_E02, + EXYNOS5420_GPIO_E03, + EXYNOS5420_GPIO_E04, + EXYNOS5420_GPIO_E05, + EXYNOS5420_GPIO_E06, + EXYNOS5420_GPIO_E07, + EXYNOS5420_GPIO_E10, /* 224 0xe0 */ + EXYNOS5420_GPIO_E11, + EXYNOS5420_GPIO_E12, + EXYNOS5420_GPIO_E13, + EXYNOS5420_GPIO_E14, + EXYNOS5420_GPIO_E15, + EXYNOS5420_GPIO_E16, + EXYNOS5420_GPIO_E17, + EXYNOS5420_GPIO_F00, /* 232 0xe8 */ + EXYNOS5420_GPIO_F01, + EXYNOS5420_GPIO_F02, + EXYNOS5420_GPIO_F03, + EXYNOS5420_GPIO_F04, + EXYNOS5420_GPIO_F05, + EXYNOS5420_GPIO_F06, + EXYNOS5420_GPIO_F07, + EXYNOS5420_GPIO_F10, /* 240 0xf0 */ + EXYNOS5420_GPIO_F11, + EXYNOS5420_GPIO_F12, + EXYNOS5420_GPIO_F13, + EXYNOS5420_GPIO_F14, + EXYNOS5420_GPIO_F15, + EXYNOS5420_GPIO_F16, + EXYNOS5420_GPIO_F17, + EXYNOS5420_GPIO_G00, /* 248 0xf8 */ + EXYNOS5420_GPIO_G01, + EXYNOS5420_GPIO_G02, + EXYNOS5420_GPIO_G03, + EXYNOS5420_GPIO_G04, + EXYNOS5420_GPIO_G05, + EXYNOS5420_GPIO_G06, + EXYNOS5420_GPIO_G07, + EXYNOS5420_GPIO_G10, /* 256 0x100 */ + EXYNOS5420_GPIO_G11, + EXYNOS5420_GPIO_G12, + EXYNOS5420_GPIO_G13, + EXYNOS5420_GPIO_G14, + EXYNOS5420_GPIO_G15, + EXYNOS5420_GPIO_G16, + EXYNOS5420_GPIO_G17, + EXYNOS5420_GPIO_G20, /* 264 0x108 */ + EXYNOS5420_GPIO_G21, + EXYNOS5420_GPIO_G22, + EXYNOS5420_GPIO_G23, + EXYNOS5420_GPIO_G24, + EXYNOS5420_GPIO_G25, + EXYNOS5420_GPIO_G26, + EXYNOS5420_GPIO_G27, + EXYNOS5420_GPIO_J40, /* 272 0x110 */ + EXYNOS5420_GPIO_J41, + EXYNOS5420_GPIO_J42, + EXYNOS5420_GPIO_J43, + EXYNOS5420_GPIO_J44, + EXYNOS5420_GPIO_J45, + EXYNOS5420_GPIO_J46, + EXYNOS5420_GPIO_J47, + + /* GPIO_PART6_STARTS */ + EXYNOS5420_GPIO_MAX_PORT_PART_5,/* 280 0x118 */ + EXYNOS5420_GPIO_Z0 = EXYNOS5420_GPIO_MAX_PORT_PART_5, + EXYNOS5420_GPIO_Z1, + EXYNOS5420_GPIO_Z2, + EXYNOS5420_GPIO_Z3, + EXYNOS5420_GPIO_Z4, + EXYNOS5420_GPIO_Z5, + EXYNOS5420_GPIO_Z6, + EXYNOS5420_GPIO_MAX_PORT +}; + +struct gpio_info { + unsigned int reg_addr; /* Address of register for this part */ + unsigned int max_gpio; /* Maximum GPIO in this part */ +}; + +#define EXYNOS4_GPIO_NUM_PARTS 3 +static struct gpio_info exynos4_gpio_data[EXYNOS4_GPIO_NUM_PARTS] = { + { EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 }, + { EXYNOS4_GPIO_PART2_BASE, EXYNOS4_GPIO_MAX_PORT_PART_2 }, + { EXYNOS4_GPIO_PART3_BASE, EXYNOS4_GPIO_MAX_PORT }, +}; + +#define EXYNOS4X12_GPIO_NUM_PARTS 4 +static struct gpio_info exynos4x12_gpio_data[EXYNOS4X12_GPIO_NUM_PARTS] = { + { EXYNOS4X12_GPIO_PART1_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_1 }, + { EXYNOS4X12_GPIO_PART2_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_2 }, + { EXYNOS4X12_GPIO_PART3_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_3 }, + { EXYNOS4X12_GPIO_PART4_BASE, EXYNOS4X12_GPIO_MAX_PORT }, +}; + +#define EXYNOS5_GPIO_NUM_PARTS 8 +static struct gpio_info exynos5_gpio_data[EXYNOS5_GPIO_NUM_PARTS] = { + { EXYNOS5_GPIO_PART1_BASE, EXYNOS5_GPIO_MAX_PORT_PART_1 }, + { EXYNOS5_GPIO_PART2_BASE, EXYNOS5_GPIO_MAX_PORT_PART_2 }, + { EXYNOS5_GPIO_PART3_BASE, EXYNOS5_GPIO_MAX_PORT_PART_3 }, + { EXYNOS5_GPIO_PART4_BASE, EXYNOS5_GPIO_MAX_PORT_PART_4 }, + { EXYNOS5_GPIO_PART5_BASE, EXYNOS5_GPIO_MAX_PORT_PART_5 }, + { EXYNOS5_GPIO_PART6_BASE, EXYNOS5_GPIO_MAX_PORT_PART_6 }, + { EXYNOS5_GPIO_PART7_BASE, EXYNOS5_GPIO_MAX_PORT_PART_7 }, + { EXYNOS5_GPIO_PART8_BASE, EXYNOS5_GPIO_MAX_PORT }, +}; + +#define EXYNOS5420_GPIO_NUM_PARTS 6 +static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = { + { EXYNOS5420_GPIO_PART1_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_1 }, + { EXYNOS5420_GPIO_PART2_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_2 }, + { EXYNOS5420_GPIO_PART3_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_3 }, + { EXYNOS5420_GPIO_PART4_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_4 }, + { EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_5 }, + { EXYNOS5420_GPIO_PART6_BASE, EXYNOS5420_GPIO_MAX_PORT }, +}; + +static inline struct gpio_info *get_gpio_data(void) { - unsigned gpio_part = S5P_GPIO_GET_PART(gpio); - - switch (gpio_part) { - case 1: - return samsung_get_base_gpio_part1(); - case 2: - return samsung_get_base_gpio_part2(); - case 3: - return samsung_get_base_gpio_part3(); - case 4: - return samsung_get_base_gpio_part4(); - default: - return 0; + if (cpu_is_exynos5()) { + if (proid_is_exynos5420()) + return exynos5420_gpio_data; + else + return exynos5_gpio_data; + } else if (cpu_is_exynos4()) { + if (proid_is_exynos4412()) + return exynos4x12_gpio_data; + else + return exynos4_gpio_data; } + + return NULL; } + +static inline unsigned int get_bank_num(void) +{ + if (cpu_is_exynos5()) { + if (proid_is_exynos5420()) + return EXYNOS5420_GPIO_NUM_PARTS; + else + return EXYNOS5_GPIO_NUM_PARTS; + } else if (cpu_is_exynos4()) { + if (proid_is_exynos4412()) + return EXYNOS4X12_GPIO_NUM_PARTS; + else + return EXYNOS4_GPIO_NUM_PARTS; + } + + return 0; +} + +/* + * This structure helps mapping symbolic GPIO names into indices from + * exynos5_gpio_pin/exynos5420_gpio_pin enums. + * + * By convention, symbolic GPIO name is defined as follows: + * + * g[p], where + * p is optional + * - a single character bank name, as defined by the SOC + * - a single digit set number + * - bit number within the set (in 0..7 range). + * + * essentially form an octal number of the GPIO pin within the bank + * space. On the 5420 architecture some banks' sets do not start not from zero + * ('d' starts from 1 and 'j' starts from 4). To compensate for that and + * maintain flat number space withoout holes, those banks use offsets to be + * deducted from the pin number. + */ +struct gpio_name_num_table { + char bank; /* bank name symbol */ + unsigned int bank_size; /* total number of pins in the bank */ + char bank_offset; /* offset of the first bank's pin */ + unsigned int base; /* index of the first bank's pin in the enum */ +}; + +#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base } +static const struct gpio_name_num_table exynos4_gpio_table[] = { + GPIO_ENTRY('a', EXYNOS4_GPIO_A00, EXYNOS4_GPIO_B0, 0), + GPIO_ENTRY('b', EXYNOS4_GPIO_B0, EXYNOS4_GPIO_C00, 0), + GPIO_ENTRY('c', EXYNOS4_GPIO_C00, EXYNOS4_GPIO_D00, 0), + GPIO_ENTRY('d', EXYNOS4_GPIO_D00, EXYNOS4_GPIO_E00, 0), + GPIO_ENTRY('e', EXYNOS4_GPIO_E00, EXYNOS4_GPIO_F00, 0), + GPIO_ENTRY('f', EXYNOS4_GPIO_F00, EXYNOS4_GPIO_J00, 0), + GPIO_ENTRY('j', EXYNOS4_GPIO_J00, EXYNOS4_GPIO_K00, 0), + GPIO_ENTRY('k', EXYNOS4_GPIO_K00, EXYNOS4_GPIO_L00, 0), + GPIO_ENTRY('l', EXYNOS4_GPIO_L00, EXYNOS4_GPIO_Y00, 0), + GPIO_ENTRY('y', EXYNOS4_GPIO_Y00, EXYNOS4_GPIO_X00, 0), + GPIO_ENTRY('x', EXYNOS4_GPIO_X00, EXYNOS4_GPIO_Z0, 0), + GPIO_ENTRY('z', EXYNOS4_GPIO_Z0, EXYNOS4_GPIO_MAX_PORT, 0), + { 0 } +}; + +static const struct gpio_name_num_table exynos4x12_gpio_table[] = { + GPIO_ENTRY('a', EXYNOS4X12_GPIO_A00, EXYNOS4X12_GPIO_B0, 0), + GPIO_ENTRY('b', EXYNOS4X12_GPIO_B0, EXYNOS4X12_GPIO_C00, 0), + GPIO_ENTRY('c', EXYNOS4X12_GPIO_C00, EXYNOS4X12_GPIO_D00, 0), + GPIO_ENTRY('d', EXYNOS4X12_GPIO_D00, EXYNOS4X12_GPIO_F00, 0), + GPIO_ENTRY('f', EXYNOS4X12_GPIO_F00, EXYNOS4X12_GPIO_J00, 0), + GPIO_ENTRY('j', EXYNOS4X12_GPIO_J00, EXYNOS4X12_GPIO_K00, 0), + GPIO_ENTRY('k', EXYNOS4X12_GPIO_K00, EXYNOS4X12_GPIO_L00, 0), + GPIO_ENTRY('l', EXYNOS4X12_GPIO_L00, EXYNOS4X12_GPIO_Y00, 0), + GPIO_ENTRY('y', EXYNOS4X12_GPIO_Y00, EXYNOS4X12_GPIO_M00, 0), + GPIO_ENTRY('m', EXYNOS4X12_GPIO_M00, EXYNOS4X12_GPIO_X00, 0), + GPIO_ENTRY('x', EXYNOS4X12_GPIO_X00, EXYNOS4X12_GPIO_Z0, 0), + GPIO_ENTRY('z', EXYNOS4X12_GPIO_Z0, EXYNOS4X12_GPIO_V00, 0), + GPIO_ENTRY('v', EXYNOS4X12_GPIO_V00, EXYNOS4X12_GPIO_MAX_PORT, 0), + { 0 } +}; + +static const struct gpio_name_num_table exynos5_gpio_table[] = { + GPIO_ENTRY('a', EXYNOS5_GPIO_A00, EXYNOS5_GPIO_B00, 0), + GPIO_ENTRY('b', EXYNOS5_GPIO_B00, EXYNOS5_GPIO_C00, 0), + GPIO_ENTRY('c', EXYNOS5_GPIO_C00, EXYNOS5_GPIO_D00, 0), + GPIO_ENTRY('d', EXYNOS5_GPIO_D00, EXYNOS5_GPIO_Y00, 0), + GPIO_ENTRY('y', EXYNOS5_GPIO_Y00, EXYNOS5_GPIO_C40, 0), + GPIO_ENTRY('x', EXYNOS5_GPIO_X00, EXYNOS5_GPIO_E00, 0), + GPIO_ENTRY('e', EXYNOS5_GPIO_E00, EXYNOS5_GPIO_F00, 0), + GPIO_ENTRY('f', EXYNOS5_GPIO_F00, EXYNOS5_GPIO_G00, 0), + GPIO_ENTRY('g', EXYNOS5_GPIO_G00, EXYNOS5_GPIO_H00, 0), + GPIO_ENTRY('h', EXYNOS5_GPIO_H00, EXYNOS5_GPIO_V00, 0), + GPIO_ENTRY('v', EXYNOS5_GPIO_V00, EXYNOS5_GPIO_Z0, 0), + GPIO_ENTRY('z', EXYNOS5_GPIO_Z0, EXYNOS5_GPIO_MAX_PORT, 0), + { 0 } +}; + +static const struct gpio_name_num_table exynos5420_gpio_table[] = { + GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0), + GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0), + GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Y70, 0), + GPIO_ENTRY('x', EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_C00, 0), + GPIO_ENTRY('c', EXYNOS5420_GPIO_C00, EXYNOS5420_GPIO_D10, 0), + GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 010), + GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_E00, 0), + GPIO_ENTRY('e', EXYNOS5420_GPIO_E00, EXYNOS5420_GPIO_F00, 0), + GPIO_ENTRY('f', EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_G00, 0), + GPIO_ENTRY('g', EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_J40, 0), + GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_Z0, 040), + GPIO_ENTRY('z', EXYNOS5420_GPIO_Z0, EXYNOS5420_GPIO_MAX_PORT, 0), + { 0 } +}; + +void gpio_cfg_pin(int gpio, int cfg); +void gpio_set_pull(int gpio, int mode); +void gpio_set_drv(int gpio, int mode); +int gpio_direction_output(unsigned gpio, int value); +int gpio_set_value(unsigned gpio, int value); +int gpio_get_value(unsigned gpio); +void gpio_set_rate(int gpio, int mode); +struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio); +int s5p_gpio_get_pin(unsigned gpio); #endif /* Pin configurations */ -#define GPIO_INPUT 0x0 -#define GPIO_OUTPUT 0x1 -#define GPIO_IRQ 0xf -#define GPIO_FUNC(x) (x) +#define S5P_GPIO_INPUT 0x0 +#define S5P_GPIO_OUTPUT 0x1 +#define S5P_GPIO_IRQ 0xf +#define S5P_GPIO_FUNC(x) (x) /* Pull mode */ -#define GPIO_PULL_NONE 0x0 -#define GPIO_PULL_DOWN 0x1 -#define GPIO_PULL_UP 0x3 +#define S5P_GPIO_PULL_NONE 0x0 +#define S5P_GPIO_PULL_DOWN 0x1 +#define S5P_GPIO_PULL_UP 0x3 /* Drive Strength level */ -#define GPIO_DRV_1X 0x0 -#define GPIO_DRV_3X 0x1 -#define GPIO_DRV_2X 0x2 -#define GPIO_DRV_4X 0x3 -#define GPIO_DRV_FAST 0x0 -#define GPIO_DRV_SLOW 0x1 +#define S5P_GPIO_DRV_1X 0x0 +#define S5P_GPIO_DRV_3X 0x1 +#define S5P_GPIO_DRV_2X 0x2 +#define S5P_GPIO_DRV_4X 0x3 +#define S5P_GPIO_DRV_FAST 0x0 +#define S5P_GPIO_DRV_SLOW 0x1 #endif diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h index da8df74a10..d5dbc22c18 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h +++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h @@ -19,170 +19,830 @@ struct s5p_gpio_bank { unsigned char res1[8]; }; -struct s5pc100_gpio { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank b; - struct s5p_gpio_bank c; - struct s5p_gpio_bank d; - struct s5p_gpio_bank e0; - struct s5p_gpio_bank e1; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank f2; - struct s5p_gpio_bank f3; - struct s5p_gpio_bank g0; - struct s5p_gpio_bank g1; - struct s5p_gpio_bank g2; - struct s5p_gpio_bank g3; - struct s5p_gpio_bank i; - struct s5p_gpio_bank j0; - struct s5p_gpio_bank j1; - struct s5p_gpio_bank j2; - struct s5p_gpio_bank j3; - struct s5p_gpio_bank j4; - struct s5p_gpio_bank k0; - struct s5p_gpio_bank k1; - struct s5p_gpio_bank k2; - struct s5p_gpio_bank k3; - struct s5p_gpio_bank l0; - struct s5p_gpio_bank l1; - struct s5p_gpio_bank l2; - struct s5p_gpio_bank l3; - struct s5p_gpio_bank l4; - struct s5p_gpio_bank h0; - struct s5p_gpio_bank h1; - struct s5p_gpio_bank h2; - struct s5p_gpio_bank h3; +/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */ +enum s5pc100_gpio_pin { + S5PC100_GPIO_A00, + S5PC100_GPIO_A01, + S5PC100_GPIO_A02, + S5PC100_GPIO_A03, + S5PC100_GPIO_A04, + S5PC100_GPIO_A05, + S5PC100_GPIO_A06, + S5PC100_GPIO_A07, + S5PC100_GPIO_A10, + S5PC100_GPIO_A11, + S5PC100_GPIO_A12, + S5PC100_GPIO_A13, + S5PC100_GPIO_A14, + S5PC100_GPIO_A15, + S5PC100_GPIO_A16, + S5PC100_GPIO_A17, + S5PC100_GPIO_B0, + S5PC100_GPIO_B1, + S5PC100_GPIO_B2, + S5PC100_GPIO_B3, + S5PC100_GPIO_B4, + S5PC100_GPIO_B5, + S5PC100_GPIO_B6, + S5PC100_GPIO_B7, + S5PC100_GPIO_C0, + S5PC100_GPIO_C1, + S5PC100_GPIO_C2, + S5PC100_GPIO_C3, + S5PC100_GPIO_C4, + S5PC100_GPIO_C5, + S5PC100_GPIO_C6, + S5PC100_GPIO_C7, + S5PC100_GPIO_D0, + S5PC100_GPIO_D1, + S5PC100_GPIO_D2, + S5PC100_GPIO_D3, + S5PC100_GPIO_D4, + S5PC100_GPIO_D5, + S5PC100_GPIO_D6, + S5PC100_GPIO_D7, + S5PC100_GPIO_E00, + S5PC100_GPIO_E01, + S5PC100_GPIO_E02, + S5PC100_GPIO_E03, + S5PC100_GPIO_E04, + S5PC100_GPIO_E05, + S5PC100_GPIO_E06, + S5PC100_GPIO_E07, + S5PC100_GPIO_E10, + S5PC100_GPIO_E11, + S5PC100_GPIO_E12, + S5PC100_GPIO_E13, + S5PC100_GPIO_E14, + S5PC100_GPIO_E15, + S5PC100_GPIO_E16, + S5PC100_GPIO_E17, + S5PC100_GPIO_F00, + S5PC100_GPIO_F01, + S5PC100_GPIO_F02, + S5PC100_GPIO_F03, + S5PC100_GPIO_F04, + S5PC100_GPIO_F05, + S5PC100_GPIO_F06, + S5PC100_GPIO_F07, + S5PC100_GPIO_F10, + S5PC100_GPIO_F11, + S5PC100_GPIO_F12, + S5PC100_GPIO_F13, + S5PC100_GPIO_F14, + S5PC100_GPIO_F15, + S5PC100_GPIO_F16, + S5PC100_GPIO_F17, + S5PC100_GPIO_F20, + S5PC100_GPIO_F21, + S5PC100_GPIO_F22, + S5PC100_GPIO_F23, + S5PC100_GPIO_F24, + S5PC100_GPIO_F25, + S5PC100_GPIO_F26, + S5PC100_GPIO_F27, + S5PC100_GPIO_F30, + S5PC100_GPIO_F31, + S5PC100_GPIO_F32, + S5PC100_GPIO_F33, + S5PC100_GPIO_F34, + S5PC100_GPIO_F35, + S5PC100_GPIO_F36, + S5PC100_GPIO_F37, + S5PC100_GPIO_G00, + S5PC100_GPIO_G01, + S5PC100_GPIO_G02, + S5PC100_GPIO_G03, + S5PC100_GPIO_G04, + S5PC100_GPIO_G05, + S5PC100_GPIO_G06, + S5PC100_GPIO_G07, + S5PC100_GPIO_G10, + S5PC100_GPIO_G11, + S5PC100_GPIO_G12, + S5PC100_GPIO_G13, + S5PC100_GPIO_G14, + S5PC100_GPIO_G15, + S5PC100_GPIO_G16, + S5PC100_GPIO_G17, + S5PC100_GPIO_G20, + S5PC100_GPIO_G21, + S5PC100_GPIO_G22, + S5PC100_GPIO_G23, + S5PC100_GPIO_G24, + S5PC100_GPIO_G25, + S5PC100_GPIO_G26, + S5PC100_GPIO_G27, + S5PC100_GPIO_G30, + S5PC100_GPIO_G31, + S5PC100_GPIO_G32, + S5PC100_GPIO_G33, + S5PC100_GPIO_G34, + S5PC100_GPIO_G35, + S5PC100_GPIO_G36, + S5PC100_GPIO_G37, + S5PC100_GPIO_I0, + S5PC100_GPIO_I1, + S5PC100_GPIO_I2, + S5PC100_GPIO_I3, + S5PC100_GPIO_I4, + S5PC100_GPIO_I5, + S5PC100_GPIO_I6, + S5PC100_GPIO_I7, + S5PC100_GPIO_J00, + S5PC100_GPIO_J01, + S5PC100_GPIO_J02, + S5PC100_GPIO_J03, + S5PC100_GPIO_J04, + S5PC100_GPIO_J05, + S5PC100_GPIO_J06, + S5PC100_GPIO_J07, + S5PC100_GPIO_J10, + S5PC100_GPIO_J11, + S5PC100_GPIO_J12, + S5PC100_GPIO_J13, + S5PC100_GPIO_J14, + S5PC100_GPIO_J15, + S5PC100_GPIO_J16, + S5PC100_GPIO_J17, + S5PC100_GPIO_J20, + S5PC100_GPIO_J21, + S5PC100_GPIO_J22, + S5PC100_GPIO_J23, + S5PC100_GPIO_J24, + S5PC100_GPIO_J25, + S5PC100_GPIO_J26, + S5PC100_GPIO_J27, + S5PC100_GPIO_J30, + S5PC100_GPIO_J31, + S5PC100_GPIO_J32, + S5PC100_GPIO_J33, + S5PC100_GPIO_J34, + S5PC100_GPIO_J35, + S5PC100_GPIO_J36, + S5PC100_GPIO_J37, + S5PC100_GPIO_J40, + S5PC100_GPIO_J41, + S5PC100_GPIO_J42, + S5PC100_GPIO_J43, + S5PC100_GPIO_J44, + S5PC100_GPIO_J45, + S5PC100_GPIO_J46, + S5PC100_GPIO_J47, + S5PC100_GPIO_K00, + S5PC100_GPIO_K01, + S5PC100_GPIO_K02, + S5PC100_GPIO_K03, + S5PC100_GPIO_K04, + S5PC100_GPIO_K05, + S5PC100_GPIO_K06, + S5PC100_GPIO_K07, + S5PC100_GPIO_K10, + S5PC100_GPIO_K11, + S5PC100_GPIO_K12, + S5PC100_GPIO_K13, + S5PC100_GPIO_K14, + S5PC100_GPIO_K15, + S5PC100_GPIO_K16, + S5PC100_GPIO_K17, + S5PC100_GPIO_K20, + S5PC100_GPIO_K21, + S5PC100_GPIO_K22, + S5PC100_GPIO_K23, + S5PC100_GPIO_K24, + S5PC100_GPIO_K25, + S5PC100_GPIO_K26, + S5PC100_GPIO_K27, + S5PC100_GPIO_K30, + S5PC100_GPIO_K31, + S5PC100_GPIO_K32, + S5PC100_GPIO_K33, + S5PC100_GPIO_K34, + S5PC100_GPIO_K35, + S5PC100_GPIO_K36, + S5PC100_GPIO_K37, + S5PC100_GPIO_L00, + S5PC100_GPIO_L01, + S5PC100_GPIO_L02, + S5PC100_GPIO_L03, + S5PC100_GPIO_L04, + S5PC100_GPIO_L05, + S5PC100_GPIO_L06, + S5PC100_GPIO_L07, + S5PC100_GPIO_L10, + S5PC100_GPIO_L11, + S5PC100_GPIO_L12, + S5PC100_GPIO_L13, + S5PC100_GPIO_L14, + S5PC100_GPIO_L15, + S5PC100_GPIO_L16, + S5PC100_GPIO_L17, + S5PC100_GPIO_L20, + S5PC100_GPIO_L21, + S5PC100_GPIO_L22, + S5PC100_GPIO_L23, + S5PC100_GPIO_L24, + S5PC100_GPIO_L25, + S5PC100_GPIO_L26, + S5PC100_GPIO_L27, + S5PC100_GPIO_L30, + S5PC100_GPIO_L31, + S5PC100_GPIO_L32, + S5PC100_GPIO_L33, + S5PC100_GPIO_L34, + S5PC100_GPIO_L35, + S5PC100_GPIO_L36, + S5PC100_GPIO_L37, + S5PC100_GPIO_L40, + S5PC100_GPIO_L41, + S5PC100_GPIO_L42, + S5PC100_GPIO_L43, + S5PC100_GPIO_L44, + S5PC100_GPIO_L45, + S5PC100_GPIO_L46, + S5PC100_GPIO_L47, + S5PC100_GPIO_H00, + S5PC100_GPIO_H01, + S5PC100_GPIO_H02, + S5PC100_GPIO_H03, + S5PC100_GPIO_H04, + S5PC100_GPIO_H05, + S5PC100_GPIO_H06, + S5PC100_GPIO_H07, + S5PC100_GPIO_H10, + S5PC100_GPIO_H11, + S5PC100_GPIO_H12, + S5PC100_GPIO_H13, + S5PC100_GPIO_H14, + S5PC100_GPIO_H15, + S5PC100_GPIO_H16, + S5PC100_GPIO_H17, + S5PC100_GPIO_H20, + S5PC100_GPIO_H21, + S5PC100_GPIO_H22, + S5PC100_GPIO_H23, + S5PC100_GPIO_H24, + S5PC100_GPIO_H25, + S5PC100_GPIO_H26, + S5PC100_GPIO_H27, + S5PC100_GPIO_H30, + S5PC100_GPIO_H31, + S5PC100_GPIO_H32, + S5PC100_GPIO_H33, + S5PC100_GPIO_H34, + S5PC100_GPIO_H35, + S5PC100_GPIO_H36, + S5PC100_GPIO_H37, + + S5PC100_GPIO_MAX_PORT }; -struct s5pc110_gpio { - struct s5p_gpio_bank a0; - struct s5p_gpio_bank a1; - struct s5p_gpio_bank b; - struct s5p_gpio_bank c0; - struct s5p_gpio_bank c1; - struct s5p_gpio_bank d0; - struct s5p_gpio_bank d1; - struct s5p_gpio_bank e0; - struct s5p_gpio_bank e1; - struct s5p_gpio_bank f0; - struct s5p_gpio_bank f1; - struct s5p_gpio_bank f2; - struct s5p_gpio_bank f3; - struct s5p_gpio_bank g0; - struct s5p_gpio_bank g1; - struct s5p_gpio_bank g2; - struct s5p_gpio_bank g3; - struct s5p_gpio_bank i; - struct s5p_gpio_bank j0; - struct s5p_gpio_bank j1; - struct s5p_gpio_bank j2; - struct s5p_gpio_bank j3; - struct s5p_gpio_bank j4; - struct s5p_gpio_bank mp0_1; - struct s5p_gpio_bank mp0_2; - struct s5p_gpio_bank mp0_3; - struct s5p_gpio_bank mp0_4; - struct s5p_gpio_bank mp0_5; - struct s5p_gpio_bank mp0_6; - struct s5p_gpio_bank mp0_7; - struct s5p_gpio_bank mp1_0; - struct s5p_gpio_bank mp1_1; - struct s5p_gpio_bank mp1_2; - struct s5p_gpio_bank mp1_3; - struct s5p_gpio_bank mp1_4; - struct s5p_gpio_bank mp1_5; - struct s5p_gpio_bank mp1_6; - struct s5p_gpio_bank mp1_7; - struct s5p_gpio_bank mp1_8; - struct s5p_gpio_bank mp2_0; - struct s5p_gpio_bank mp2_1; - struct s5p_gpio_bank mp2_2; - struct s5p_gpio_bank mp2_3; - struct s5p_gpio_bank mp2_4; - struct s5p_gpio_bank mp2_5; - struct s5p_gpio_bank mp2_6; - struct s5p_gpio_bank mp2_7; - struct s5p_gpio_bank mp2_8; - struct s5p_gpio_bank res1[48]; - struct s5p_gpio_bank h0; - struct s5p_gpio_bank h1; - struct s5p_gpio_bank h2; - struct s5p_gpio_bank h3; +enum s5pc110_gpio_pin { + S5PC110_GPIO_A00, + S5PC110_GPIO_A01, + S5PC110_GPIO_A02, + S5PC110_GPIO_A03, + S5PC110_GPIO_A04, + S5PC110_GPIO_A05, + S5PC110_GPIO_A06, + S5PC110_GPIO_A07, + S5PC110_GPIO_A10, + S5PC110_GPIO_A11, + S5PC110_GPIO_A12, + S5PC110_GPIO_A13, + S5PC110_GPIO_A14, + S5PC110_GPIO_A15, + S5PC110_GPIO_A16, + S5PC110_GPIO_A17, + S5PC110_GPIO_B0, + S5PC110_GPIO_B1, + S5PC110_GPIO_B2, + S5PC110_GPIO_B3, + S5PC110_GPIO_B4, + S5PC110_GPIO_B5, + S5PC110_GPIO_B6, + S5PC110_GPIO_B7, + S5PC110_GPIO_C00, + S5PC110_GPIO_C01, + S5PC110_GPIO_C02, + S5PC110_GPIO_C03, + S5PC110_GPIO_C04, + S5PC110_GPIO_C05, + S5PC110_GPIO_C06, + S5PC110_GPIO_C07, + S5PC110_GPIO_C10, + S5PC110_GPIO_C11, + S5PC110_GPIO_C12, + S5PC110_GPIO_C13, + S5PC110_GPIO_C14, + S5PC110_GPIO_C15, + S5PC110_GPIO_C16, + S5PC110_GPIO_C17, + S5PC110_GPIO_D00, + S5PC110_GPIO_D01, + S5PC110_GPIO_D02, + S5PC110_GPIO_D03, + S5PC110_GPIO_D04, + S5PC110_GPIO_D05, + S5PC110_GPIO_D06, + S5PC110_GPIO_D07, + S5PC110_GPIO_D10, + S5PC110_GPIO_D11, + S5PC110_GPIO_D12, + S5PC110_GPIO_D13, + S5PC110_GPIO_D14, + S5PC110_GPIO_D15, + S5PC110_GPIO_D16, + S5PC110_GPIO_D17, + S5PC110_GPIO_E00, + S5PC110_GPIO_E01, + S5PC110_GPIO_E02, + S5PC110_GPIO_E03, + S5PC110_GPIO_E04, + S5PC110_GPIO_E05, + S5PC110_GPIO_E06, + S5PC110_GPIO_E07, + S5PC110_GPIO_E10, + S5PC110_GPIO_E11, + S5PC110_GPIO_E12, + S5PC110_GPIO_E13, + S5PC110_GPIO_E14, + S5PC110_GPIO_E15, + S5PC110_GPIO_E16, + S5PC110_GPIO_E17, + S5PC110_GPIO_F00, + S5PC110_GPIO_F01, + S5PC110_GPIO_F02, + S5PC110_GPIO_F03, + S5PC110_GPIO_F04, + S5PC110_GPIO_F05, + S5PC110_GPIO_F06, + S5PC110_GPIO_F07, + S5PC110_GPIO_F10, + S5PC110_GPIO_F11, + S5PC110_GPIO_F12, + S5PC110_GPIO_F13, + S5PC110_GPIO_F14, + S5PC110_GPIO_F15, + S5PC110_GPIO_F16, + S5PC110_GPIO_F17, + S5PC110_GPIO_F20, + S5PC110_GPIO_F21, + S5PC110_GPIO_F22, + S5PC110_GPIO_F23, + S5PC110_GPIO_F24, + S5PC110_GPIO_F25, + S5PC110_GPIO_F26, + S5PC110_GPIO_F27, + S5PC110_GPIO_F30, + S5PC110_GPIO_F31, + S5PC110_GPIO_F32, + S5PC110_GPIO_F33, + S5PC110_GPIO_F34, + S5PC110_GPIO_F35, + S5PC110_GPIO_F36, + S5PC110_GPIO_F37, + S5PC110_GPIO_G00, + S5PC110_GPIO_G01, + S5PC110_GPIO_G02, + S5PC110_GPIO_G03, + S5PC110_GPIO_G04, + S5PC110_GPIO_G05, + S5PC110_GPIO_G06, + S5PC110_GPIO_G07, + S5PC110_GPIO_G10, + S5PC110_GPIO_G11, + S5PC110_GPIO_G12, + S5PC110_GPIO_G13, + S5PC110_GPIO_G14, + S5PC110_GPIO_G15, + S5PC110_GPIO_G16, + S5PC110_GPIO_G17, + S5PC110_GPIO_G20, + S5PC110_GPIO_G21, + S5PC110_GPIO_G22, + S5PC110_GPIO_G23, + S5PC110_GPIO_G24, + S5PC110_GPIO_G25, + S5PC110_GPIO_G26, + S5PC110_GPIO_G27, + S5PC110_GPIO_G30, + S5PC110_GPIO_G31, + S5PC110_GPIO_G32, + S5PC110_GPIO_G33, + S5PC110_GPIO_G34, + S5PC110_GPIO_G35, + S5PC110_GPIO_G36, + S5PC110_GPIO_G37, + S5PC110_GPIO_I0, + S5PC110_GPIO_I1, + S5PC110_GPIO_I2, + S5PC110_GPIO_I3, + S5PC110_GPIO_I4, + S5PC110_GPIO_I5, + S5PC110_GPIO_I6, + S5PC110_GPIO_I7, + S5PC110_GPIO_J00, + S5PC110_GPIO_J01, + S5PC110_GPIO_J02, + S5PC110_GPIO_J03, + S5PC110_GPIO_J04, + S5PC110_GPIO_J05, + S5PC110_GPIO_J06, + S5PC110_GPIO_J07, + S5PC110_GPIO_J10, + S5PC110_GPIO_J11, + S5PC110_GPIO_J12, + S5PC110_GPIO_J13, + S5PC110_GPIO_J14, + S5PC110_GPIO_J15, + S5PC110_GPIO_J16, + S5PC110_GPIO_J17, + S5PC110_GPIO_J20, + S5PC110_GPIO_J21, + S5PC110_GPIO_J22, + S5PC110_GPIO_J23, + S5PC110_GPIO_J24, + S5PC110_GPIO_J25, + S5PC110_GPIO_J26, + S5PC110_GPIO_J27, + S5PC110_GPIO_J30, + S5PC110_GPIO_J31, + S5PC110_GPIO_J32, + S5PC110_GPIO_J33, + S5PC110_GPIO_J34, + S5PC110_GPIO_J35, + S5PC110_GPIO_J36, + S5PC110_GPIO_J37, + S5PC110_GPIO_J40, + S5PC110_GPIO_J41, + S5PC110_GPIO_J42, + S5PC110_GPIO_J43, + S5PC110_GPIO_J44, + S5PC110_GPIO_J45, + S5PC110_GPIO_J46, + S5PC110_GPIO_J47, + S5PC110_GPIO_MP010, + S5PC110_GPIO_MP011, + S5PC110_GPIO_MP012, + S5PC110_GPIO_MP013, + S5PC110_GPIO_MP014, + S5PC110_GPIO_MP015, + S5PC110_GPIO_MP016, + S5PC110_GPIO_MP017, + S5PC110_GPIO_MP020, + S5PC110_GPIO_MP021, + S5PC110_GPIO_MP022, + S5PC110_GPIO_MP023, + S5PC110_GPIO_MP024, + S5PC110_GPIO_MP025, + S5PC110_GPIO_MP026, + S5PC110_GPIO_MP027, + S5PC110_GPIO_MP030, + S5PC110_GPIO_MP031, + S5PC110_GPIO_MP032, + S5PC110_GPIO_MP033, + S5PC110_GPIO_MP034, + S5PC110_GPIO_MP035, + S5PC110_GPIO_MP036, + S5PC110_GPIO_MP037, + S5PC110_GPIO_MP040, + S5PC110_GPIO_MP041, + S5PC110_GPIO_MP042, + S5PC110_GPIO_MP043, + S5PC110_GPIO_MP044, + S5PC110_GPIO_MP045, + S5PC110_GPIO_MP046, + S5PC110_GPIO_MP047, + S5PC110_GPIO_MP050, + S5PC110_GPIO_MP051, + S5PC110_GPIO_MP052, + S5PC110_GPIO_MP053, + S5PC110_GPIO_MP054, + S5PC110_GPIO_MP055, + S5PC110_GPIO_MP056, + S5PC110_GPIO_MP057, + S5PC110_GPIO_MP060, + S5PC110_GPIO_MP061, + S5PC110_GPIO_MP062, + S5PC110_GPIO_MP063, + S5PC110_GPIO_MP064, + S5PC110_GPIO_MP065, + S5PC110_GPIO_MP066, + S5PC110_GPIO_MP067, + S5PC110_GPIO_MP070, + S5PC110_GPIO_MP071, + S5PC110_GPIO_MP072, + S5PC110_GPIO_MP073, + S5PC110_GPIO_MP074, + S5PC110_GPIO_MP075, + S5PC110_GPIO_MP076, + S5PC110_GPIO_MP077, + S5PC110_GPIO_MP100, + S5PC110_GPIO_MP101, + S5PC110_GPIO_MP102, + S5PC110_GPIO_MP103, + S5PC110_GPIO_MP104, + S5PC110_GPIO_MP105, + S5PC110_GPIO_MP106, + S5PC110_GPIO_MP107, + S5PC110_GPIO_MP110, + S5PC110_GPIO_MP111, + S5PC110_GPIO_MP112, + S5PC110_GPIO_MP113, + S5PC110_GPIO_MP114, + S5PC110_GPIO_MP115, + S5PC110_GPIO_MP116, + S5PC110_GPIO_MP117, + S5PC110_GPIO_MP120, + S5PC110_GPIO_MP121, + S5PC110_GPIO_MP122, + S5PC110_GPIO_MP123, + S5PC110_GPIO_MP124, + S5PC110_GPIO_MP125, + S5PC110_GPIO_MP126, + S5PC110_GPIO_MP127, + S5PC110_GPIO_MP130, + S5PC110_GPIO_MP131, + S5PC110_GPIO_MP132, + S5PC110_GPIO_MP133, + S5PC110_GPIO_MP134, + S5PC110_GPIO_MP135, + S5PC110_GPIO_MP136, + S5PC110_GPIO_MP137, + S5PC110_GPIO_MP140, + S5PC110_GPIO_MP141, + S5PC110_GPIO_MP142, + S5PC110_GPIO_MP143, + S5PC110_GPIO_MP144, + S5PC110_GPIO_MP145, + S5PC110_GPIO_MP146, + S5PC110_GPIO_MP147, + S5PC110_GPIO_MP150, + S5PC110_GPIO_MP151, + S5PC110_GPIO_MP152, + S5PC110_GPIO_MP153, + S5PC110_GPIO_MP154, + S5PC110_GPIO_MP155, + S5PC110_GPIO_MP156, + S5PC110_GPIO_MP157, + S5PC110_GPIO_MP160, + S5PC110_GPIO_MP161, + S5PC110_GPIO_MP162, + S5PC110_GPIO_MP163, + S5PC110_GPIO_MP164, + S5PC110_GPIO_MP165, + S5PC110_GPIO_MP166, + S5PC110_GPIO_MP167, + S5PC110_GPIO_MP170, + S5PC110_GPIO_MP171, + S5PC110_GPIO_MP172, + S5PC110_GPIO_MP173, + S5PC110_GPIO_MP174, + S5PC110_GPIO_MP175, + S5PC110_GPIO_MP176, + S5PC110_GPIO_MP177, + S5PC110_GPIO_MP180, + S5PC110_GPIO_MP181, + S5PC110_GPIO_MP182, + S5PC110_GPIO_MP183, + S5PC110_GPIO_MP184, + S5PC110_GPIO_MP185, + S5PC110_GPIO_MP186, + S5PC110_GPIO_MP187, + S5PC110_GPIO_MP200, + S5PC110_GPIO_MP201, + S5PC110_GPIO_MP202, + S5PC110_GPIO_MP203, + S5PC110_GPIO_MP204, + S5PC110_GPIO_MP205, + S5PC110_GPIO_MP206, + S5PC110_GPIO_MP207, + S5PC110_GPIO_MP210, + S5PC110_GPIO_MP211, + S5PC110_GPIO_MP212, + S5PC110_GPIO_MP213, + S5PC110_GPIO_MP214, + S5PC110_GPIO_MP215, + S5PC110_GPIO_MP216, + S5PC110_GPIO_MP217, + S5PC110_GPIO_MP220, + S5PC110_GPIO_MP221, + S5PC110_GPIO_MP222, + S5PC110_GPIO_MP223, + S5PC110_GPIO_MP224, + S5PC110_GPIO_MP225, + S5PC110_GPIO_MP226, + S5PC110_GPIO_MP227, + S5PC110_GPIO_MP230, + S5PC110_GPIO_MP231, + S5PC110_GPIO_MP232, + S5PC110_GPIO_MP233, + S5PC110_GPIO_MP234, + S5PC110_GPIO_MP235, + S5PC110_GPIO_MP236, + S5PC110_GPIO_MP237, + S5PC110_GPIO_MP240, + S5PC110_GPIO_MP241, + S5PC110_GPIO_MP242, + S5PC110_GPIO_MP243, + S5PC110_GPIO_MP244, + S5PC110_GPIO_MP245, + S5PC110_GPIO_MP246, + S5PC110_GPIO_MP247, + S5PC110_GPIO_MP250, + S5PC110_GPIO_MP251, + S5PC110_GPIO_MP252, + S5PC110_GPIO_MP253, + S5PC110_GPIO_MP254, + S5PC110_GPIO_MP255, + S5PC110_GPIO_MP256, + S5PC110_GPIO_MP257, + S5PC110_GPIO_MP260, + S5PC110_GPIO_MP261, + S5PC110_GPIO_MP262, + S5PC110_GPIO_MP263, + S5PC110_GPIO_MP264, + S5PC110_GPIO_MP265, + S5PC110_GPIO_MP266, + S5PC110_GPIO_MP267, + S5PC110_GPIO_MP270, + S5PC110_GPIO_MP271, + S5PC110_GPIO_MP272, + S5PC110_GPIO_MP273, + S5PC110_GPIO_MP274, + S5PC110_GPIO_MP275, + S5PC110_GPIO_MP276, + S5PC110_GPIO_MP277, + S5PC110_GPIO_MP280, + S5PC110_GPIO_MP281, + S5PC110_GPIO_MP282, + S5PC110_GPIO_MP283, + S5PC110_GPIO_MP284, + S5PC110_GPIO_MP285, + S5PC110_GPIO_MP286, + S5PC110_GPIO_MP287, + S5PC110_GPIO_RES, + S5PC110_GPIO_H00 = (S5PC110_GPIO_RES + (48 * 8)), + S5PC110_GPIO_H01, + S5PC110_GPIO_H02, + S5PC110_GPIO_H03, + S5PC110_GPIO_H04, + S5PC110_GPIO_H05, + S5PC110_GPIO_H06, + S5PC110_GPIO_H07, + S5PC110_GPIO_H10, + S5PC110_GPIO_H11, + S5PC110_GPIO_H12, + S5PC110_GPIO_H13, + S5PC110_GPIO_H14, + S5PC110_GPIO_H15, + S5PC110_GPIO_H16, + S5PC110_GPIO_H17, + S5PC110_GPIO_H20, + S5PC110_GPIO_H21, + S5PC110_GPIO_H22, + S5PC110_GPIO_H23, + S5PC110_GPIO_H24, + S5PC110_GPIO_H25, + S5PC110_GPIO_H26, + S5PC110_GPIO_H27, + S5PC110_GPIO_H30, + S5PC110_GPIO_H31, + S5PC110_GPIO_H32, + S5PC110_GPIO_H33, + S5PC110_GPIO_H34, + S5PC110_GPIO_H35, + S5PC110_GPIO_H36, + S5PC110_GPIO_H37, + + S5PC110_GPIO_MAX_PORT +}; + +struct gpio_info { + unsigned int reg_addr; /* Address of register for this part */ + unsigned int max_gpio; /* Maximum GPIO in this part */ +}; + +#define S5PC100_GPIO_NUM_PARTS 1 +static struct gpio_info s5pc100_gpio_data[S5PC100_GPIO_NUM_PARTS] = { + { S5PC100_GPIO_BASE, S5PC100_GPIO_MAX_PORT }, +}; + +#define S5PC110_GPIO_NUM_PARTS 1 +static struct gpio_info s5pc110_gpio_data[S5PC110_GPIO_NUM_PARTS] = { + { S5PC110_GPIO_BASE, S5PC110_GPIO_MAX_PORT }, +}; + +static inline struct gpio_info *get_gpio_data(void) +{ + if (cpu_is_s5pc100()) + return s5pc100_gpio_data; + else if (cpu_is_s5pc110()) + return s5pc110_gpio_data; + + return NULL; +} + +static inline unsigned int get_bank_num(void) +{ + if (cpu_is_s5pc100()) + return S5PC100_GPIO_NUM_PARTS; + else if (cpu_is_s5pc110()) + return S5PC110_GPIO_NUM_PARTS; + + return 0; +} + +/* + * This structure helps mapping symbolic GPIO names into indices from + * exynos5_gpio_pin/exynos5420_gpio_pin enums. + * + * By convention, symbolic GPIO name is defined as follows: + * + * g[p], where + * p is optional + * - a single character bank name, as defined by the SOC + * - a single digit set number + * - bit number within the set (in 0..7 range). + * + * essentially form an octal number of the GPIO pin within the bank + * space. On the 5420 architecture some banks' sets do not start not from zero + * ('d' starts from 1 and 'j' starts from 4). To compensate for that and + * maintain flat number space withoout holes, those banks use offsets to be + * deducted from the pin number. + */ +struct gpio_name_num_table { + char bank; /* bank name symbol */ + u8 bank_size; /* total number of pins in the bank */ + char bank_offset; /* offset of the first bank's pin */ + unsigned int base; /* index of the first bank's pin in the enum */ +}; + +#define GPIO_PER_BANK 8 +#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base } +static const struct gpio_name_num_table s5pc100_gpio_table[] = { + GPIO_ENTRY('a', S5PC100_GPIO_A00, S5PC100_GPIO_B0, 0), + GPIO_ENTRY('b', S5PC100_GPIO_B0, S5PC100_GPIO_C0, 0), + GPIO_ENTRY('c', S5PC100_GPIO_C0, S5PC100_GPIO_D0, 0), + GPIO_ENTRY('d', S5PC100_GPIO_D0, S5PC100_GPIO_E00, 0), + GPIO_ENTRY('e', S5PC100_GPIO_E00, S5PC100_GPIO_F00, 0), + GPIO_ENTRY('f', S5PC100_GPIO_F00, S5PC100_GPIO_G00, 0), + GPIO_ENTRY('g', S5PC100_GPIO_G00, S5PC100_GPIO_I0, 0), + GPIO_ENTRY('i', S5PC100_GPIO_I0, S5PC100_GPIO_J00, 0), + GPIO_ENTRY('j', S5PC100_GPIO_J00, S5PC100_GPIO_K00, 0), + GPIO_ENTRY('k', S5PC100_GPIO_K00, S5PC100_GPIO_L00, 0), + GPIO_ENTRY('l', S5PC100_GPIO_L00, S5PC100_GPIO_H00, 0), + GPIO_ENTRY('h', S5PC100_GPIO_H00, S5PC100_GPIO_MAX_PORT, 0), + { 0 } +}; + +static const struct gpio_name_num_table s5pc110_gpio_table[] = { + GPIO_ENTRY('a', S5PC110_GPIO_A00, S5PC110_GPIO_B0, 0), + GPIO_ENTRY('b', S5PC110_GPIO_B0, S5PC110_GPIO_C00, 0), + GPIO_ENTRY('c', S5PC110_GPIO_C00, S5PC110_GPIO_D00, 0), + GPIO_ENTRY('d', S5PC110_GPIO_D00, S5PC110_GPIO_E00, 0), + GPIO_ENTRY('e', S5PC110_GPIO_E00, S5PC110_GPIO_F00, 0), + GPIO_ENTRY('f', S5PC110_GPIO_F00, S5PC110_GPIO_G00, 0), + GPIO_ENTRY('g', S5PC110_GPIO_G00, S5PC110_GPIO_I0, 0), + GPIO_ENTRY('i', S5PC110_GPIO_I0, S5PC110_GPIO_J00, 0), + GPIO_ENTRY('j', S5PC110_GPIO_J00, S5PC110_GPIO_MP010, 0), + GPIO_ENTRY('h', S5PC110_GPIO_H00, S5PC110_GPIO_MAX_PORT, 0), + { 0 } }; /* functions */ -void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg); -void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en); -void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio); -void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en); -unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio); -void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode); -void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode); -void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); +void gpio_cfg_pin(int gpio, int cfg); +void gpio_set_pull(int gpio, int mode); +void gpio_set_drv(int gpio, int mode); +int gpio_direction_output(unsigned gpio, int value); +int gpio_set_value(unsigned gpio, int value); +int gpio_get_value(unsigned gpio); +void gpio_set_rate(int gpio, int mode); +struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio); +int s5p_gpio_get_pin(unsigned gpio); /* GPIO pins per bank */ #define GPIO_PER_BANK 8 - -#define S5P_GPIO_PART_SHIFT (24) -#define S5P_GPIO_PART_MASK (0xff) -#define S5P_GPIO_BANK_SHIFT (8) -#define S5P_GPIO_BANK_MASK (0xffff) -#define S5P_GPIO_PIN_MASK (0xff) - -#define S5P_GPIO_SET_PART(x) \ - (((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT) - -#define S5P_GPIO_GET_PART(x) \ - (((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK) - -#define S5P_GPIO_SET_PIN(x) \ - ((x) & S5P_GPIO_PIN_MASK) - -#define S5PC100_SET_BANK(bank) \ - (((unsigned)&(((struct s5pc100_gpio *) \ - S5PC100_GPIO_BASE)->bank) - S5PC100_GPIO_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) - -#define S5PC110_SET_BANK(bank) \ - ((((unsigned)&(((struct s5pc110_gpio *) \ - S5PC110_GPIO_BASE)->bank) - S5PC110_GPIO_BASE) \ - & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) - -#define s5pc100_gpio_get(bank, pin) \ - (S5P_GPIO_SET_PART(0) | \ - S5PC100_SET_BANK(bank) | \ - S5P_GPIO_SET_PIN(pin)) - -#define s5pc110_gpio_get(bank, pin) \ - (S5P_GPIO_SET_PART(0) | \ - S5PC110_SET_BANK(bank) | \ - S5P_GPIO_SET_PIN(pin)) - -static inline unsigned int s5p_gpio_base(int nr) -{ - return samsung_get_base_gpio(); -} #endif /* Pin configurations */ -#define GPIO_INPUT 0x0 -#define GPIO_OUTPUT 0x1 -#define GPIO_IRQ 0xf -#define GPIO_FUNC(x) (x) +#define S5P_GPIO_INPUT 0x0 +#define S5P_GPIO_OUTPUT 0x1 +#define S5P_GPIO_IRQ 0xf +#define S5P_GPIO_FUNC(x) (x) /* Pull mode */ -#define GPIO_PULL_NONE 0x0 -#define GPIO_PULL_DOWN 0x1 -#define GPIO_PULL_UP 0x2 +#define S5P_GPIO_PULL_NONE 0x0 +#define S5P_GPIO_PULL_DOWN 0x1 +#define S5P_GPIO_PULL_UP 0x2 /* Drive Strength level */ -#define GPIO_DRV_1X 0x0 -#define GPIO_DRV_3X 0x1 -#define GPIO_DRV_2X 0x2 -#define GPIO_DRV_4X 0x3 -#define GPIO_DRV_FAST 0x0 -#define GPIO_DRV_SLOW 0x1 +#define S5P_GPIO_DRV_1X 0x0 +#define S5P_GPIO_DRV_3X 0x1 +#define S5P_GPIO_DRV_2X 0x2 +#define S5P_GPIO_DRV_4X 0x3 +#define S5P_GPIO_DRV_FAST 0x0 +#define S5P_GPIO_DRV_SLOW 0x1 #endif diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c index 9efc355dab..ef88314f7d 100644 --- a/board/samsung/arndale/arndale.c +++ b/board/samsung/arndale/arndale.c @@ -16,17 +16,14 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_USB_EHCI_EXYNOS int board_usb_init(int index, enum usb_init_type init) { - struct exynos5_gpio_part1 *gpio = (struct exynos5_gpio_part1 *) - samsung_get_base_gpio_part1(); - /* Configure gpios for usb 3503 hub: * disconnect, toggle reset and connect */ - s5p_gpio_direction_output(&gpio->d1, 7, 0); - s5p_gpio_direction_output(&gpio->x3, 5, 0); + gpio_direction_output(EXYNOS5_GPIO_D17, 0); + gpio_direction_output(EXYNOS5_GPIO_X35, 0); - s5p_gpio_direction_output(&gpio->x3, 5, 1); - s5p_gpio_direction_output(&gpio->d1, 7, 1); + gpio_direction_output(EXYNOS5_GPIO_X35, 1); + gpio_direction_output(EXYNOS5_GPIO_D17, 1); return 0; } diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index 61b9ece038..4cea63b813 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -17,8 +17,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct s5pc110_gpio *s5pc110_gpio; - u32 get_board_rev(void) { return 0; @@ -27,8 +25,6 @@ u32 get_board_rev(void) int board_init(void) { /* Set Initial global variables */ - s5pc110_gpio = (struct s5pc110_gpio *)S5PC110_GPIO_BASE; - gd->bd->bi_arch_number = MACH_TYPE_GONI; gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; @@ -82,7 +78,7 @@ int board_mmc_init(bd_t *bis) int i, ret, ret_sd = 0; /* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */ - s5p_gpio_direction_output(&s5pc110_gpio->j2, 7, 1); + gpio_direction_output(S5PC110_GPIO_J27, 1); /* * MMC0 GPIO @@ -91,15 +87,15 @@ int board_mmc_init(bd_t *bis) * GPG0[2] SD_0_CDn -> Not used * GPG0[3:6] SD_0_DATA[0:3] */ - for (i = 0; i < 7; i++) { - if (i == 2) + for (i = S5PC110_GPIO_G00; i < S5PC110_GPIO_G07; i++) { + if (i == S5PC110_GPIO_G02) continue; /* GPG0[0:6] special function 2 */ - s5p_gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2); + gpio_cfg_pin(i, 0x2); /* GPG0[0:6] pull disable */ - s5p_gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); /* GPG0[0:6] drv 4x */ - s5p_gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } ret = s5p_mmc_init(0, 4); @@ -110,20 +106,20 @@ int board_mmc_init(bd_t *bis) * SD card (T_FLASH) detect and init * T_FLASH_DETECT: EINT28: GPH3[4] input mode */ - s5p_gpio_cfg_pin(&s5pc110_gpio->h3, 4, GPIO_INPUT); - s5p_gpio_set_pull(&s5pc110_gpio->h3, 4, GPIO_PULL_UP); + gpio_cfg_pin(S5PC110_GPIO_H34, S5P_GPIO_INPUT); + gpio_set_pull(S5PC110_GPIO_H34, S5P_GPIO_PULL_UP); - if (!s5p_gpio_get_value(&s5pc110_gpio->h3, 4)) { - for (i = 0; i < 7; i++) { - if (i == 2) + if (!gpio_get_value(S5PC110_GPIO_H34)) { + for (i = S5PC110_GPIO_G20; i < S5PC110_GPIO_G27; i++) { + if (i == S5PC110_GPIO_G22) continue; /* GPG2[0:6] special function 2 */ - s5p_gpio_cfg_pin(&s5pc110_gpio->g2, i, 0x2); + gpio_cfg_pin(i, 0x2); /* GPG2[0:6] pull disable */ - s5p_gpio_set_pull(&s5pc110_gpio->g2, i, GPIO_PULL_NONE); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); /* GPG2[0:6] drv 4x */ - s5p_gpio_set_drv(&s5pc110_gpio->g2, i, GPIO_DRV_4X); + gpio_set_drv(i, S5P_GPIO_DRV_4X); } ret_sd = s5p_mmc_init(2, 4); diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c index 379a45cc23..58821c41a4 100644 --- a/board/samsung/smdk5250/exynos5-dt.c +++ b/board/samsung/smdk5250/exynos5-dt.c @@ -27,12 +27,9 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_SOUND_MAX98095 static void board_enable_audio_codec(void) { - struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) - samsung_get_base_gpio_part1(); - /* Enable MAX98095 Codec */ - s5p_gpio_direction_output(&gpio1->x1, 7, 1); - s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE); + gpio_direction_output(EXYNOS5_GPIO_X17, 1); + gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE); } #endif @@ -47,19 +44,16 @@ int exynos_init(void) #ifdef CONFIG_LCD void exynos_cfg_lcd_gpio(void) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1(); - /* For Backlight */ - s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->b2, 0, 1); + gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT); + gpio_set_value(EXYNOS5_GPIO_B20, 1); /* LCD power on */ - s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->x1, 5, 1); + gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT); + gpio_set_value(EXYNOS5_GPIO_X15, 1); /* Set Hotplug detect for DP */ - s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3)); } void exynos_set_dp_phy(unsigned int onoff) diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c index 28a6d9e718..014b7bdf89 100644 --- a/board/samsung/smdk5250/smdk5250.c +++ b/board/samsung/smdk5250/smdk5250.c @@ -29,12 +29,9 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_SOUND_MAX98095 static void board_enable_audio_codec(void) { - struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) - samsung_get_base_gpio_part1(); - /* Enable MAX98095 Codec */ - s5p_gpio_direction_output(&gpio1->x1, 7, 1); - s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE); + gpio_direction_output(EXYNOS5_GPIO_X17, 1); + gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE); } #endif @@ -275,19 +272,17 @@ int exynos_power_init(void) #ifdef CONFIG_LCD void exynos_cfg_lcd_gpio(void) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); /* For Backlight */ - s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->b2, 0, 1); + gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT); + gpio_set_value(EXYNOS5_GPIO_B20, 1); /* LCD power on */ - s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->x1, 5, 1); + gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT); + gpio_set_value(EXYNOS5_GPIO_X15, 1); /* Set Hotplug detect for DP */ - s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3)); } void exynos_set_dp_phy(unsigned int onoff) diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c index e4606ecd2a..9207522953 100644 --- a/board/samsung/smdk5420/smdk5420.c +++ b/board/samsung/smdk5420/smdk5420.c @@ -21,11 +21,8 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_USB_EHCI_EXYNOS static int board_usb_vbus_init(void) { - struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) - samsung_get_base_gpio_part1(); - /* Enable VBUS power switch */ - s5p_gpio_direction_output(&gpio1->x2, 6, 1); + gpio_direction_output(EXYNOS5420_GPIO_X26, 1); /* VBUS turn ON time */ mdelay(3); @@ -49,15 +46,15 @@ void cfg_lcd_gpio(void) (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1(); /* For Backlight */ - s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->b2, 0, 1); + gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_OUTPUT); + gpio_set_value(EXYNOS5420_GPIO_B20, 1); /* LCD power on */ - s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT); - s5p_gpio_set_value(&gpio1->x1, 5, 1); + gpio_cfg_pin(EXYNOS5420_GPIO_X15, S5P_GPIO_OUTPUT); + gpio_set_value(EXYNOS5420_GPIO_X15, 1); /* Set Hotplug detect for DP */ - s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3)); + gpio_cfg_pin(EXYNOS5420_GPIO_X07, S5P_GPIO_FUNC(0x3)); } vidinfo_t panel_info = { diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index 860c851b25..e009564a59 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -21,11 +21,8 @@ static void smc9115_pre_init(void) { u32 smc_bw_conf, smc_bc_conf; - struct s5pc100_gpio *const gpio = - (struct s5pc100_gpio *)samsung_get_base_gpio(); - /* gpio configuration GPK0CON */ - s5p_gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); + gpio_cfg_pin(S5PC100_GPIO_K00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2)); /* Ethernet needs bus width of 16 bits */ smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c index 81a306082d..8eca358981 100644 --- a/board/samsung/smdkv310/smdkv310.c +++ b/board/samsung/smdkv310/smdkv310.c @@ -15,15 +15,13 @@ #include DECLARE_GLOBAL_DATA_PTR; -struct exynos4_gpio_part1 *gpio1; -struct exynos4_gpio_part2 *gpio2; static void smc9115_pre_init(void) { u32 smc_bw_conf, smc_bc_conf; /* gpio configuration GPK0CON */ - s5p_gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS4_GPIO_Y00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2)); /* Ethernet needs bus width of 16 bits */ smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); @@ -38,9 +36,6 @@ static void smc9115_pre_init(void) int board_init(void) { - gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE; - gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE; - smc9115_pre_init(); gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); @@ -103,21 +98,21 @@ int board_mmc_init(bd_t *bis) * GPK2[2] SD_2_CDn * GPK2[3:6] SD_2_DATA[0:3](2) */ - for (i = 0; i < 7; i++) { + for (i = EXYNOS4_GPIO_K20; i < EXYNOS4_GPIO_K27; i++) { /* GPK2[0:6] special function 2 */ - s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2)); + gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2)); /* GPK2[0:6] drv 4x */ - s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); + gpio_set_drv(i, S5P_GPIO_DRV_4X); /* GPK2[0:1] pull disable */ - if (i == 0 || i == 1) { - s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); + if (i == EXYNOS4_GPIO_K20 || i == EXYNOS4_GPIO_K21) { + gpio_set_pull(i, S5P_GPIO_PULL_NONE); continue; } /* GPK2[2:6] pull up */ - s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP); + gpio_set_pull(i, S5P_GPIO_PULL_UP); } err = s5p_mmc_init(2, 4); return err; diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index 7c79e7b73a..f8b2908002 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -54,8 +54,6 @@ int exynos_init(void) void i2c_init_board(void) { int err; - struct exynos4_gpio_part2 *gpio2 = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); /* I2C_5 -> PMIC */ err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE); @@ -65,8 +63,8 @@ void i2c_init_board(void) } /* I2C_8 -> FG */ - s5p_gpio_direction_output(&gpio2->y4, 0, 1); - s5p_gpio_direction_output(&gpio2->y4, 1, 1); + gpio_direction_output(EXYNOS4_GPIO_Y40, 1); + gpio_direction_output(EXYNOS4_GPIO_Y41, 1); } static void trats_low_power_mode(void) @@ -347,21 +345,19 @@ int exynos_power_init(void) static unsigned int get_hw_revision(void) { - struct exynos4_gpio_part1 *gpio = - (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1(); int hwrev = 0; int i; /* hw_rev[3:0] == GPE1[3:0] */ - for (i = 0; i < 4; i++) { - s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT); - s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE); + for (i = EXYNOS4_GPIO_E10; i < EXYNOS4_GPIO_E14; i++) { + gpio_cfg_pin(i, S5P_GPIO_INPUT); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); } udelay(1); for (i = 0; i < 4; i++) - hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i); + hwrev |= (gpio_get_value(EXYNOS4_GPIO_E10 + i) << i); debug("hwrev 0x%x\n", hwrev); @@ -444,11 +440,8 @@ int usb_cable_connected(void) static void pmic_reset(void) { - struct exynos4_gpio_part2 *gpio = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - - s5p_gpio_direction_output(&gpio->x0, 7, 1); - s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE); + gpio_direction_output(EXYNOS4_GPIO_X07, 1); + gpio_set_pull(EXYNOS4_GPIO_X27, S5P_GPIO_PULL_NONE); } static void board_clock_init(void) @@ -525,12 +518,9 @@ static void board_power_init(void) static void exynos_uart_init(void) { - struct exynos4_gpio_part2 *gpio2 = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ - s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP); - s5p_gpio_direction_output(&gpio2->y4, 7, 1); + gpio_set_pull(EXYNOS4_GPIO_Y47, S5P_GPIO_PULL_UP); + gpio_direction_output(EXYNOS4_GPIO_Y47, 1); } int exynos_early_init_f(void) @@ -546,14 +536,11 @@ int exynos_early_init_f(void) void exynos_reset_lcd(void) { - struct exynos4_gpio_part2 *gpio2 = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - - s5p_gpio_direction_output(&gpio2->y4, 5, 1); + gpio_direction_output(EXYNOS4_GPIO_Y45, 1); udelay(10000); - s5p_gpio_direction_output(&gpio2->y4, 5, 0); + gpio_direction_output(EXYNOS4_GPIO_Y45, 0); udelay(10000); - s5p_gpio_direction_output(&gpio2->y4, 5, 1); + gpio_direction_output(EXYNOS4_GPIO_Y45, 1); } int lcd_power(void) diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index f558ef97a9..d4d5926d81 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -25,9 +25,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct exynos4x12_gpio_part1 *gpio1; -static struct exynos4x12_gpio_part2 *gpio2; - static unsigned int board_rev = -1; static inline u32 get_model_rev(void); @@ -37,26 +34,24 @@ static void check_hw_revision(void) int modelrev = 0; int i; - gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2(); - /* * GPM1[1:0]: MODEL_REV[1:0] * Don't set as pull-none for these N/C pin. * TRM say that it may cause unexcepted state and leakage current. * and pull-none is only for output function. */ - for (i = 0; i < 2; i++) - s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT); + for (i = EXYNOS4X12_GPIO_M10; i < EXYNOS4X12_GPIO_M12; i++) + gpio_cfg_pin(i, S5P_GPIO_INPUT); /* GPM1[5:2]: HW_REV[3:0] */ - for (i = 2; i < 6; i++) { - s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT); - s5p_gpio_set_pull(&gpio2->m1, i, GPIO_PULL_NONE); + for (i = EXYNOS4X12_GPIO_M12; i < EXYNOS4X12_GPIO_M16; i++) { + gpio_cfg_pin(i, S5P_GPIO_INPUT); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); } /* GPM1[1:0]: MODEL_REV[1:0] */ for (i = 0; i < 2; i++) - modelrev |= (s5p_gpio_get_value(&gpio2->m1, i) << i); + modelrev |= (gpio_get_value(EXYNOS4X12_GPIO_M10 + i) << i); /* board_rev[15:8] = model */ board_rev = modelrev << 8; @@ -74,26 +69,24 @@ static inline u32 get_model_rev(void) static void board_external_gpio_init(void) { - gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2(); - /* * some pins which in alive block are connected with external pull-up * but it's default setting is pull-down. * if that pin set as input then that floated */ - s5p_gpio_set_pull(&gpio2->x0, 2, GPIO_PULL_NONE); /* PS_ALS_INT */ - s5p_gpio_set_pull(&gpio2->x0, 4, GPIO_PULL_NONE); /* TSP_nINT */ - s5p_gpio_set_pull(&gpio2->x0, 7, GPIO_PULL_NONE); /* AP_PMIC_IRQ*/ - s5p_gpio_set_pull(&gpio2->x1, 5, GPIO_PULL_NONE); /* IF_PMIC_IRQ*/ - s5p_gpio_set_pull(&gpio2->x2, 0, GPIO_PULL_NONE); /* VOL_UP */ - s5p_gpio_set_pull(&gpio2->x2, 1, GPIO_PULL_NONE); /* VOL_DOWN */ - s5p_gpio_set_pull(&gpio2->x2, 3, GPIO_PULL_NONE); /* FUEL_ALERT */ - s5p_gpio_set_pull(&gpio2->x2, 4, GPIO_PULL_NONE); /* ADC_INT */ - s5p_gpio_set_pull(&gpio2->x2, 7, GPIO_PULL_NONE); /* nPOWER */ - s5p_gpio_set_pull(&gpio2->x3, 0, GPIO_PULL_NONE); /* WPC_INT */ - s5p_gpio_set_pull(&gpio2->x3, 5, GPIO_PULL_NONE); /* OK_KEY */ - s5p_gpio_set_pull(&gpio2->x3, 7, GPIO_PULL_NONE); /* HDMI_HPD */ + gpio_set_pull(EXYNOS4X12_GPIO_X02, S5P_GPIO_PULL_NONE); /* PS_ALS_INT */ + gpio_set_pull(EXYNOS4X12_GPIO_X04, S5P_GPIO_PULL_NONE); /* TSP_nINT */ + gpio_set_pull(EXYNOS4X12_GPIO_X07, S5P_GPIO_PULL_NONE); /* AP_PMIC_IRQ*/ + gpio_set_pull(EXYNOS4X12_GPIO_X15, S5P_GPIO_PULL_NONE); /* IF_PMIC_IRQ*/ + gpio_set_pull(EXYNOS4X12_GPIO_X20, S5P_GPIO_PULL_NONE); /* VOL_UP */ + gpio_set_pull(EXYNOS4X12_GPIO_X21, S5P_GPIO_PULL_NONE); /* VOL_DOWN */ + gpio_set_pull(EXYNOS4X12_GPIO_X23, S5P_GPIO_PULL_NONE); /* FUEL_ALERT */ + gpio_set_pull(EXYNOS4X12_GPIO_X24, S5P_GPIO_PULL_NONE); /* ADC_INT */ + gpio_set_pull(EXYNOS4X12_GPIO_X27, S5P_GPIO_PULL_NONE); /* nPOWER */ + gpio_set_pull(EXYNOS4X12_GPIO_X30, S5P_GPIO_PULL_NONE); /* WPC_INT */ + gpio_set_pull(EXYNOS4X12_GPIO_X35, S5P_GPIO_PULL_NONE); /* OK_KEY */ + gpio_set_pull(EXYNOS4X12_GPIO_X37, S5P_GPIO_PULL_NONE); /* HDMI_HPD */ } #ifdef CONFIG_SYS_I2C_INIT_BOARD @@ -101,9 +94,6 @@ static void board_init_i2c(void) { int err; - gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1(); - gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2(); - /* I2C_7 */ err = exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE); if (err) { @@ -112,12 +102,12 @@ static void board_init_i2c(void) } /* I2C_8 */ - s5p_gpio_direction_output(&gpio1->f1, 4, 1); - s5p_gpio_direction_output(&gpio1->f1, 5, 1); + gpio_direction_output(EXYNOS4X12_GPIO_F14, 1); + gpio_direction_output(EXYNOS4X12_GPIO_F15, 1); /* I2C_9 */ - s5p_gpio_direction_output(&gpio2->m2, 1, 1); - s5p_gpio_direction_output(&gpio2->m2, 0, 1); + gpio_direction_output(EXYNOS4X12_GPIO_M21, 1); + gpio_direction_output(EXYNOS4X12_GPIO_M20, 1); } #endif @@ -125,17 +115,17 @@ static void board_init_i2c(void) int get_soft_i2c_scl_pin(void) { if (I2C_ADAP_HWNR) - return exynos4x12_gpio_get(2, m2, 1); /* I2C9 */ + return EXYNOS4X12_GPIO_M21; /* I2C9 */ else - return exynos4x12_gpio_get(1, f1, 4); /* I2C8 */ + return EXYNOS4X12_GPIO_F14; /* I2C8 */ } int get_soft_i2c_sda_pin(void) { if (I2C_ADAP_HWNR) - return exynos4x12_gpio_get(2, m2, 0); /* I2C9 */ + return EXYNOS4X12_GPIO_M20; /* I2C9 */ else - return exynos4x12_gpio_get(1, f1, 5); /* I2C8 */ + return EXYNOS4X12_GPIO_F15; /* I2C8 */ } #endif @@ -398,11 +388,9 @@ void exynos_lcd_power_on(void) { struct pmic *p = pmic_get("MAX77686_PMIC"); - gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1(); - /* LCD_2.2V_EN: GPC0[1] */ - s5p_gpio_set_pull(&gpio1->c0, 1, GPIO_PULL_UP); - s5p_gpio_direction_output(&gpio1->c0, 1, 1); + gpio_set_pull(EXYNOS4X12_GPIO_C01, S5P_GPIO_PULL_UP); + gpio_direction_output(EXYNOS4X12_GPIO_C01, 1); /* LDO25 VCC_3.1V_LCD */ pmic_probe(p); @@ -412,12 +400,10 @@ void exynos_lcd_power_on(void) void exynos_reset_lcd(void) { - gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1(); - /* reset lcd */ - s5p_gpio_direction_output(&gpio1->f2, 1, 0); + gpio_direction_output(EXYNOS4X12_GPIO_F21, 0); udelay(10); - s5p_gpio_set_value(&gpio1->f2, 1, 1); + gpio_set_value(EXYNOS4X12_GPIO_F21, 1); } void exynos_lcd_misc_init(vidinfo_t *vid) diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index f9d71b617d..25f2a935b7 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -27,8 +27,6 @@ DECLARE_GLOBAL_DATA_PTR; -struct exynos4_gpio_part1 *gpio1; -struct exynos4_gpio_part2 *gpio2; unsigned int board_rev; u32 get_board_rev(void) @@ -312,35 +310,35 @@ void exynos_cfg_lcd_gpio(void) for (i = 0; i < 8; i++) { /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */ - s5p_gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS4_GPIO_F00 + i, S5P_GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS4_GPIO_F10 + i, S5P_GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS4_GPIO_F20 + i, S5P_GPIO_FUNC(2)); /* pull-up/down disable */ - s5p_gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE); - s5p_gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE); - s5p_gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE); + gpio_set_pull(EXYNOS4_GPIO_F00 + i, S5P_GPIO_PULL_NONE); + gpio_set_pull(EXYNOS4_GPIO_F10 + i, S5P_GPIO_PULL_NONE); + gpio_set_pull(EXYNOS4_GPIO_F20 + i, S5P_GPIO_PULL_NONE); /* drive strength to max (24bit) */ - s5p_gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X); - s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW); - s5p_gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X); - s5p_gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW); - s5p_gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X); - s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW); + gpio_set_drv(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_4X); + gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW); + gpio_set_drv(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_4X); + gpio_set_rate(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_SLOW); + gpio_set_drv(EXYNOS4_GPIO_F20 + i, S5P_GPIO_DRV_4X); + gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW); } - for (i = 0; i < f3_end; i++) { + for (i = EXYNOS4_GPIO_F30; i < (EXYNOS4_GPIO_F30 + f3_end); i++) { /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */ - s5p_gpio_cfg_pin(&gpio1->f3, i, GPIO_FUNC(2)); + gpio_cfg_pin(i, S5P_GPIO_FUNC(2)); /* pull-up/down disable */ - s5p_gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE); + gpio_set_pull(i, S5P_GPIO_PULL_NONE); /* drive strength to max (24bit) */ - s5p_gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X); - s5p_gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW); + gpio_set_drv(i, S5P_GPIO_DRV_4X); + gpio_set_rate(i, S5P_GPIO_DRV_SLOW); } /* gpio pad configuration for LCD reset. */ - s5p_gpio_cfg_pin(&gpio2->y4, 5, GPIO_OUTPUT); + gpio_cfg_pin(EXYNOS4_GPIO_Y45, S5P_GPIO_OUTPUT); spi_init(); } @@ -352,11 +350,11 @@ int mipi_power(void) void exynos_reset_lcd(void) { - s5p_gpio_set_value(&gpio2->y4, 5, 1); + gpio_set_value(EXYNOS4_GPIO_Y45, 1); udelay(10000); - s5p_gpio_set_value(&gpio2->y4, 5, 0); + gpio_set_value(EXYNOS4_GPIO_Y45, 0); udelay(10000); - s5p_gpio_set_value(&gpio2->y4, 5, 1); + gpio_set_value(EXYNOS4_GPIO_Y45, 1); udelay(100); } @@ -386,9 +384,6 @@ void exynos_enable_ldo(unsigned int onoff) int exynos_init(void) { - gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE; - gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE; - gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210; switch (get_hwrev()) { @@ -399,7 +394,7 @@ int exynos_init(void) * you should set it HIGH since it removes the inverter */ /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */ - s5p_gpio_direction_output(&gpio1->e3, 6, 0); + gpio_direction_output(EXYNOS4_GPIO_E36, 0); break; default: /* @@ -407,7 +402,7 @@ int exynos_init(void) * But set it as HIGH to ensure */ /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */ - s5p_gpio_direction_output(&gpio1->e1, 3, 1); + gpio_direction_output(EXYNOS4_GPIO_E13, 1); break; } diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c index 11a0472c69..db7b673731 100644 --- a/drivers/gpio/s5p_gpio.c +++ b/drivers/gpio/s5p_gpio.c @@ -8,11 +8,9 @@ #include #include #include +#include -#define S5P_GPIO_GET_BANK(x) ((x >> S5P_GPIO_BANK_SHIFT) \ - & S5P_GPIO_BANK_MASK) - -#define S5P_GPIO_GET_PIN(x) (x & S5P_GPIO_PIN_MASK) +#define S5P_GPIO_GET_PIN(x) (x % GPIO_PER_BANK) #define CON_MASK(x) (0xf << ((x) << 2)) #define CON_SFR(x, v) ((v) << ((x) << 2)) @@ -28,7 +26,103 @@ #define RATE_MASK(x) (0x1 << (x + 16)) #define RATE_SET(x) (0x1 << (x + 16)) -void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg) +#define name_to_gpio(n) s5p_name_to_gpio(n) +static inline int s5p_name_to_gpio(const char *name) +{ + unsigned num, irregular_set_number, irregular_bank_base; + const struct gpio_name_num_table *tabp; + char this_bank, bank_name, irregular_bank_name; + char *endp; + + /* + * The gpio name starts with either 'g' or 'gp' followed by the bank + * name character. Skip one or two characters depending on the prefix. + */ + if (name[0] == 'g' && name[1] == 'p') + name += 2; + else if (name[0] == 'g') + name++; + else + return -1; /* Name must start with 'g' */ + + bank_name = *name++; + if (!*name) + return -1; /* At least one digit is required/expected. */ + + /* + * On both exynos5 and exynos5420 architectures there is a bank of + * GPIOs which does not fall into the regular address pattern. Those + * banks are c4 on Exynos5 and y7 on Exynos5420. The rest of the below + * assignments help to handle these irregularities. + */ +#if defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) + if (cpu_is_exynos5()) { + if (proid_is_exynos5420()) { + tabp = exynos5420_gpio_table; + irregular_bank_name = 'y'; + irregular_set_number = '7'; + irregular_bank_base = EXYNOS5420_GPIO_Y70; + } else { + tabp = exynos5_gpio_table; + irregular_bank_name = 'c'; + irregular_set_number = '4'; + irregular_bank_base = EXYNOS5_GPIO_C40; + } + } else { + if (proid_is_exynos4412()) + tabp = exynos4x12_gpio_table; + else + tabp = exynos4_gpio_table; + irregular_bank_name = 0; + irregular_set_number = 0; + irregular_bank_base = 0; + } +#else + if (cpu_is_s5pc110()) + tabp = s5pc110_gpio_table; + else + tabp = s5pc100_gpio_table; + irregular_bank_name = 0; + irregular_set_number = 0; + irregular_bank_base = 0; +#endif + + this_bank = tabp->bank; + do { + if (bank_name == this_bank) { + unsigned pin_index; /* pin number within the bank */ + if ((bank_name == irregular_bank_name) && + (name[0] == irregular_set_number)) { + pin_index = name[1] - '0'; + /* Irregular sets have 8 pins. */ + if (pin_index >= GPIO_PER_BANK) + return -1; + num = irregular_bank_base + pin_index; + } else { + pin_index = simple_strtoul(name, &endp, 8); + pin_index -= tabp->bank_offset; + /* + * Sanity check: bunk 'z' has no set number, + * for all other banks there must be exactly + * two octal digits, and the resulting number + * should not exceed the number of pins in the + * bank. + */ + if (((bank_name != 'z') && !name[1]) || + *endp || + (pin_index >= tabp->bank_size)) + return -1; + num = tabp->base + pin_index; + } + return num; + } + this_bank = (++tabp)->bank; + } while (this_bank); + + return -1; +} + +static void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg) { unsigned int value; @@ -38,18 +132,7 @@ void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg) writel(value, &bank->con); } -void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en) -{ - s5p_gpio_cfg_pin(bank, gpio, GPIO_OUTPUT); - s5p_gpio_set_value(bank, gpio, en); -} - -void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio) -{ - s5p_gpio_cfg_pin(bank, gpio, GPIO_INPUT); -} - -void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en) +static void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en) { unsigned int value; @@ -60,7 +143,19 @@ void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en) writel(value, &bank->dat); } -unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio) +static void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, + int gpio, int en) +{ + s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_OUTPUT); + s5p_gpio_set_value(bank, gpio, en); +} + +static void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio) +{ + s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_INPUT); +} + +static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio) { unsigned int value; @@ -68,7 +163,7 @@ unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio) return !!(value & DAT_MASK(gpio)); } -void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode) +static void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode) { unsigned int value; @@ -76,8 +171,8 @@ void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode) value &= ~PULL_MASK(gpio); switch (mode) { - case GPIO_PULL_DOWN: - case GPIO_PULL_UP: + case S5P_GPIO_PULL_DOWN: + case S5P_GPIO_PULL_UP: value |= PULL_MODE(gpio, mode); break; default: @@ -87,7 +182,7 @@ void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode) writel(value, &bank->pull); } -void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode) +static void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode) { unsigned int value; @@ -95,10 +190,10 @@ void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode) value &= ~DRV_MASK(gpio); switch (mode) { - case GPIO_DRV_1X: - case GPIO_DRV_2X: - case GPIO_DRV_3X: - case GPIO_DRV_4X: + case S5P_GPIO_DRV_1X: + case S5P_GPIO_DRV_2X: + case S5P_GPIO_DRV_3X: + case S5P_GPIO_DRV_4X: value |= DRV_SET(gpio, mode); break; default: @@ -108,7 +203,7 @@ void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode) writel(value, &bank->drv); } -void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) +static void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) { unsigned int value; @@ -116,8 +211,8 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) value &= ~RATE_MASK(gpio); switch (mode) { - case GPIO_DRV_FAST: - case GPIO_DRV_SLOW: + case S5P_GPIO_DRV_FAST: + case S5P_GPIO_DRV_SLOW: value |= RATE_SET(gpio); break; default: @@ -127,12 +222,31 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) writel(value, &bank->drv); } -struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio) +struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio) { - unsigned bank = S5P_GPIO_GET_BANK(gpio); - unsigned base = s5p_gpio_base(gpio); + const struct gpio_info *data; + unsigned int upto; + int i, count; - return (struct s5p_gpio_bank *)(base + bank); + data = get_gpio_data(); + count = get_bank_num(); + upto = 0; + + for (i = 0; i < count; i++) { + debug("i=%d, upto=%d\n", i, upto); + if (gpio < data->max_gpio) { + struct s5p_gpio_bank *bank; + bank = (struct s5p_gpio_bank *)data->reg_addr; + bank += (gpio - upto) / GPIO_PER_BANK; + debug("gpio=%d, bank=%p\n", gpio, bank); + return bank; + } + + upto = data->max_gpio; + data++; + } + + return NULL; } int s5p_gpio_get_pin(unsigned gpio) @@ -179,3 +293,27 @@ int gpio_set_value(unsigned gpio, int value) return 0; } + +void gpio_set_pull(int gpio, int mode) +{ + s5p_gpio_set_pull(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio), mode); +} + +void gpio_set_drv(int gpio, int mode) +{ + s5p_gpio_set_drv(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio), mode); +} + +void gpio_cfg_pin(int gpio, int cfg) +{ + s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio), cfg); +} + +void gpio_set_rate(int gpio, int mode) +{ + s5p_gpio_set_rate(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio), mode); +} From 9b97b727dcfbdc02a0a78e4c1d81670742f28784 Mon Sep 17 00:00:00 2001 From: Akshay Saraswat Date: Tue, 13 May 2014 10:30:15 +0530 Subject: [PATCH 12/12] S5P: Exynos: Config: Enable GPIO CMD config Enabling configs for GPIO CMD, EXYNOS4 family and replacing exynos_gpio_get with new linear GPIO pin number required because of the new function asking only 2 arguments (pin and value) instead of 3 (bank, pin and value). Signed-off-by: Akshay Saraswat Acked-by: Przemyslaw Marczak Signed-off-by: Minkyu Kang --- include/configs/exynos5-dt.h | 2 ++ include/configs/s5p_goni.h | 4 ++-- include/configs/s5pc210_universal.h | 16 ++++++++-------- include/configs/smdkv310.h | 1 + include/configs/trats.h | 8 ++++---- include/configs/trats2.h | 4 ++-- 6 files changed, 19 insertions(+), 16 deletions(-) diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-dt.h index 414db420dc..5a9b1b42d3 100644 --- a/include/configs/exynos5-dt.h +++ b/include/configs/exynos5-dt.h @@ -288,4 +288,6 @@ #define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_GPIO + #endif /* __CONFIG_H */ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 991c43e1cc..799d4fe9d8 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -214,8 +214,8 @@ /* * I2C Settings */ -#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get(j4, 3) -#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get(j4, 0) +#define CONFIG_SOFT_I2C_GPIO_SCL S5PC110_GPIO_J43 +#define CONFIG_SOFT_I2C_GPIO_SDA S5PC110_GPIO_J40 #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index db5561ab8c..eb046cdac9 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -167,8 +167,8 @@ /* * I2C Settings */ -#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(1, b, 7) -#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(1, b, 6) +#define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_B7 +#define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_B6 #define CONFIG_CMD_I2C @@ -193,10 +193,10 @@ */ #define CONFIG_SOFT_SPI #define CONFIG_SOFT_SPI_MODE SPI_MODE_3 -#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_get(2, y3, 1) -#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_get(2, y3, 3) -#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_get(2, y3, 0) -#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_get(2, y4, 3) +#define CONFIG_SOFT_SPI_GPIO_SCLK EXYNOS4_GPIO_Y31 +#define CONFIG_SOFT_SPI_GPIO_MOSI EXYNOS4_GPIO_Y33 +#define CONFIG_SOFT_SPI_GPIO_MISO EXYNOS4_GPIO_Y30 +#define CONFIG_SOFT_SPI_GPIO_CS EXYNOS4_GPIO_Y43 #define SPI_DELAY udelay(1) #undef SPI_INIT @@ -228,8 +228,8 @@ int universal_spi_read(void); #define KEY_PWR_INTERRUPT_REG MAX8998_REG_IRQ1 #define KEY_PWR_INTERRUPT_MASK (1 << 7) -#define KEY_VOL_UP_GPIO exynos4_gpio_get(2, x2, 0) -#define KEY_VOL_DOWN_GPIO exynos4_gpio_get(2, x2, 1) +#define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20 +#define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21 #endif /* __ASSEMBLY__ */ /* LCD console */ diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index 1388f49986..34adfaf608 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -12,6 +12,7 @@ /* High Level Configuration Options */ #define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ #define CONFIG_S5P 1 /* S5P Family */ +#define CONFIG_EXYNOS4 /* EXYNOS4 Family */ #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ #define CONFIG_SMDKV310 1 /* working with SMDKV310*/ diff --git a/include/configs/trats.h b/include/configs/trats.h index 815948bbff..fc16911686 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -204,8 +204,8 @@ #define CONFIG_SYS_I2C_INIT_BOARD /* I2C FG */ -#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(2, y4, 1) -#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(2, y4, 0) +#define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_Y41 +#define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_Y40 /* POWER */ #define CONFIG_POWER @@ -242,8 +242,8 @@ #define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1 #define KEY_PWR_INTERRUPT_MASK (1 << 0) -#define KEY_VOL_UP_GPIO exynos4_gpio_get(2, x2, 0) -#define KEY_VOL_DOWN_GPIO exynos4_gpio_get(2, x2, 1) +#define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20 +#define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21 #endif /* __ASSEMBLY__ */ /* LCD console */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 30a4b8cd8d..3d5f21dde0 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -222,8 +222,8 @@ int get_soft_i2c_sda_pin(void); #define KEY_PWR_INTERRUPT_REG MAX77686_REG_PMIC_INT1 #define KEY_PWR_INTERRUPT_MASK (1 << 1) -#define KEY_VOL_UP_GPIO exynos4x12_gpio_get(2, x2, 2) -#define KEY_VOL_DOWN_GPIO exynos4x12_gpio_get(2, x3, 3) +#define KEY_VOL_UP_GPIO EXYNOS4X12_GPIO_X22 +#define KEY_VOL_DOWN_GPIO EXYNOS4X12_GPIO_X33 #endif /* __ASSEMBLY__ */ /* LCD console */