kmp204x: set CPU watchdog reset reason flag
Check the core timer status register (TSR) for watchdog reset, and and set the QRIO's reset reason flag REASON1[0] accordingly. This allows the appliction SW to identify the cpu watchdog as a reset reason, by setting the REASON1[0] flag in the QRIO. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
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@ -80,14 +80,26 @@ int get_scl(void)
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#define ZL30158_RST 8
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#define ZL30158_RST 8
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#define BFTIC4_RST 0
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#define BFTIC4_RST 0
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#define RSTRQSR1_WDT_RR 0x00200000
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#define RSTRQSR1_SW_RR 0x00100000
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int board_early_init_f(void)
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int board_early_init_f(void)
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{
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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bool cpuwd_flag = false;
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/* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
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/* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
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setbits_be32(&gur->ddrclkdr, 0x001f000f);
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setbits_be32(&gur->ddrclkdr, 0x001f000f);
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/* set reset reason according CPU register */
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if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
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RSTRQSR1_WDT_RR)
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cpuwd_flag = true;
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qrio_cpuwd_flag(cpuwd_flag);
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/* clear CPU bits by writing 1 */
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setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
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/* set the BFTIC's prstcfg to reset at power-up and unit reset only */
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/* set the BFTIC's prstcfg to reset at power-up and unit reset only */
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qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
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qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
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/* and enable WD on it */
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/* and enable WD on it */
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