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powerpc/mpc85xx: Add workaround for DDR erratum A004934 

After DDR controller is enabled, it performs a calibration for the
transmit data vs DQS paths. During this calibration, the DDR controller
may make an inaccurate calculation, resulting in a non-optimal tap point.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
York Sun 2012-10-08 07:44:26 +00:00 committed by Andy Fleming
parent eb53941206
commit a1d558a20f
3 changed files with 7 additions and 0 deletions
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3
arch/powerpc/cpu/mpc85xx/cmd_errata.c
View File

@ -133,6 +133,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
puts("Work-around for Erratum SRIO-A004034 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
puts("Work-around for Erratum A004934 enabled\n");
#endif
return 0;
}

3
arch/powerpc/cpu/mpc85xx/ddr-gen3.c
View File

@ -140,6 +140,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->debug[i], regs->debug[i]);
}
}
#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
out_be32(&ddr->debug[28], 0x00003000);
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
out_be32(&ddr->debug[12], 0x00000015);

1
arch/powerpc/include/asm/config_mpc85xx.h
View File

@ -512,6 +512,7 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_A004468
#define CONFIG_SYS_FSL_ERRATUM_A_004934
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#elif defined(CONFIG_PPC_B4860)