PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance
AMCC suggested to set the PMU bit to 0 for best performace on the PPC440 DDR controller. Please see doc/README.440-DDR-performance for details. Patch by Stefan Roese, 28 Jul 2006
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Stefan Roese
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a2c95a7224
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@ -2,6 +2,12 @@
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Changes since U-Boot 1.1.4:
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======================================================================
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* PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance
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AMCC suggested to set the PMU bit to 0 for best performace on
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the PPC440 DDR controller.
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Please see doc/README.440-DDR-performance for details.
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Patch by Stefan Roese, 28 Jul 2006
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* AMCC bamboo (440EP) U-Boot image reduced to 384kbyte
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Please see doc/README.bamboo for details.
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Patch by Stefan Roese, 27 Jul 2006
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@ -313,13 +313,13 @@ void sdram_init(void)
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mtsdram(mem_tr0, 0x410a4012); /* ?? */
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mtsdram(mem_rtr, 0x04080000); /* ?? */
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mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
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mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
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mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */
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udelay(400); /* Delay 200 usecs (min) */
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/*--------------------------------------------------------------------
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* Enable the controller, then wait for DCEN to complete
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*------------------------------------------------------------------*/
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mtsdram(mem_cfg0, 0x84000000); /* Enable */
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mtsdram(mem_cfg0, 0x80000000); /* Enable */
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for (;;) {
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mfsdram(mem_mcsts, reg);
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@ -309,13 +309,13 @@ void sdram_init(void)
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mtsdram(mem_tr0, 0x410a4012); /* ?? */
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mtsdram(mem_rtr, 0x04080000); /* ?? */
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mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
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mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
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mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */
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udelay(400); /* Delay 200 usecs (min) */
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/*--------------------------------------------------------------------
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* Enable the controller, then wait for DCEN to complete
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*------------------------------------------------------------------*/
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mtsdram(mem_cfg0, 0x84000000); /* Enable */
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mtsdram(mem_cfg0, 0x80000000); /* Enable */
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for (;;) {
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mfsdram(mem_mcsts, reg);
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@ -379,7 +379,7 @@ long int initdram(int board_type)
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/*
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* Enable the controller, then wait for DCEN to complete
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*/
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mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
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mtsdram(mem_cfg0, 0x82000000); /* DCEN=1, PMUD=0, 64-bit */
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udelay(10000);
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if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
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@ -1007,9 +1007,9 @@ void program_cfg0(unsigned long* dimm_populated,
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}
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/*
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* program Page Management Unit
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* program Page Management Unit (0 == enabled)
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*/
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cfg0 |= SDRAM_CFG0_PMUD;
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cfg0 &= ~SDRAM_CFG0_PMUD;
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/*
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* program Memory Controller Options 0
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@ -0,0 +1,90 @@
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AMCC suggested to set the PMU bit to 0 for best performace on the
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PPC440 DDR controller. The 440er common DDR setup files (sdram.c &
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spd_sdram.c) are changed accordingly. So all 440er boards using
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these setup routines will automatically receive this performance
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increase.
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Please see below some benchmarks done by AMCC to demonstrate this
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performance changes:
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----------------------------------------
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SDRAM0_CFG0[PMU] = 1 (U-boot default for Bamboo, Yosemite and Yellowstone)
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----------------------------------------
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Stream benchmark results
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-------------------------------------------------------------
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This system uses 8 bytes per DOUBLE PRECISION word.
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-------------------------------------------------------------
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Array size = 2000000, Offset = 0
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Total memory required = 45.8 MB.
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Each test is run 10 times, but only
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the *best* time for each is used.
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-------------------------------------------------------------
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Your clock granularity/precision appears to be 1 microseconds.
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Each test below will take on the order of 112345 microseconds.
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(= 112345 clock ticks)
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Increase the size of the arrays if this shows that you are not getting
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at least 20 clock ticks per test.
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-------------------------------------------------------------
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WARNING -- The above is only a rough guideline.
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For best results, please be sure you know the precision of your system
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timer.
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-------------------------------------------------------------
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Function Rate (MB/s) RMS time Min time Max time
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Copy: 256.7683 0.1248 0.1246 0.1250
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Scale: 246.0157 0.1302 0.1301 0.1302
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Add: 255.0316 0.1883 0.1882 0.1885
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Triad: 253.1245 0.1897 0.1896 0.1899
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TTCP Benchmark Results
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ttcp-t: socket
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ttcp-t: connect
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ttcp-t: buflen=8192, nbuf=2048, align=16384/0, port=5000 tcp ->
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localhost
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ttcp-t: 16777216 bytes in 0.28 real seconds = 454.29 Mbit/sec +++
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ttcp-t: 2048 I/O calls, msec/call = 0.14, calls/sec = 7268.57
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ttcp-t: 0.0user 0.1sys 0:00real 60% 0i+0d 0maxrss 0+2pf 3+1506csw
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----------------------------------------
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SDRAM0_CFG0[PMU] = 0 (Suggested modification)
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Setting PMU = 0 provides a noticeable performance improvement *2% to
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5% improvement in memory performance.
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*Improves the Mbit/sec for TTCP benchmark by almost 76%.
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----------------------------------------
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Stream benchmark results
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-------------------------------------------------------------
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This system uses 8 bytes per DOUBLE PRECISION word.
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-------------------------------------------------------------
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Array size = 2000000, Offset = 0
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Total memory required = 45.8 MB.
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Each test is run 10 times, but only
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the *best* time for each is used.
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-------------------------------------------------------------
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Your clock granularity/precision appears to be 1 microseconds.
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Each test below will take on the order of 120066 microseconds.
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(= 120066 clock ticks)
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Increase the size of the arrays if this shows that you are not getting
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at least 20 clock ticks per test.
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-------------------------------------------------------------
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WARNING -- The above is only a rough guideline.
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For best results, please be sure you know the precision of your system
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timer.
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-------------------------------------------------------------
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Function Rate (MB/s) RMS time Min time Max time
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Copy: 262.5167 0.1221 0.1219 0.1223
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Scale: 258.4856 0.1238 0.1238 0.1240
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Add: 262.5404 0.1829 0.1828 0.1831
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Triad: 266.8594 0.1800 0.1799 0.1802
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TTCP Benchmark Results
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ttcp-t: socket
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ttcp-t: connect
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ttcp-t: buflen=8192, nbuf=2048, align=16384/0, port=5000 tcp ->
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localhost
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ttcp-t: 16777216 bytes in 0.16 real seconds = 804.06 Mbit/sec +++
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ttcp-t: 2048 I/O calls, msec/call = 0.08, calls/sec = 12864.89
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ttcp-t: 0.0user 0.0sys 0:00real 46% 0i+0d 0maxrss 0+2pf 120+1csw
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2006-07-28, Stefan Roese <sr@denx.de>
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