arm: mvebu: Add runtime boot-device detection
This patch adds runtime boot-device detection to SPL U-Boot. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Phil Sutter <phil@nwl.cc> Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
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@ -99,14 +99,24 @@
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#if defined(CONFIG_ARMADA_38X)
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#if defined(CONFIG_ARMADA_38X)
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/* SAR values for Armada 38x */
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/* SAR values for Armada 38x */
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#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600))
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#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600))
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#define SAR_CPU_FREQ_OFFS 10
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#define SAR_CPU_FREQ_OFFS 10
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#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS)
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#define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS)
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#define SAR_BOOT_DEVICE_OFFS 4
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#define SAR_BOOT_DEVICE_OFFS 4
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#define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS)
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#define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS)
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#define BOOT_DEV_SEL_OFFS 4
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#define BOOT_DEV_SEL_MASK (0x1f << BOOT_DEV_SEL_OFFS)
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#define BOOT_FROM_UART 0x28
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#define BOOT_FROM_SPI 0x32
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#define BOOT_FROM_MMC 0x30
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#define BOOT_FROM_MMC_ALT 0x31
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#else
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#else
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/* SAR values for Armada XP */
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/* SAR values for Armada XP */
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#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
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#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
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#define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234))
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#define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234))
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#define SAR_CPU_FREQ_OFFS 21
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#define SAR_CPU_FREQ_OFFS 21
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#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
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#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
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#define SAR_FFC_FREQ_OFFS 24
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#define SAR_FFC_FREQ_OFFS 24
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@ -115,6 +125,12 @@
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#define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS)
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#define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS)
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#define SAR_BOOT_DEVICE_OFFS 5
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#define SAR_BOOT_DEVICE_OFFS 5
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#define SAR_BOOT_DEVICE_MASK (0xf << SAR_BOOT_DEVICE_OFFS)
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#define SAR_BOOT_DEVICE_MASK (0xf << SAR_BOOT_DEVICE_OFFS)
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#define BOOT_DEV_SEL_OFFS 5
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#define BOOT_DEV_SEL_MASK (0xf << BOOT_DEV_SEL_OFFS)
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#define BOOT_FROM_UART 0x2
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#define BOOT_FROM_SPI 0x3
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#endif
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#endif
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#endif /* _MVEBU_SOC_H */
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#endif /* _MVEBU_SOC_H */
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
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* Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
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*
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*
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* SPDX-License-Identifier: GPL-2.0+
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* SPDX-License-Identifier: GPL-2.0+
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*/
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*/
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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static u32 get_boot_device(void)
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{
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u32 val;
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u32 boot_device;
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val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
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boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
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switch (boot_device) {
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#ifdef CONFIG_SPL_MMC_SUPPORT
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case BOOT_FROM_MMC:
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case BOOT_FROM_MMC_ALT:
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return BOOT_DEVICE_MMC1;
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#endif
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case BOOT_FROM_UART:
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return BOOT_DEVICE_UART;
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case BOOT_FROM_SPI:
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default:
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return BOOT_DEVICE_SPI;
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};
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}
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u32 spl_boot_device(void)
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u32 spl_boot_device(void)
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{
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{
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#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
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return get_boot_device();
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return BOOT_DEVICE_SPI;
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#endif
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#if defined(CONFIG_SPL_MMC_SUPPORT)
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return BOOT_DEVICE_MMC1;
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#endif
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}
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}
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#ifdef CONFIG_SPL_MMC_SUPPORT
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#ifdef CONFIG_SPL_MMC_SUPPORT
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