spi: xilinx_spi: Driver clean-up
- Zap unneeded macros - Re-arrange the code - Removed __attribute__((weak)) - Replace __func__ macro with func names to save macro transition. - Re-arranged comment lines. - Arrange driver code in more readable format[1] [1] http://patchwork.ozlabs.org/patch/265683/ Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Jagan Teki
parent
f93542a873
commit
a7b6ef05bf
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@ -1,79 +1,31 @@
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/*
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* Xilinx SPI driver
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*
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* supports 8 bit SPI transfers only, with or w/o FIFO
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* Supports 8 bit SPI transfers only, with or w/o FIFO
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*
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* based on bfin_spi.c, by way of altera_spi.c
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* Copyright (c) 2005-2008 Analog Devices Inc.
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* Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
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* Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
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* Based on bfin_spi.c, by way of altera_spi.c
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* Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
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* Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
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* Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
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* Copyright (c) 2005-2008 Analog Devices Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* [0]: http://www.xilinx.com/support/documentation
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*
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* [S]: [0]/ip_documentation/xps_spi.pdf
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* [0]/ip_documentation/axi_spi_ds742.pdf
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*/
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#include <config.h>
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#include <common.h>
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#include <malloc.h>
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#include <spi.h>
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/*
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* Xilinx SPI Register Definition
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* [0]: http://www.xilinx.com/support/documentation
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*
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* Xilinx SPI Register Definitions
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* [1]: [0]/ip_documentation/xps_spi.pdf
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* page 8, Register Descriptions
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* [2]: [0]/ip_documentation/axi_spi_ds742.pdf
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* page 7, Register Overview Table
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*/
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struct xilinx_spi_reg {
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u32 __space0__[7];
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u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */
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u32 ipisr; /* IP Interrupt Status Register (IPISR) */
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u32 __space1__;
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u32 ipier; /* IP Interrupt Enable Register (IPIER) */
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u32 __space2__[5];
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u32 srr; /* Softare Reset Register (SRR) */
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u32 __space3__[7];
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u32 spicr; /* SPI Control Register (SPICR) */
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u32 spisr; /* SPI Status Register (SPISR) */
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u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */
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u32 spidrr; /* SPI Data Receive Register (SPIDRR) */
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u32 spissr; /* SPI Slave Select Register (SPISSR) */
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u32 spitfor; /* SPI Transmit FIFO Occupancy Register (SPITFOR) */
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u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */
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};
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/* Device Global Interrupt Enable Register (dgier), [1] p15, [2] p15 */
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#define DGIER_GIE (1 << 31)
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/* IP Interrupt Status Register (ipisr), [1] p15, [2] p15 */
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#define IPISR_DRR_NOT_EMPTY (1 << 8)
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#define IPISR_SLAVE_SELECT (1 << 7)
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#define IPISR_TXF_HALF_EMPTY (1 << 6)
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#define IPISR_DRR_OVERRUN (1 << 5)
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#define IPISR_DRR_FULL (1 << 4)
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#define IPISR_DTR_UNDERRUN (1 << 3)
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#define IPISR_DTR_EMPTY (1 << 2)
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#define IPISR_SLAVE_MODF (1 << 1)
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#define IPISR_MODF (1 << 0)
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/* IP Interrupt Enable Register (ipier), [1] p17, [2] p18 */
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#define IPIER_DRR_NOT_EMPTY (1 << 8)
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#define IPIER_SLAVE_SELECT (1 << 7)
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#define IPIER_TXF_HALF_EMPTY (1 << 6)
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#define IPIER_DRR_OVERRUN (1 << 5)
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#define IPIER_DRR_FULL (1 << 4)
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#define IPIER_DTR_UNDERRUN (1 << 3)
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#define IPIER_DTR_EMPTY (1 << 2)
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#define IPIER_SLAVE_MODF (1 << 1)
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#define IPIER_MODF (1 << 0)
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/* Softare Reset Register (srr), [1] p9, [2] p8 */
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#define SRR_RESET_CODE 0x0000000A
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/* SPI Control Register (spicr), [1] p9, [2] p8 */
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#define SPICR_LSB_FIRST (1 << 9)
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@ -110,17 +62,42 @@ struct xilinx_spi_reg {
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#define SPISSR_ACT(cs) ~SPISSR_MASK(cs)
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#define SPISSR_OFF ~0UL
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/* SPI Transmit FIFO Occupancy Register (spitfor), [1] p13, [2] p14 */
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#define SPITFOR_OCYVAL_POS 0
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#define SPITFOR_OCYVAL_MASK (0xf << SPITFOR_OCYVAL_POS)
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/* SPI Receive FIFO Occupancy Register (spirfor), [1] p14, [2] p14 */
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#define SPIRFOR_OCYVAL_POS 0
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#define SPIRFOR_OCYVAL_MASK (0xf << SPIRFOR_OCYVAL_POS)
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/* SPI Software Reset Register (ssr) */
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#define SPISSR_RESET_VALUE 0x0a
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#define XILSPI_MAX_XFER_BITS 8
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#define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | SPICR_MASTER_MODE | \
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SPICR_SPE)
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#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
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#ifndef CONFIG_XILINX_SPI_IDLE_VAL
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#define CONFIG_XILINX_SPI_IDLE_VAL 0xff
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#endif
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#ifndef CONFIG_SYS_XILINX_SPI_LIST
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#define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE }
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#endif
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/* xilinx spi register set */
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struct xilinx_spi_reg {
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u32 __space0__[7];
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u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */
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u32 ipisr; /* IP Interrupt Status Register (IPISR) */
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u32 __space1__;
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u32 ipier; /* IP Interrupt Enable Register (IPIER) */
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u32 __space2__[5];
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u32 srr; /* Softare Reset Register (SRR) */
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u32 __space3__[7];
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u32 spicr; /* SPI Control Register (SPICR) */
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u32 spisr; /* SPI Status Register (SPISR) */
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u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */
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u32 spidrr; /* SPI Data Receive Register (SPIDRR) */
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u32 spissr; /* SPI Slave Select Register (SPISSR) */
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u32 spitfor; /* SPI Transmit FIFO Occupancy Register (SPITFOR) */
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u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */
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};
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/* xilinx spi slave */
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struct xilinx_spi_slave {
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struct spi_slave slave;
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struct xilinx_spi_reg *regs;
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@ -129,37 +106,17 @@ struct xilinx_spi_slave {
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};
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static inline struct xilinx_spi_slave *to_xilinx_spi_slave(
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struct spi_slave *slave)
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struct spi_slave *slave)
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{
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return container_of(slave, struct xilinx_spi_slave, slave);
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}
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#ifndef CONFIG_SYS_XILINX_SPI_LIST
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#define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE }
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#endif
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#ifndef CONFIG_XILINX_SPI_IDLE_VAL
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#define CONFIG_XILINX_SPI_IDLE_VAL 0xff
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#endif
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#define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | \
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SPICR_MASTER_MODE | \
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SPICR_SPE)
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#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | \
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SPICR_MANUAL_SS)
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#define XILSPI_MAX_XFER_BITS 8
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static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
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__attribute__((weak))
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus < ARRAY_SIZE(xilinx_spi_base_list) && cs < 32;
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}
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__attribute__((weak))
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void spi_cs_activate(struct spi_slave *slave)
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{
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struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
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@ -167,7 +124,6 @@ void spi_cs_activate(struct spi_slave *slave)
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writel(SPISSR_ACT(slave->cs), &xilspi->regs->spissr);
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}
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__attribute__((weak))
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
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@ -180,33 +136,26 @@ void spi_init(void)
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/* do nothing */
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}
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void spi_set_speed(struct spi_slave *slave, uint hz)
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{
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/* xilinx spi core does not support programmable speed */
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct xilinx_spi_slave *xilspi;
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if (!spi_cs_is_valid(bus, cs)) {
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printf("XILSPI error: %s: unsupported bus %d / cs %d\n",
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__func__, bus, cs);
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printf("XILSPI error: unsupported bus %d / cs %d\n", bus, cs);
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return NULL;
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}
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xilspi = spi_alloc_slave(struct xilinx_spi_slave, bus, cs);
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if (!xilspi) {
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printf("XILSPI error: %s: malloc of SPI structure failed\n",
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__func__);
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printf("XILSPI error: malloc of SPI structure failed\n");
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return NULL;
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}
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xilspi->regs = (struct xilinx_spi_reg *)xilinx_spi_base_list[bus];
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xilspi->freq = max_hz;
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xilspi->mode = mode;
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debug("%s: bus:%i cs:%i base:%p mode:%x max_hz:%d\n", __func__,
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bus, cs, xilspi->regs, xilspi->mode, xilspi->freq);
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debug("spi_setup_slave: bus:%i cs:%i base:%p mode:%x max_hz:%d\n",
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bus, cs, xilspi->regs, xilspi->mode, xilspi->freq);
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writel(SPISSR_RESET_VALUE, &xilspi->regs->srr);
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@ -225,7 +174,7 @@ int spi_claim_bus(struct spi_slave *slave)
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struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
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u32 spicr;
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debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
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debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
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writel(SPISSR_OFF, &xilspi->regs->spissr);
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spicr = XILSPI_SPICR_DFLT_ON;
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@ -246,7 +195,7 @@ void spi_release_bus(struct spi_slave *slave)
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{
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struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
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debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
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debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
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writel(SPISSR_OFF, &xilspi->regs->spissr);
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writel(XILSPI_SPICR_DFLT_OFF, &xilspi->regs->spicr);
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}
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@ -262,14 +211,15 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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unsigned rxecount = 17; /* max. 16 elements in FIFO, leftover 1 */
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unsigned global_timeout;
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debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
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slave->bus, slave->cs, bitlen, bytes, flags);
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debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n",
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slave->bus, slave->cs, bitlen, bytes, flags);
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if (bitlen == 0)
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goto done;
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if (bitlen % XILSPI_MAX_XFER_BITS) {
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printf("XILSPI warning: %s: Not a multiple of %d bits\n",
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__func__, XILSPI_MAX_XFER_BITS);
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printf("XILSPI warning: Not a multiple of %d bits\n",
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XILSPI_MAX_XFER_BITS);
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flags |= SPI_XFER_END;
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goto done;
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}
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@ -281,7 +231,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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}
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if (!rxecount) {
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printf("XILSPI error: %s: Rx buffer not empty\n", __func__);
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printf("XILSPI error: Rx buffer not empty\n");
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return -1;
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}
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@ -296,7 +246,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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unsigned timeout = global_timeout;
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/* get Tx element from data out buffer and count up */
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unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
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debug("%s: tx:%x ", __func__, d);
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debug("spi_xfer: tx:%x ", d);
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/* write out and wait for processing (receive data) */
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writel(d & SPIDTR_8BIT_MASK, &xilspi->regs->spidtr);
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@ -307,7 +257,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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}
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if (!timeout) {
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printf("XILSPI error: %s: Xfer timeout\n", __func__);
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printf("XILSPI error: Xfer timeout\n");
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return -1;
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}
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@ -315,7 +265,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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d = readl(&xilspi->regs->spidrr) & SPIDRR_8BIT_MASK;
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if (rxp)
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*rxp++ = d;
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debug("rx:%x\n", d);
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debug("spi_xfer: rx:%x\n", d);
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}
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done:
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