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board: k2e-evm: add board support 

This patch adds Keystone2 k2e_evm evaluation board support.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
This commit is contained in:
Hao Zhang 2014-07-16 00:59:27 +03:00 committed by Tom Rini
parent 1284246eb9
commit a906847966
8 changed files with 178 additions and 0 deletions
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1
arch/arm/include/asm/arch-keystone/hardware.h
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@ -119,6 +119,7 @@ typedef volatile unsigned int *dv_reg_p;
#define KS2_PLL_CNTRL_BASE 0x02310000
#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE
#define KS2_RSTCTRL_RSTYPE (KS2_PLL_CNTRL_BASE + 0xe4)
#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8)
#define KS2_RSTCTRL_KEY 0x5a69
#define KS2_RSTCTRL_MASK 0xffff0000

2
board/ti/ks2_evm/Makefile
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@ -9,3 +9,5 @@ obj-y += board.o
obj-y += ddr3_cfg.o
obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
obj-$(CONFIG_K2E_EVM) += board_k2e.o
obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o

39
board/ti/ks2_evm/board_k2e.c Normal file
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@ -0,0 +1,39 @@
/*
* K2E EVM : Board initialization
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/ddr3.h>
#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
unsigned int external_clk[ext_clk_count] = {
[sys_clk] = 100000000,
[alt_core_clk] = 100000000,
[pa_clk] = 100000000,
[ddr3_clk] = 100000000,
[mcm_clk] = 312500000,
[pcie_clk] = 100000000,
[sgmii_clk] = 156250000,
[xgmii_clk] = 156250000,
[usb_clk] = 100000000,
};
static struct pll_init_data pll_config[] = {
CORE_PLL_1200,
PASS_PLL_1000,
};
#if defined(CONFIG_BOARD_EARLY_INIT_F)
int board_early_init_f(void)
{
init_plls(ARRAY_SIZE(pll_config), pll_config);
return 0;
}
#endif

40
board/ti/ks2_evm/ddr3_cfg.c
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@ -93,6 +93,46 @@ struct ddr3_emif_config ddr3_1333_2g = {
};
#endif
#ifdef CONFIG_K2E_EVM
/* DDR3 PHY configuration data with 1600M rate, and 4GB size */
struct ddr3_phy_config ddr3phy_1600_4g = {
.pllcr = 0x0001C000ul,
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
.ptr0 = 0x42C21590ul,
.ptr1 = 0xD05612C0ul,
.ptr2 = 0, /* not set in gel */
.ptr3 = 0x08861A80ul,
.ptr4 = 0x0C827100ul,
.dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
.dcr_val = ((1 << 10)),
.dtpr0 = 0x9D9CBB66ul,
.dtpr1 = 0x12840300ul,
.dtpr2 = 0x5002D200ul,
.mr0 = 0x00001C70ul,
.mr1 = 0x00000006ul,
.mr2 = 0x00000018ul,
.dtcr = 0x710035C7ul,
.pgcr2 = 0x00F07A12ul,
.zq0cr1 = 0x0001005Dul,
.zq1cr1 = 0x0001005Bul,
.zq2cr1 = 0x0001005Bul,
.pir_v1 = 0x00000033ul,
.pir_v2 = 0x0000FF81ul,
};
/* DDR3 EMIF configuration data with 1600M rate, and 4GB size */
struct ddr3_emif_config ddr3_1600_4g = {
.sdcfg = 0x6200CE62ul,
.sdtim1 = 0x166C9855ul,
.sdtim2 = 0x00001D4Aul,
.sdtim3 = 0x421DFF53ul,
.sdtim4 = 0x543F07FFul,
.zqcfg = 0x70073200ul,
.sdrfc = 0x00001869ul,
};
#endif
int ddr3_get_dimm_params(char *dimm_name)
{
int ret;

3
board/ti/ks2_evm/ddr3_cfg.h
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@ -16,6 +16,9 @@ extern struct ddr3_emif_config ddr3_1600_8g;
extern struct ddr3_phy_config ddr3phy_1333_2g;
extern struct ddr3_emif_config ddr3_1333_2g;
extern struct ddr3_phy_config ddr3phy_1600_4g;
extern struct ddr3_emif_config ddr3_1600_4g;
int ddr3_get_dimm_params(char *dimm_name);
#endif /* __DDR3_CFG_H */

55
board/ti/ks2_evm/ddr3_k2e.c Normal file
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@ -0,0 +1,55 @@
/*
* Keystone2: DDR3 initialization
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include "ddr3_cfg.h"
#include <asm/arch/ddr3.h>
static int ddr3_size;
static struct pll_init_data ddr3_400 = DDR3_PLL_400;
void ddr3_init(void)
{
char dimm_name[32];
if (~(readl(KS2_PLL_CNTRL_BASE + KS2_RSTCTRL_RSTYPE) & 0x1))
init_pll(&ddr3_400);
ddr3_get_dimm_params(dimm_name);
printf("Detected SO-DIMM [%s]\n", dimm_name);
/* Reset DDR3 PHY after PLL enabled */
ddr3_reset_ddrphy();
if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
/* 8G SO-DIMM */
ddr3_size = 8;
printf("DRAM: 8 GiB\n");
ddr3phy_1600_8g.zq0cr1 |= 0x10000;
ddr3phy_1600_8g.zq1cr1 |= 0x10000;
ddr3phy_1600_8g.zq2cr1 |= 0x10000;
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_8g);
} else if (!strcmp(dimm_name, "18KSF51272HZ-1G6K2")) {
/* 4G SO-DIMM */
ddr3_size = 4;
printf("DRAM: 4 GiB\n");
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_4g);
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_4g);
}
}
/**
* ddr3_get_size - return ddr3 size in GiB
*/
int ddr3_get_size(void)
{
return ddr3_size;
}

1
boards.cfg
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@ -301,6 +301,7 @@ Active arm armv7 exynos samsung trats2
Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Przemyslaw Marczak <p.marczak@samsung.com>
Active arm armv7 highbank - highbank highbank - Rob Herring <robh@kernel.org>
Active arm armv7 keystone ti ks2_evm k2hk_evm - Vitaly Andrianov <vitalya@ti.com>
Active arm armv7 keystone ti ks2_evm k2e_evm - Vitaly Andrianov <vitalya@ti.com>
Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut <marek.vasut@gmail.com>
Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg -
Active arm armv7 mx5 freescale mx51evk mx51evk mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg Stefano Babic <sbabic@denx.de>

37
include/configs/k2e_evm.h Normal file
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@ -0,0 +1,37 @@
/*
* Configuration header file for TI's k2e-evm
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_K2E_EVM_H
#define __CONFIG_K2E_EVM_H
/* Platform type */
#define CONFIG_SOC_K2E
#define CONFIG_K2E_EVM
/* U-Boot general configuration */
#define CONFIG_SYS_PROMPT "K2E EVM # "
#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0"
#define KS2_FDT_NAME "name_fdt=k2e-evm.dtb\0"
#define KS2_ADDR_MON "addr_mon=0x0c140000\0"
#define KS2_NAME_MON "name_mon=skern-k2e-evm.bin\0"
#define NAME_UBOOT "name_uboot=u-boot-spi-k2e-evm.gph\0"
#define NAME_UBI "name_ubi=k2e-evm-ubifs.ubi\0"
#include <configs/ks2_evm.h>
/* SPL SPI Loader Configuration */
#define CONFIG_SPL_TEXT_BASE 0x0c100000
/* NAND Configuration */
#define CONFIG_SYS_NAND_PAGE_2K
#endif /* __CONFIG_K2E_EVM_H */