Blackfin: update anomaly lists
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
4ace2823bc
commit
a9d6777d39
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@ -2,7 +2,7 @@
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* File: include/asm-blackfin/mach-bf527/anomaly.h
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* Copyright (C) 2004-2008 Analog Devices Inc.
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* Copyright (C) 2004-2009 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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@ -167,12 +167,16 @@
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#define ANOMALY_05000263 (0)
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#define ANOMALY_05000266 (0)
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#define ANOMALY_05000273 (0)
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#define ANOMALY_05000278 (0)
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#define ANOMALY_05000285 (0)
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#define ANOMALY_05000305 (0)
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#define ANOMALY_05000307 (0)
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#define ANOMALY_05000311 (0)
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#define ANOMALY_05000312 (0)
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#define ANOMALY_05000323 (0)
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#define ANOMALY_05000363 (0)
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#define ANOMALY_05000412 (0)
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#define ANOMALY_05000447 (0)
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#define ANOMALY_05000448 (0)
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#endif
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@ -2,7 +2,7 @@
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* File: include/asm-blackfin/mach-bf533/anomaly.h
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* Copyright (C) 2004-2008 Analog Devices Inc.
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* Copyright (C) 2004-2009 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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@ -160,7 +160,7 @@
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#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
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/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
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#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
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/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
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/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
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#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
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/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
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#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
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@ -278,9 +278,12 @@
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#define ANOMALY_05000266 (0)
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#define ANOMALY_05000323 (0)
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#define ANOMALY_05000353 (1)
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#define ANOMALY_05000380 (0)
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#define ANOMALY_05000386 (1)
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#define ANOMALY_05000412 (0)
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#define ANOMALY_05000432 (0)
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#define ANOMALY_05000435 (0)
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#define ANOMALY_05000447 (0)
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#define ANOMALY_05000448 (0)
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#endif
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@ -2,7 +2,7 @@
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* File: include/asm-blackfin/mach-bf537/anomaly.h
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* Copyright (C) 2004-2008 Analog Devices Inc.
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* Copyright (C) 2004-2009 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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@ -110,7 +110,7 @@
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#define ANOMALY_05000301 (1)
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/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
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#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
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/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
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/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
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#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
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/* SCKELOW Bit Does Not Maintain State Through Hibernate */
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#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
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@ -168,9 +168,12 @@
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#define ANOMALY_05000323 (0)
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#define ANOMALY_05000353 (1)
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#define ANOMALY_05000363 (0)
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#define ANOMALY_05000380 (0)
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#define ANOMALY_05000386 (1)
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#define ANOMALY_05000412 (0)
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#define ANOMALY_05000432 (0)
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#define ANOMALY_05000435 (0)
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#define ANOMALY_05000447 (0)
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#define ANOMALY_05000448 (0)
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#endif
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@ -2,12 +2,12 @@
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* File: include/asm-blackfin/mach-bf548/anomaly.h
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* Copyright (C) 2004-2008 Analog Devices Inc.
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* Copyright (C) 2004-2009 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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/* This file shoule be up to date with:
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* - Revision G, 08/07/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
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* - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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@ -91,8 +91,6 @@
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#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
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/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
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#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
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/* Mobile DDR Operation Not Functional */
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#define ANOMALY_05000377 (1)
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/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
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#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
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/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
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@ -157,8 +155,22 @@
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#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
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/* Software System Reset Corrupts PLL_LOCKCNT Register */
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#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
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/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
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#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
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/* OTP Write Accesses Not Supported */
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#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
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/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
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#define ANOMALY_05000443 (1)
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/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
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#define ANOMALY_05000446 (1)
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/* UART IrDA Receiver Fails on Extended Bit Pulses */
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#define ANOMALY_05000447 (1)
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/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
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#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
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/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
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#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
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/* USB DMA Mode 1 Short Packet Data Corruption */
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#define ANOMALY_05000450 (1
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000125 (0)
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@ -171,10 +183,13 @@
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#define ANOMALY_05000263 (0)
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#define ANOMALY_05000266 (0)
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#define ANOMALY_05000273 (0)
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#define ANOMALY_05000278 (0)
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#define ANOMALY_05000305 (0)
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#define ANOMALY_05000307 (0)
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#define ANOMALY_05000311 (0)
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#define ANOMALY_05000323 (0)
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#define ANOMALY_05000363 (0)
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#define ANOMALY_05000380 (0)
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#define ANOMALY_05000412 (0)
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#define ANOMALY_05000432 (0)
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#define ANOMALY_05000435 (0)
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@ -2,7 +2,7 @@
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* File: include/asm-blackfin/mach-bf561/anomaly.h
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* Copyright (C) 2004-2008 Analog Devices Inc.
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* Copyright (C) 2004-2009 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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@ -224,7 +224,7 @@
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#define ANOMALY_05000301 (1)
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/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
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#define ANOMALY_05000302 (1)
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/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
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/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
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#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
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/* SCKELOW Bit Does Not Maintain State Through Hibernate */
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#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
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@ -283,8 +283,11 @@
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#define ANOMALY_05000273 (0)
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#define ANOMALY_05000311 (0)
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#define ANOMALY_05000353 (1)
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#define ANOMALY_05000380 (0)
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#define ANOMALY_05000386 (1)
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#define ANOMALY_05000432 (0)
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#define ANOMALY_05000435 (0)
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#define ANOMALY_05000447 (0)
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#define ANOMALY_05000448 (0)
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#endif
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