ARM: mxs: Add Creative ZEN XFi3 board
Add STMP3780-based XFi3 board. This board is a small PMP device sporting a CPU which was later rebranded to i.MX233 . Currently supported is USB gadget mode and both external SD and internal Phison SD-NAND bridge . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Marek Vasut
Stefano Babic
parent
e24278aff2
commit
aa04fef49c
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@ -980,6 +980,7 @@ Marek Vasut <marek.vasut@gmail.com>
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vpac270 xscale/pxa
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zipitz2 xscale/pxa
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mx23_olinuxino i.MX23
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xfi3 i.MX23
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m28evk i.MX28
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sc_sps_1 i.MX28
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m53evk i.MX53
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@ -0,0 +1,31 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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ifndef CONFIG_SPL_BUILD
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COBJS := xfi3.o
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else
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COBJS := spl_boot.o
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endif
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,134 @@
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/*
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* Creative ZEN X-Fi3 setup
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*
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* Copyright (C) 2013 Marek Vasut <marex@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/io.h>
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#include <asm/arch/iomux-mx23.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#define MUX_CONFIG_EMI (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_PULLUP)
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#define MUX_CONFIG_SSP (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
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#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
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const iomux_cfg_t iomux_setup[] = {
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/* EMI */
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MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
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MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI,
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MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
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MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
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MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
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MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
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MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
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MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
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MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
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MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD,
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MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD,
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MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD,
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MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD,
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MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD,
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MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD,
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MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD,
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MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD,
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MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD,
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MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD,
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MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
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MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
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MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
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MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
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MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
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MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
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MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
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MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
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MX23_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD,
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MX23_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD,
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MX23_PAD_LCD_WR__LCD_WR | MUX_CONFIG_LCD,
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MX23_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
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MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
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MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
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MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP,
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MX23_PAD_SSP1_DETECT__GPIO_2_1 | MUX_CONFIG_SSP,
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MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP,
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MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP,
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MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP,
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MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP,
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MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP,
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MX23_PAD_GPMI_D07__GPIO_0_7 | MUX_CONFIG_SSP,
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MX23_PAD_GPMI_D00__SSP2_DATA0 | MUX_CONFIG_SSP,
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MX23_PAD_GPMI_D01__SSP2_DATA1 | MUX_CONFIG_SSP,
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MX23_PAD_GPMI_D02__SSP2_DATA2 | MUX_CONFIG_SSP,
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MX23_PAD_GPMI_D03__SSP2_DATA3 | MUX_CONFIG_SSP,
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MX23_PAD_GPMI_RDY1__SSP2_CMD | MUX_CONFIG_SSP,
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MX23_PAD_GPMI_WRN__SSP2_SCK | MUX_CONFIG_SSP,
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/* PWM -- FIXME */
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MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP,
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};
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void mxs_adjust_memory_params(uint32_t *dram_vals)
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{
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/* mDDR configuration values */
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const uint32_t regs[] = {
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0x01010001, 0x00010000, 0x01000000, 0x00000001,
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0x00010101, 0x00000001, 0x00010000, 0x01000001,
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0x01010000, 0x00000001, 0x07000200, 0x04070203,
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0x02020002, 0x06070a02, 0x0d000201, 0x0305000d,
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0x02080800, 0x19330f0a, 0x1f1f1c00, 0x020a1313,
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0x03061323, 0x0000000a, 0x00080008, 0x00200020,
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0x00200020, 0x00200020, 0x000003f7, 0x00000000,
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0x00000000, 0x00000000, 0x00000020, 0x00000000,
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0x001023cd, 0x20410010, 0x00006665, 0x00000000,
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0x00000101, 0x00000001, 0x00000000, 0x00000000,
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};
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memcpy(dram_vals, regs, sizeof(regs));
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}
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void board_init_ll(const uint32_t arg, const uint32_t *resptr)
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{
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mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
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}
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@ -0,0 +1,224 @@
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/*
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* Creative ZEN X-Fi3 board
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*
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* Copyright (C) 2013 Marek Vasut <marex@denx.de>
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*
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* Hardware investigation done by:
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*
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* Amaury Pouly <amaury.pouly@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/iomux-mx23.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Functions
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*/
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int board_early_init_f(void)
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{
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/* IO0 clock at 480MHz */
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mxs_set_ioclk(MXC_IOCLK0, 480000);
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/* SSP0 clock at 96MHz */
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mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
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return 0;
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}
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int dram_init(void)
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{
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return mxs_dram_init();
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}
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#ifdef CONFIG_CMD_MMC
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static int xfi3_mmc_cd(int id)
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{
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switch (id) {
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case 0:
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/* The SSP_DETECT is inverted on this board. */
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return gpio_get_value(MX23_PAD_SSP1_DETECT__GPIO_2_1);
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case 1:
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/* Phison bridge always present */
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return 1;
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default:
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return 0;
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}
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}
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int board_mmc_init(bd_t *bis)
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{
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int ret;
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/* MicroSD slot */
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gpio_direction_input(MX23_PAD_SSP1_DETECT__GPIO_2_1);
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gpio_direction_output(MX23_PAD_GPMI_D07__GPIO_0_7, 0);
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ret = mxsmmc_initialize(bis, 0, NULL, xfi3_mmc_cd);
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if (ret)
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return ret;
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/* Phison SD-NAND bridge */
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ret = mxsmmc_initialize(bis, 1, NULL, xfi3_mmc_cd);
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return ret;
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}
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#endif
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#ifdef CONFIG_VIDEO_MXS
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static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
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{
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struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
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const unsigned int timeout = 0x10000;
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if (mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
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timeout))
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return -ETIMEDOUT;
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writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
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(1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET),
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®s->hw_lcdif_transfer_count);
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writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN,
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®s->hw_lcdif_ctrl_clr);
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if (data)
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writel(LCDIF_CTRL_DATA_SELECT, ®s->hw_lcdif_ctrl_set);
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writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
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if (mxs_wait_mask_clr(®s->hw_lcdif_lcdif_stat_reg, 1 << 29,
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timeout))
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return -ETIMEDOUT;
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writel(payload, ®s->hw_lcdif_data);
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return mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
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timeout);
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}
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static void mxsfb_write_register(uint32_t reg, uint32_t data)
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{
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mxsfb_write_byte(reg, 0);
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mxsfb_write_byte(data, 1);
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}
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static const struct {
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uint8_t reg;
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uint8_t delay;
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uint16_t val;
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} lcd_regs[] = {
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{ 0x01, 0, 0x001c },
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{ 0x02, 0, 0x0100 },
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/* Writing 0x30 to reg. 0x03 flips the LCD */
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{ 0x03, 0, 0x1038 },
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{ 0x08, 0, 0x0808 },
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/* This can contain 0x111 to rotate the LCD. */
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{ 0x0c, 0, 0x0000 },
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{ 0x0f, 0, 0x0c01 },
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{ 0x20, 0, 0x0000 },
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{ 0x21, 30, 0x0000 },
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/* Wait 30 mS here */
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{ 0x10, 0, 0x0a00 },
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{ 0x11, 30, 0x1038 },
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/* Wait 30 mS here */
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{ 0x12, 0, 0x1010 },
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{ 0x13, 0, 0x0050 },
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{ 0x14, 0, 0x4f58 },
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{ 0x30, 0, 0x0000 },
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{ 0x31, 0, 0x00db },
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{ 0x32, 0, 0x0000 },
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{ 0x33, 0, 0x0000 },
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{ 0x34, 0, 0x00db },
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{ 0x35, 0, 0x0000 },
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{ 0x36, 0, 0x00af },
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{ 0x37, 0, 0x0000 },
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{ 0x38, 0, 0x00db },
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{ 0x39, 0, 0x0000 },
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{ 0x50, 0, 0x0000 },
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{ 0x51, 0, 0x0705 },
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{ 0x52, 0, 0x0e0a },
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{ 0x53, 0, 0x0300 },
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{ 0x54, 0, 0x0a0e },
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{ 0x55, 0, 0x0507 },
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{ 0x56, 0, 0x0000 },
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{ 0x57, 0, 0x0003 },
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{ 0x58, 0, 0x090a },
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{ 0x59, 30, 0x0a09 },
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/* Wait 30 mS here */
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{ 0x07, 30, 0x1017 },
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/* Wait 40 mS here */
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{ 0x36, 0, 0x00af },
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{ 0x37, 0, 0x0000 },
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{ 0x38, 0, 0x00db },
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{ 0x39, 0, 0x0000 },
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{ 0x20, 0, 0x0000 },
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{ 0x21, 0, 0x0000 },
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};
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void board_mxsfb_system_setup(void)
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{
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struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
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int i;
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/* Switch the LCDIF into System-Mode */
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writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE |
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LCDIF_CTRL_BYPASS_COUNT, ®s->hw_lcdif_ctrl_clr);
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/* Restart the SmartLCD controller */
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mdelay(50);
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writel(1, ®s->hw_lcdif_ctrl1_set);
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mdelay(50);
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writel(1, ®s->hw_lcdif_ctrl1_clr);
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mdelay(50);
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writel(1, ®s->hw_lcdif_ctrl1_set);
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mdelay(50);
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/* Program the SmartLCD controller */
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writel(LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, ®s->hw_lcdif_ctrl1_set);
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writel((0x03 << LCDIF_TIMING_CMD_HOLD_OFFSET) |
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(0x03 << LCDIF_TIMING_CMD_SETUP_OFFSET) |
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(0x03 << LCDIF_TIMING_DATA_HOLD_OFFSET) |
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(0x02 << LCDIF_TIMING_DATA_SETUP_OFFSET),
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®s->hw_lcdif_timing);
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/*
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* OTM2201A init and configuration sequence.
|
||||
*/
|
||||
for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) {
|
||||
mxsfb_write_register(lcd_regs[i].reg, lcd_regs[i].val);
|
||||
if (lcd_regs[i].delay)
|
||||
mdelay(lcd_regs[i].delay);
|
||||
}
|
||||
/* Turn on Framebuffer Upload Mode */
|
||||
mxsfb_write_byte(0x22, 0);
|
||||
|
||||
writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT,
|
||||
®s->hw_lcdif_ctrl_set);
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* Adress of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
||||
|
||||
/* Turn on PWM backlight */
|
||||
gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
usb_eth_initialize(bis);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -206,6 +206,7 @@ mx28evk arm arm926ejs mx28evk freesca
|
|||
mx28evk_nand arm arm926ejs mx28evk freescale mxs mx28evk:ENV_IS_IN_NAND
|
||||
mx28evk_auart_console arm arm926ejs mx28evk freescale mxs mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC
|
||||
sc_sps_1 arm arm926ejs sc_sps_1 schulercontrol mxs
|
||||
xfi3 arm arm926ejs xfi3 creative mxs xfi3
|
||||
nhk8815 arm arm926ejs nhk8815 st nomadik
|
||||
nhk8815_onenand arm arm926ejs nhk8815 st nomadik nhk8815:BOOT_ONENAND
|
||||
omap5912osk arm arm926ejs - ti omap
|
||||
|
|
|
|||
|
|
@ -0,0 +1,69 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Marek Vasut <marex@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef __CONFIGS_XFI3_H__
|
||||
#define __CONFIGS_XFI3_H__
|
||||
|
||||
/* System configurations */
|
||||
#define CONFIG_MX23 /* i.MX23 SoC */
|
||||
|
||||
/* U-Boot Commands */
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
#include <config_cmd_default.h>
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_GPIO
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_VIDEO
|
||||
|
||||
/* Memory configuration */
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
|
||||
#define PHYS_SDRAM_1 0x40000000 /* Base address */
|
||||
#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
|
||||
/* Environment */
|
||||
#define CONFIG_ENV_SIZE (16 * 1024)
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* Booting Linux */
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 "
|
||||
#define CONFIG_LOADADDR 0x42000000
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
/* LCD */
|
||||
#ifdef CONFIG_VIDEO
|
||||
#define CONFIG_VIDEO_FONT_4X6
|
||||
#define CONFIG_VIDEO_MXS_MODE_SYSTEM
|
||||
#define CONFIG_SYS_BLACK_IN_WRITE
|
||||
#define LCD_BPP LCD_COLOR16
|
||||
#endif
|
||||
|
||||
/* USB */
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_EHCI_MXS_PORT0
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
|
||||
#define CONFIG_MV_UDC /* ChipIdea CI13xxx UDC */
|
||||
#define CONFIG_USB_GADGET_DUALSPEED
|
||||
|
||||
#define CONFIG_USB_ETHER
|
||||
#define CONFIG_USB_ETH_CDC
|
||||
#define CONFIG_NETCONSOLE
|
||||
#endif
|
||||
|
||||
/* The rest of the configuration is shared */
|
||||
#include <configs/mxs.h>
|
||||
|
||||
#endif /* __CONFIGS_XFI3_H__ */
|
||||
Loading…
Reference in New Issue