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u-boot
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Merge branch 'master' of /home/wd/git/u-boot/master

This commit is contained in:
Wolfgang Denk 2010-08-03 22:45:13 +02:00
parent e9aecdec15 7385c28e9b
commit ac956293be
183 changed files with 2368 additions and 4448 deletions
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4
MAINTAINERS
View File

@ -262,10 +262,6 @@ Sangmoon Kim <dogoil@etinsys.com>
debris MPC8245
KVME080 MPC8245
Thomas Lange <thomas@corelatus.se>
GTH MPC860
Robert Lazarski <robertlazarski@gmail.com>
ATUM8548 MPC8548

1
MAKEALL
View File

@ -118,7 +118,6 @@ LIST_8xx=" \
GEN860T \
GEN860T_SC \
GENIETV \
GTH \
hermes \
IAD210 \
ICU862_100MHz \

10
README
View File

@ -1495,6 +1495,16 @@ The following options need to be configured:
#define I2C_DELAY udelay(2)
CONFIG_SOFT_I2C_GPIO_SCL / CONFIG_SOFT_I2C_GPIO_SDA
If your arch supports the generic GPIO framework (asm/gpio.h),
then you may alternatively define the two GPIOs that are to be
used as SCL / SDA. Any of the previous I2C_xxx macros will
have GPIO-based defaults assigned to them as appropriate.
You should define these to the GPIO value as given directly to
the generic GPIO functions.
CONFIG_SYS_I2C_INIT_BOARD
When a board is reset during an i2c bus transfer

6
arch/powerpc/cpu/mpc512x/diu.c
View File

@ -111,10 +111,8 @@ int mpc5121diu_init_show_bmp(cmd_tbl_t *cmdtp,
{
unsigned int addr;
if (argc < 2) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 2)
return cmd_usage(cmdtp);
if (!strncmp(argv[1], "init", 4)) {
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)

10
arch/powerpc/cpu/mpc8260/bedbug_603e.c
View File

@ -71,10 +71,7 @@ void bedbug603e_do_break (cmd_tbl_t *cmdtp, int flag, int argc,
/* -------------------------------------------------- */
if (argc < 2)
{
cmd_usage(cmdtp);
return;
}
return cmd_usage(cmdtp);
/* Turn off a breakpoint */
@ -118,10 +115,7 @@ void bedbug603e_do_break (cmd_tbl_t *cmdtp, int flag, int argc,
if(!(( isdigit( argv[ 1 ][ 0 ] )) ||
(( argv[ 1 ][ 0 ] >= 'a' ) && ( argv[ 1 ][ 0 ] <= 'f' )) ||
(( argv[ 1 ][ 0 ] >= 'A' ) && ( argv[ 1 ][ 0 ] <= 'F' ))))
{
cmd_usage(cmdtp);
return;
}
return cmd_usage(cmdtp);
addr = simple_strtoul( argv[ 1 ], NULL, 16 );

9
arch/powerpc/cpu/mpc83xx/ecc.c
View File

@ -118,10 +118,8 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
writeback[0] = 0x01234567UL;
writeback[1] = 0x89abcdefUL;
if (argc > 4) {
cmd_usage(cmdtp);
return 1;
}
if (argc > 4)
return cmd_usage(cmdtp);
if (argc == 2) {
if (strcmp(argv[1], "status") == 0) {
@ -350,8 +348,7 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
return 0;
}
}
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
U_BOOT_CMD(ecc, 4, 0, do_ecc,

2
arch/powerpc/cpu/mpc85xx/Makefile
View File

@ -58,7 +58,9 @@ COBJS-$(CONFIG_P1021) += ddr-gen3.o
COBJS-$(CONFIG_P1022) += ddr-gen3.o
COBJS-$(CONFIG_P2010) += ddr-gen3.o
COBJS-$(CONFIG_P2020) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o
COBJS-$(CONFIG_CPM2) += ether_fcc.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o

2
arch/powerpc/cpu/mpc85xx/cpu.c
View File

@ -179,7 +179,7 @@ int checkcpu (void)
#ifdef CONFIG_SYS_DPAA_FMAN
for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
printf(" FMAN%d: %s MHz\n", i,
printf(" FMAN%d: %s MHz\n", i + 1,
strmhz(buf1, sysinfo.freqFMan[i]));
}
#endif

12
arch/powerpc/cpu/mpc85xx/cpu_init.c
View File

@ -39,10 +39,6 @@
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_MPC8536
extern void fsl_serdes_init(void);
#endif
#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
@ -185,9 +181,6 @@ void cpu_init_f (void)
/* Config QE ioports */
config_qe_ioports();
#endif
#if defined(CONFIG_MPC8536)
fsl_serdes_init();
#endif
#if defined(CONFIG_FSL_DMA)
dma_init();
#endif
@ -332,6 +325,11 @@ int cpu_init_r(void)
qe_reset();
#endif
#if defined(CONFIG_SYS_HAS_SERDES)
/* needs to be in ram since code uses global static vars */
fsl_serdes_init();
#endif
#if defined(CONFIG_MP)
setup_mp();
#endif

24
arch/powerpc/cpu/mpc85xx/fdt.c
View File

@ -298,17 +298,17 @@ void fdt_add_enet_stashing(void *fdt)
}
#if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
static void ft_fixup_clks(void *blob, const char *alias, unsigned long freq)
static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
unsigned long freq)
{
const char *path = fdt_get_alias(blob, alias);
int off = fdt_path_offset(blob, path);
phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
if (off >= 0) {
off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
if (off > 0)
printf("WARNING enable to set clock-frequency "
"for %s: %s\n", alias, fdt_strerror(off));
"for %s: %s\n", compat, fdt_strerror(off));
}
}
@ -317,14 +317,17 @@ static void ft_fixup_dpaa_clks(void *blob)
sys_info_t sysinfo;
get_sys_info(&sysinfo);
ft_fixup_clks(blob, "fman0", sysinfo.freqFMan[0]);
ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
sysinfo.freqFMan[0]);
#if (CONFIG_SYS_NUM_FMAN == 2)
ft_fixup_clks(blob, "fman1", sysinfo.freqFMan[1]);
ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
sysinfo.freqFMan[1]);
#endif
#ifdef CONFIG_SYS_DPAA_PME
ft_fixup_clks(blob, "pme", sysinfo.freqPME);
do_fixup_by_compat_u32(blob, "fsl,pme",
"clock-frequency", sysinfo.freqPME, 1);
#endif
}
#else
@ -400,6 +403,11 @@ void ft_cpu_setup(void *blob, bd_t *bd)
"clock-frequency", bd->bi_brgfreq, 1);
#endif
#ifdef CONFIG_FSL_CORENET
do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
#endif
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
#ifdef CONFIG_MP

66
arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
View File

@ -66,10 +66,11 @@
#define FSL_SRDSCR3_LANEE_SGMII 0x00000000
#define FSL_SRDSCR3_LANEE_SATA 0x00150005
#define SRDS1_MAX_LANES 8
#define SRDS2_MAX_LANES 2
static u32 serdes1_prtcl_map, serdes2_prtcl_map;
static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
[0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
[0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
@ -86,39 +87,12 @@ static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
int is_serdes_configured(enum srds_prtcl device)
{
int i;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int ret = (1 << device) & serdes1_prtcl_map;
u32 srds2_cfg = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >>
GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT;
if (ret)
return ret;
debug("%s: dev = %d\n", __FUNCTION__, device);
debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg);
debug("PORDEVSR[SRDS2_IO_SEL] = %x\n", srds2_cfg);
if (srds1_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds1_cfg);
return 0;
}
if (srds2_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_cfg);
return 0;
}
for (i = 0; i < SRDS1_MAX_LANES; i++) {
if (serdes1_cfg_tbl[srds1_cfg][i] == device)
return 1;
}
for (i = 0; i < SRDS2_MAX_LANES; i++) {
if (serdes2_cfg_tbl[srds2_cfg][i] == device)
return 1;
}
return 0;
return (1 << device) & serdes2_prtcl_map;
}
void fsl_serdes_init(void)
@ -126,13 +100,20 @@ void fsl_serdes_init(void)
void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
void *sd = (void *)CONFIG_SYS_MPC85xx_SERDES2_ADDR;
u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS);
u32 srds2_io_sel;
u32 srds1_io_sel, srds2_io_sel;
u32 tmp;
int lane;
srds1_io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
/* parse the SRDS2_IO_SEL of PORDEVSR */
srds2_io_sel = (pordevsr & GUTS_PORDEVSR_SERDES2_IO_SEL)
>> GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT;
debug("PORDEVSR[SRDS1_IO_SEL] = %x\n", srds1_io_sel);
debug("PORDEVSR[SRDS2_IO_SEL] = %x\n", srds2_io_sel);
switch (srds2_io_sel) {
case 1: /* Lane A - SATA1, Lane E - SATA2 */
/* CR 0 */
@ -246,4 +227,23 @@ void fsl_serdes_init(void)
default:
break;
}
if (srds1_io_sel > ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[SRDS1_IO_SEL] = %d\n", srds1_io_sel);
return;
}
for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_io_sel][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
if (srds2_io_sel > ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_io_sel);
return;
}
for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds2_io_sel][lane];
serdes2_prtcl_map |= (1 << lane_prtcl);
}
}

38
arch/powerpc/cpu/mpc85xx/p1022_serdes.c
View File

@ -17,6 +17,8 @@
#define SRDS1_MAX_LANES 4
#define SRDS2_MAX_LANES 2
static u32 serdes1_prtcl_map, serdes2_prtcl_map;
static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
[0x00] = {NONE, NONE, NONE, NONE},
[0x01] = {NONE, NONE, NONE, NONE},
@ -72,27 +74,41 @@ static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
};
int is_serdes_configured(enum srds_prtcl device)
{
int ret = (1 << device) & serdes1_prtcl_map;
if (ret)
return ret;
return (1 << device) & serdes2_prtcl_map;
}
void fsl_serdes_init(void)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
unsigned int i;
int lane;
debug("%s: dev = %d\n", __FUNCTION__, device);
debug("PORDEVSR[IO_SEL] = 0x%x\n", srds_cfg);
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds_cfg);
return 0;
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
for (i = 0; i < SRDS1_MAX_LANES; i++) {
if (serdes1_cfg_tbl[srds_cfg][i] == device)
return 1;
if (serdes2_cfg_tbl[srds_cfg][i] == device)
return 1;
if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
return 0;
for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
serdes2_prtcl_map |= (1 << lane_prtcl);
}
}

10
arch/powerpc/cpu/mpc8xx/bedbug_860.c
View File

@ -70,10 +70,7 @@ void bedbug860_do_break (cmd_tbl_t *cmdtp, int flag, int argc,
/* -------------------------------------------------- */
if (argc < 2)
{
cmd_usage(cmdtp);
return;
}
return cmd_usage(cmdtp);
/* Turn off a breakpoint */
@ -121,10 +118,7 @@ void bedbug860_do_break (cmd_tbl_t *cmdtp, int flag, int argc,
/* Set a breakpoint at the address */
if( !isdigit( argv[ 1 ][ 0 ]))
{
cmd_usage(cmdtp);
return;
}
return cmd_usage(cmdtp);
addr = simple_strtoul( argv[ 1 ], NULL, 16 ) & 0xfffffffc;

3
arch/powerpc/cpu/mpc8xx/cpu_init.c
View File

@ -149,8 +149,7 @@ void cpu_init_f (volatile immap_t * immr)
* I owe him a free beer. - wd]
*/
#if defined(CONFIG_GTH) || \
defined(CONFIG_HERMES) || \
#if defined(CONFIG_HERMES) || \
defined(CONFIG_ICU862) || \
defined(CONFIG_IP860) || \
defined(CONFIG_IVML24) || \

6
arch/powerpc/cpu/mpc8xxx/cpu.c
View File

@ -80,10 +80,16 @@ struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(P2010, P2010_E, 1),
CPU_TYPE_ENTRY(P2020, P2020, 2),
CPU_TYPE_ENTRY(P2020, P2020_E, 2),
CPU_TYPE_ENTRY(P3041, P3041, 4),
CPU_TYPE_ENTRY(P3041, P3041_E, 4),
CPU_TYPE_ENTRY(P4040, P4040, 4),
CPU_TYPE_ENTRY(P4040, P4040_E, 4),
CPU_TYPE_ENTRY(P4080, P4080, 8),
CPU_TYPE_ENTRY(P4080, P4080_E, 8),
CPU_TYPE_ENTRY(P5010, P5010, 1),
CPU_TYPE_ENTRY(P5010, P5010_E, 1),
CPU_TYPE_ENTRY(P5020, P5020, 2),
CPU_TYPE_ENTRY(P5020, P5020_E, 2),
#elif defined(CONFIG_MPC86xx)
CPU_TYPE_ENTRY(8610, 8610, 1),
CPU_TYPE_ENTRY(8641, 8641, 2),

12
arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
View File

@ -767,6 +767,13 @@ static u32 DQS_calibration_methodB(struct ddrautocal *cal)
debug("\n\n");
#if defined(CONFIG_DDR_RFDC_FIXED)
mtsdram(SDRAM_RFDC, CONFIG_DDR_RFDC_FIXED);
size = 512;
rffd_average = CONFIG_DDR_RFDC_FIXED & SDRAM_RFDC_RFFD_MASK;
mfsdram(SDRAM_RDCC, rdcc); /* record this value */
cal->rdcc = rdcc;
#else /* CONFIG_DDR_RFDC_FIXED */
in_window = 0;
rdcc = 0;
@ -830,6 +837,7 @@ static u32 DQS_calibration_methodB(struct ddrautocal *cal)
rffd_average = SDRAM_RFDC_RFFD_MAX;
mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
#endif /* CONFIG_DDR_RFDC_FIXED */
rffd = rffd_average;
in_window = 0;
@ -1211,10 +1219,14 @@ u32 DQS_autocalibration(void)
debug("*** best_result: read value SDRAM_RQDC 0x%08x\n",
rqdc_reg);
#if defined(CONFIG_DDR_RFDC_FIXED)
mtsdram(SDRAM_RFDC, CONFIG_DDR_RFDC_FIXED);
#else /* CONFIG_DDR_RFDC_FIXED */
mfsdram(SDRAM_RFDC, rfdc_reg);
rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
mtsdram(SDRAM_RFDC, rfdc_reg |
SDRAM_RFDC_RFFD_ENCODE(tcal.autocal.rffd));
#endif /* CONFIG_DDR_RFDC_FIXED */
mfsdram(SDRAM_RFDC, rfdc_reg);
debug("*** best_result: read value SDRAM_RFDC 0x%08x\n",

3
arch/powerpc/cpu/ppc4xx/Makefile
View File

@ -51,6 +51,9 @@ COBJS += cpu_init.o
COBJS += denali_data_eye.o
COBJS += denali_spd_ddr2.o
COBJS += ecc.o
ifdef CONFIG_CMD_ECCTEST
COBJS += cmd_ecctest.o
endif
COBJS += fdt.o
COBJS += interrupts.o
COBJS += iop480_uart.o

284
arch/powerpc/cpu/ppc4xx/cmd_ecctest.c Normal file
View File

@ -0,0 +1,284 @@
/*
* (C) Copyright 2010
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/cache.h>
#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) || \
defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
#if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC)
#if defined(CONFIG_405EX)
/*
* Currently only 405EX uses 16bit data bus width as an alternative
* option to 32bit data width (SDRAM0_MCOPT1_WDTH)
*/
#define SDRAM_DATA_ALT_WIDTH 2
#else
#define SDRAM_DATA_ALT_WIDTH 8
#endif
#if defined(CONFIG_SYS_OCM_BASE)
#define CONFIG_FUNC_ISRAM_ADDR CONFIG_SYS_OCM_BASE
#endif
#if defined(CONFIG_SYS_ISRAM_BASE)
#define CONFIG_FUNC_ISRAM_ADDR CONFIG_SYS_ISRAM_BASE
#endif
#if !defined(CONFIG_FUNC_ISRAM_ADDR)
#error "No internal SRAM/OCM provided!"
#endif
#define force_inline inline __attribute__ ((always_inline))
static inline void machine_check_disable(void)
{
mtmsr(mfmsr() & ~MSR_ME);
}
static inline void machine_check_enable(void)
{
mtmsr(mfmsr() | MSR_ME);
}
/*
* These helper functions need to be inlined, since they
* are called from the functions running from internal SRAM.
* SDRAM operation is forbidden at that time, so calling
* functions in SDRAM has to be avoided.
*/
static force_inline void wait_ddr_idle(void)
{
u32 val;
do {
mfsdram(SDRAM_MCSTAT, val);
} while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
}
static force_inline void recalibrate_ddr(void)
{
u32 val;
/*
* Rewrite RQDC & RFDC to calibrate again. If this is not
* done, the SDRAM controller is working correctly after
* changing the MCOPT1_MCHK bits.
*/
mfsdram(SDRAM_RQDC, val);
mtsdram(SDRAM_RQDC, val);
mfsdram(SDRAM_RFDC, val);
mtsdram(SDRAM_RFDC, val);
}
static force_inline void set_mcopt1_mchk(u32 bits)
{
u32 val;
wait_ddr_idle();
mfsdram(SDRAM_MCOPT1, val);
mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) | bits);
recalibrate_ddr();
}
/*
* The next 2 functions are copied to internal SRAM/OCM and run
* there. No function calls allowed here. No SDRAM acitivity should
* be done here.
*/
static void inject_ecc_error(void *ptr, int par)
{
u32 val;
/*
* Taken from PPC460EX/EXr/GT users manual (Rev 1.21)
* 22.2.17.13 ECC Diagnostics
*
* Items 1 ... 5 are already done by now, running from RAM
* with ECC enabled
*/
out_be32(ptr, 0x00000000);
val = in_be32(ptr);
/* 6. Set memory controller to no error checking */
set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_NON);
/* 7. Modify one or two bits for error simulation */
if (par == 1)
out_be32(ptr, in_be32(ptr) ^ 0x00000001);
else
out_be32(ptr, in_be32(ptr) ^ 0x00000003);
/* 8. Wait for SDRAM idle */
val = in_be32(ptr);
set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_CHK_REP);
/* Wait for SDRAM idle */
wait_ddr_idle();
/* Continue with 9. in calling function... */
}
static void rewrite_ecc_parity(void *ptr, int par)
{
u32 current_address = (u32)ptr;
u32 end_address;
u32 address_increment;
u32 mcopt1;
u32 val;
/*
* Fill ECC parity byte again. Otherwise further accesses to
* the failure address will result in exceptions.
*/
/* Wait for SDRAM idle */
val = in_be32(0x00000000);
set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_GEN);
/* ECC bit set method for non-cached memory */
mfsdram(SDRAM_MCOPT1, mcopt1);
if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
address_increment = 4;
else
address_increment = SDRAM_DATA_ALT_WIDTH;
end_address = current_address + CONFIG_SYS_CACHELINE_SIZE;
while (current_address < end_address) {
*((unsigned long *)current_address) = 0;
current_address += address_increment;
}
set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_CHK_REP);
/* Wait for SDRAM idle */
wait_ddr_idle();
}
static int do_ecctest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u32 old_val;
u32 val;
u32 *ptr;
void (*sram_func)(u32 *, int);
int error;
if (argc < 3) {
cmd_usage(cmdtp);
return 1;
}
ptr = (u32 *)simple_strtoul(argv[1], NULL, 16);
error = simple_strtoul(argv[2], NULL, 16);
if ((error < 1) || (error > 2)) {
cmd_usage(cmdtp);
return 1;
}
printf("Using address %p for %d bit ECC error injection\n",
ptr, error);
/*
* Save value to restore it later on
*/
old_val = in_be32(ptr);
/*
* Copy ECC injection function into internal SRAM/OCM
*/
sram_func = (void *)CONFIG_FUNC_ISRAM_ADDR;
memcpy((void *)CONFIG_FUNC_ISRAM_ADDR, inject_ecc_error, 0x10000);
/*
* Disable interrupts and exceptions before calling this
* function in internal SRAM/OCM
*/
disable_interrupts();
machine_check_disable();
eieio();
/*
* Jump to ECC simulation function in internal SRAM/OCM
*/
(*sram_func)(ptr, error);
/* 10. Read the corresponding address */
val = in_be32(ptr);
/*
* Read and print ECC status register/info:
* The faulting address is only known upon uncorrectable ECC
* errors.
*/
mfsdram(SDRAM_ECCES, val);
if (val & SDRAM_ECCES_CE)
printf("ECC: Correctable error\n");
if (val & SDRAM_ECCES_UE) {
printf("ECC: Uncorrectable error at 0x%02x%08x\n",
mfdcr(SDRAM_ERRADDULL), mfdcr(SDRAM_ERRADDLLL));
}
/*
* Clear pending interrupts/exceptions
*/
mtsdram(SDRAM_ECCES, 0xffffffff);
mtdcr(SDRAM_ERRSTATLL, 0xff000000);
set_mcsr(get_mcsr());
/* Now enable interrupts and exceptions again */
eieio();
machine_check_enable();
enable_interrupts();
/*
* The ECC parity byte need to be re-written for the
* corresponding address. Otherwise future accesses to it
* will result in exceptions.
*
* Jump to ECC parity generation function
*/
memcpy((void *)CONFIG_FUNC_ISRAM_ADDR, rewrite_ecc_parity, 0x10000);
(*sram_func)(ptr, 0);
/*
* Restore value in corresponding address
*/
out_be32(ptr, old_val);
return 0;
}
U_BOOT_CMD(
ecctest, 3, 0, do_ecctest,
"Test ECC by single and double error bit injection",
"address 1/2"
);
#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */
#endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)... */

21
arch/powerpc/cpu/ppc4xx/ecc.c
View File

@ -130,7 +130,26 @@ static void program_ecc_addr(unsigned long start_address,
/* clear ECC error repoting registers */
mtsdram(SDRAM_ECCES, 0xffffffff);
mtdcr(0x4c, 0xffffffff);
#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
/*
* IBM DDR(1) core (440GX):
* Clear Mx bits in SDRAM0_BESR0/1
*/
mtsdram(SDRAM0_BESR0, 0xffffffff);
mtsdram(SDRAM0_BESR1, 0xffffffff);
#elif defined(CONFIG_440)
/*
* 440/460 DDR2 core:
* Clear EMID (Error PLB Master ID) in MQ0_ESL
*/
mtdcr(SDRAM_ERRSTATLL, 0xfff00000);
#else
/*
* 405EX(r) DDR2 core:
* Clear M0ID (Error PLB Master ID) in SDRAM_BESR
*/
mtsdram(SDRAM_BESR, 0xf0000000);
#endif
mtsdram(SDRAM_MCOPT1,
(mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);

16
arch/powerpc/cpu/ppc4xx/traps.c
View File

@ -209,6 +209,22 @@ MachineCheckException(struct pt_regs *regs)
/* Clear MCSR */
mtspr(SPRN_MCSR, val);
}
#if defined(CONFIG_DDR_ECC) && defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
/*
* Read and print ECC status register/info:
* The faulting address is only known upon uncorrectable ECC
* errors.
*/
mfsdram(SDRAM_ECCES, val);
if (val & SDRAM_ECCES_CE)
printf("ECC: Correctable error\n");
if (val & SDRAM_ECCES_UE) {
printf("ECC: Uncorrectable error at 0x%02x%08x\n",
mfdcr(SDRAM_ERRADDULL), mfdcr(SDRAM_ERRADDLLL));
}
#endif /* CONFIG_DDR_ECC ... */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
mfsdram(DDR0_00, val) ;
printf("DDR0: DDR0_00 %lx\n", val);

4
arch/powerpc/include/asm/config.h
View File

@ -44,8 +44,12 @@
defined(CONFIG_P1021) || defined(CONFIG_P1022) || \
defined(CONFIG_P2020) || defined(CONFIG_MPC8641)
#define CONFIG_MAX_CPUS 2
#elif defined(CONFIG_PPC_P3041)
#define CONFIG_MAX_CPUS 4
#elif defined(CONFIG_PPC_P4080)
#define CONFIG_MAX_CPUS 8
#elif defined(CONFIG_PPC_P5020)
#define CONFIG_MAX_CPUS 2
#else
#define CONFIG_MAX_CPUS 1
#endif

84
arch/powerpc/include/asm/fsl_pci.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2007,2009 Freescale Semiconductor, Inc.
* Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -29,8 +29,8 @@ int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
int fsl_is_pci_agent(struct pci_controller *hose);
void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data);
void fsl_pci_config_unlock(struct pci_controller *hose);
void ft_fsl_pci_setup(void *blob, const char *pci_alias,
struct pci_controller *hose);
void ft_fsl_pci_setup(void *blob, const char *pci_compat,
struct pci_controller *hose, unsigned long ctrl_addr);
/*
* Common PCI/PCIE Register structure for mpc85xx and mpc86xx
@ -202,4 +202,82 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
x.pci_num = num; \
}
#define __FT_FSL_PCI_SETUP(blob, compat, num) \
ft_fsl_pci_setup(blob, compat, &pci##num##_hose, \
CONFIG_SYS_PCI##num##_ADDR)
#define __FT_FSL_PCI_DEL(blob, compat, num) \
ft_fsl_pci_setup(blob, compat, NULL, CONFIG_SYS_PCI##num##_ADDR)
#define __FT_FSL_PCIE_SETUP(blob, compat, num) \
ft_fsl_pci_setup(blob, compat, &pcie##num##_hose, \
CONFIG_SYS_PCIE##num##_ADDR)
#define __FT_FSL_PCIE_DEL(blob, compat, num) \
ft_fsl_pci_setup(blob, compat, NULL, CONFIG_SYS_PCIE##num##_ADDR)
#ifdef CONFIG_PCI1
#define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1)
#else
#define FT_FSL_PCI1_SETUP __FT_FSL_PCI_DEL(blob, FSL_PCI_COMPAT, 1)
#endif
#ifdef CONFIG_PCI2
#define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2)
#else
#define FT_FSL_PCI2_SETUP __FT_FSL_PCI_DEL(blob, FSL_PCI_COMPAT, 2)
#endif
#ifdef CONFIG_PCIE1
#define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 1)
#else
#define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 1)
#endif
#ifdef CONFIG_PCIE2
#define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 2)
#else
#define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 2)
#endif
#ifdef CONFIG_PCIE3
#define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3)
#else
#define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 3)
#endif
#ifdef CONFIG_PCIE4
#define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4)
#else
#define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 4)
#endif
#if defined(CONFIG_FSL_CORENET)
#define FSL_PCIE_COMPAT "fsl,p4080-pcie"
#define FT_FSL_PCI_SETUP \
FT_FSL_PCIE1_SETUP; \
FT_FSL_PCIE2_SETUP; \
FT_FSL_PCIE3_SETUP; \
FT_FSL_PCIE4_SETUP;
#elif defined(CONFIG_MPC85xx)
#define FSL_PCI_COMPAT "fsl,mpc8540-pci"
#define FSL_PCIE_COMPAT "fsl,mpc8548-pcie"
#define FT_FSL_PCI_SETUP \
FT_FSL_PCI1_SETUP; \
FT_FSL_PCI2_SETUP; \
FT_FSL_PCIE1_SETUP; \
FT_FSL_PCIE2_SETUP; \
FT_FSL_PCIE3_SETUP;
#elif defined(CONFIG_MPC86xx)
#define FSL_PCI_COMPAT "fsl,mpc8610-pci"
#define FSL_PCIE_COMPAT "fsl,mpc8641-pcie"
#define FT_FSL_PCI_SETUP \
FT_FSL_PCI1_SETUP; \
FT_FSL_PCIE1_SETUP; \
FT_FSL_PCIE2_SETUP;
#else
#error FT_FSL_PCI_SETUP not defined
#endif
#endif

1
arch/powerpc/include/asm/fsl_serdes.h
View File

@ -44,5 +44,6 @@ enum srds_prtcl {
};
int is_serdes_configured(enum srds_prtcl device);
void fsl_serdes_init(void);
#endif /* __FSL_SERDES_H */

20
arch/powerpc/include/asm/immap_85xx.h
View File

@ -2060,8 +2060,17 @@ typedef struct ccsr_sec {
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x6000
#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
#define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
#define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
#define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
#else
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
#endif
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
@ -2138,6 +2147,17 @@ typedef struct ccsr_sec {
#define CONFIG_SYS_FSL_SEC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_PCI1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
#define CONFIG_SYS_PCI2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
#define CONFIG_SYS_PCIE1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
#define CONFIG_SYS_PCIE2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
#define CONFIG_SYS_PCIE3_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)

17
arch/powerpc/include/asm/immap_86xx.h
View File

@ -1257,6 +1257,23 @@ extern immap_t *immr;
#define CONFIG_SYS_MPC86xx_DMA_OFFSET (0x21000)
#define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
#define CONFIG_SYS_MPC86xx_PCI1_OFFSET 0x8000
#ifdef CONFIG_MPC8610
#define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0xa000
#else
#define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0x8000
#endif
#define CONFIG_SYS_MPC86xx_PCIE2_OFFSET 0x9000
#define CONFIG_SYS_PCI1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCI1_OFFSET)
#define CONFIG_SYS_PCI2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCI2_OFFSET)
#define CONFIG_SYS_PCIE1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCIE1_OFFSET)
#define CONFIG_SYS_PCIE2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCIE2_OFFSET)
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_MDIO1_OFFSET 0x24000
#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)

10
arch/powerpc/include/asm/ppc4xx-sdram.h
View File

@ -63,6 +63,8 @@
#define SDRAM_CFG0 0x20 /* memory controller options 0 */
#define SDRAM_CFG1 0x21 /* memory controller options 1 */
#define SDRAM0_BESR0 0x0000 /* bus error status reg 0 */
#define SDRAM0_BESR1 0x0008 /* bus error status reg 1 */
#define SDRAM0_BEAR 0x0010 /* bus error address reg */
#define SDRAM0_SLIO 0x0018 /* ddr sdram slave interface options */
#define SDRAM0_CFG0 0x0020 /* ddr sdram options 0 */
@ -363,6 +365,7 @@
/*
* Memory controller registers
*/
#ifdef CONFIG_405EX
#define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */
#define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */
#define SDRAM_BEARL 0x02 /* PLB bus error address low */
@ -371,11 +374,10 @@
#define SDRAM_WMIRQT 0x07 /* PLB write master interrupt (test/set) */
#define SDRAM_PLBOPT 0x08 /* PLB slave options */
#define SDRAM_PUABA 0x09 /* PLB upper address base */
#ifndef CONFIG_405EX
#define SDRAM_MCSTAT 0x14 /* memory controller status */
#else
#define SDRAM_MCSTAT 0x1F /* memory controller status */
#endif
#else /* CONFIG_405EX */
#define SDRAM_MCSTAT 0x14 /* memory controller status */
#endif /* CONFIG_405EX */
#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */

6
arch/powerpc/include/asm/processor.h
View File

@ -1052,10 +1052,16 @@
#define SVR_P2010_E 0x80EB00
#define SVR_P2020 0x80E200
#define SVR_P2020_E 0x80EA00
#define SVR_P3041 0x821103
#define SVR_P3041_E 0x821903
#define SVR_P4040 0x820100
#define SVR_P4040_E 0x820900
#define SVR_P4080 0x820000
#define SVR_P4080_E 0x820800
#define SVR_P5010 0x822100
#define SVR_P5010_E 0x822900
#define SVR_P5020 0x822000
#define SVR_P5020_E 0x822800
#define SVR_8610 0x80A000
#define SVR_8641 0x809000

6
board/amcc/acadia/cmd_acadia.c
View File

@ -44,10 +44,8 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[
u8 *buf;
int cpu_freq;
if (argc < 3) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 3)
return cmd_usage(cmdtp);
cpu_freq = simple_strtol(argv[1], NULL, 10);
if (cpu_freq != 267) {

64
board/amcc/canyonlands/canyonlands.c
View File

@ -34,7 +34,17 @@ extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH ch
DECLARE_GLOBAL_DATA_PTR;
#define CONFIG_SYS_BCSR3_PCIE 0x10
struct board_bcsr {
u8 board_id;
u8 cpld_rev;
u8 led_user;
u8 board_status;
u8 reset_ctrl;
u8 flash_ctrl;
u8 eth_ctrl;
u8 usb_ctrl;
u8 irq_ctrl;
};
#define BOARD_CANYONLANDS_PCIE 1
#define BOARD_CANYONLANDS_SATA 2
@ -112,6 +122,9 @@ int board_early_init_f(void)
{
#if !defined(CONFIG_ARCHES)
u32 sdr0_cust0;
struct board_bcsr *bcsr_data =
(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
#endif
/*
@ -172,14 +185,10 @@ int board_early_init_f(void)
#if !defined(CONFIG_ARCHES)
/* Enable ethernet and take out of reset */
out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0);
out_8(&bcsr_data->eth_ctrl, 0) ;
/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
out_8((void *)CONFIG_SYS_BCSR_BASE + 5, 0);
/* Enable USB host & USB-OTG */
out_8((void *)CONFIG_SYS_BCSR_BASE + 7, 0);
out_8(&bcsr_data->flash_ctrl, 0) ;
mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
/* Setup PLB4-AHB bridge based on the system address map */
@ -201,6 +210,41 @@ int board_early_init_f(void)
return 0;
}
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
int usb_board_init(void)
{
struct board_bcsr *bcsr_data =
(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
u8 val;
/* Enable USB host & USB-OTG */
val = in_8(&bcsr_data->usb_ctrl);
val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
out_8(&bcsr_data->usb_ctrl, val);
return 0;
}
int usb_board_stop(void)
{
struct board_bcsr *bcsr_data =
(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
u8 val;
/* Disable USB host & USB-OTG */
val = in_8(&bcsr_data->usb_ctrl);
val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
out_8(&bcsr_data->usb_ctrl, val);
return 0;
}
int usb_board_init_fail(void)
{
return usb_board_stop();
}
#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */
#if !defined(CONFIG_ARCHES)
static void canyonlands_sata_init(int board_type)
{
@ -244,11 +288,13 @@ int get_cpu_num(void)
#if !defined(CONFIG_ARCHES)
int checkboard(void)
{
struct board_bcsr *bcsr_data =
(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
char *s = getenv("serial#");
if (pvr_460ex()) {
printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE)
if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
gd->board_type = BOARD_CANYONLANDS_PCIE;
else
gd->board_type = BOARD_CANYONLANDS_SATA;
@ -268,7 +314,7 @@ int checkboard(void)
break;
}
printf(", Rev. %X", in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)));
printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));
if (s != NULL) {
puts(", serial# ");

3
board/amcc/luan/luan.c
View File

@ -223,8 +223,7 @@ int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] )
l2cache_status() ? "ON" : "OFF");
return 0;
default:
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
return 0;

13
board/amcc/makalu/cmd_pll.c
View File

@ -182,14 +182,14 @@ do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char c = '\0';
pll_freq_t pll_freq;
if (argc < 2) {
cmd_usage(cmdtp);
goto ret;
}
for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++)
if (argc < 2)
return cmd_usage(cmdtp);
for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++) {
if (!strcmp(pll_name[pll_freq], argv[1]))
break;
}
switch (pll_freq) {
case PLL_ebc20:
@ -223,8 +223,7 @@ do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
default:
printf("Invalid options\n\n");
cmd_usage(cmdtp);
goto ret;
return cmd_usage(cmdtp);
}
printf("PLL set to %s, "

20
board/amcc/taihu/lcd.c
View File

@ -139,10 +139,9 @@ static int do_lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char * const arg
static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
if (argc < 2) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 2)
return cmd_usage(cmdtp);
lcd_puts(argv[1]);
return 0;
@ -150,10 +149,9 @@ static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv
static int do_lcd_putc (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
if (argc < 2) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 2)
return cmd_usage(cmdtp);
lcd_putc((char)argv[1][0]);
return 0;
@ -165,10 +163,8 @@ static int do_lcd_cur (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[
ulong dir;
char cur_addr;
if (argc < 3) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 3)
return cmd_usage(cmdtp);
count = simple_strtoul(argv[1], NULL, 16);
if (count > 31) {

15
board/amcc/taihu/taihu.c
View File

@ -101,16 +101,12 @@ static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char * const argv[
{
int led_no;
if (argc != 3) {
cmd_usage(cmd_tp);
return -1;
}
if (argc != 3)
return cmd_usage(cmd_tp);
led_no = simple_strtoul(argv[1], NULL, 16);
if (led_no != 1 && led_no != 2) {
cmd_usage(cmd_tp);
return -1;
}
if (led_no != 1 && led_no != 2)
return cmd_usage(cmd_tp);
if (strcmp(argv[2],"off") == 0x0) {
if (led_no == 1)
@ -123,8 +119,7 @@ static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char * const argv[
else
gpio_write_bit(31, 0);
} else {
cmd_usage(cmd_tp);
return -1;
return cmd_usage(cmd_tp);
}
return 0;

20
board/amcc/taishan/lcd.c
View File

@ -166,19 +166,17 @@ static int do_lcd_clear(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv
}
static int do_lcd_puts(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
if (argc < 2) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 2)
return cmd_usage(cmdtp);
lcd_puts(argv[1]);
return 0;
}
static int do_lcd_putc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
if (argc < 2) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 2)
return cmd_usage(cmdtp);
lcd_putc((char)argv[1][0]);
return 0;
}
@ -188,10 +186,8 @@ static int do_lcd_cur(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]
ulong dir;
char cur_addr;
if (argc < 3) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 3)
return cmd_usage(cmdtp);
count = simple_strtoul(argv[1], NULL, 16);
if (count > 31) {

6
board/amcc/yucca/cmd_yucca.c
View File

@ -58,10 +58,8 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
char plbClock[4];
char pcixClock[4];
if (argc < 3) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 3)
return cmd_usage(cmdtp);
if (strcmp(argv[2], "prom0") == 0)
chip = IIC0_BOOTPROM_ADDR;

10
board/atum8548/atum8548.c
View File

@ -292,14 +292,6 @@ void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI1
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCI2
ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
#endif
#ifdef CONFIG_PCIE1
ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
#endif
FT_FSL_PCI_SETUP;
}
#endif

6
board/barco/barco.c
View File

@ -290,12 +290,6 @@ void barcobcd_boot (void)
int barcobcd_boot_image (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#if 0
if (argc > 1) {
cmd_usage(cmdtp);
return 1;
}
#endif
barcobcd_boot ();
return 0;

21
board/digsy_mtc/cmd_mtc.c
View File

@ -75,10 +75,8 @@ static int do_mtc_led(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
int err;
int i;
if (argc < 2) {
cmd_usage(cmdtp);
return -1;
}
if (argc < 2)
return cmd_usage(cmdtp);
memset(&pcmd, 0, sizeof(pcmd));
memset(&prx, 0, sizeof(prx));
@ -149,10 +147,8 @@ static int do_mtc_digout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv
int err;
uchar channel_mask = 0;
if (argc < 3) {
cmd_usage(cmdtp);
return -1;
}
if (argc < 3)
return cmd_usage(cmdtp);
if (strncmp(argv[1], "on", 2) == 0)
channel_mask |= 1;
@ -178,10 +174,8 @@ static int do_mtc_digin(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[
int err;
uchar channel_num = 0;
if (argc < 2) {
cmd_usage(cmdtp);
return -1;
}
if (argc < 2)
return cmd_usage(cmdtp);
channel_num = simple_strtol(argv[1], NULL, 10);
if ((channel_num != 1) && (channel_num != 2)) {
@ -332,8 +326,7 @@ int cmd_mtc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return c->cmd(c, flag, argc, argv);
} else {
/* Unrecognized command */
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
return err;

6
board/esd/common/lcd.c
View File

@ -345,10 +345,8 @@ int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifdef CONFIG_VIDEO_SM501
char *str;
#endif
if (argc != 2) {
cmd_usage(cmdtp);
return 1;
}
if (argc != 2)
return cmd_usage(cmdtp);
addr = simple_strtoul(argv[1], NULL, 16);

4
board/esd/dasa_sim/cmd_dasa_sim.c
View File

@ -221,9 +221,7 @@ int do_pci9054 (cmd_tbl_t * cmdtp, int flag, int argc,
return 0;
}
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
U_BOOT_CMD(

6
board/freescale/common/sys_eeprom.c
View File

@ -351,8 +351,7 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
prog_eeprom();
break;
default:
cmd_usage(cmdtp);
break;
return cmd_usage(cmdtp);
}
return 0;
@ -388,8 +387,7 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
break;
case 'h': /* help */
default:
cmd_usage(cmdtp);
break;
return cmd_usage(cmdtp);
}
return 0;

22
board/freescale/mpc8536ds/mpc8536ds.c
View File

@ -396,26 +396,8 @@ void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI1
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#else
ft_fsl_pci_setup(blob, "pci0", NULL);
#endif
#ifdef CONFIG_PCIE2
ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
#else
ft_fsl_pci_setup(blob, "pci1", NULL);
#endif
#ifdef CONFIG_PCIE2
ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
#else
ft_fsl_pci_setup(blob, "pci2", NULL);
#endif
#ifdef CONFIG_PCIE1
ft_fsl_pci_setup(blob, "pci3", &pcie3_hose);
#else
ft_fsl_pci_setup(blob, "pci3", NULL);
#endif
FT_FSL_PCI_SETUP;
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif

15
board/freescale/mpc8544ds/mpc8544ds.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2007,2009 Freescale Semiconductor, Inc.
* Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -360,19 +360,8 @@ void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
FT_FSL_PCI_SETUP;
#ifdef CONFIG_PCI1
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE2
ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
#ifdef CONFIG_PCIE1
ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
#endif
#ifdef CONFIG_PCIE3
ft_fsl_pci_setup(blob, "pci3", &pcie2_hose);
#endif
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif

9
board/freescale/mpc8548cds/mpc8548cds.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2004, 2007, 200 Freescale Semiconductor, Inc.
* Copyright 2004, 2007, 2009-2010 Freescale Semiconductor, Inc.
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*
@ -388,11 +388,6 @@ int last_stage_init(void)
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_pci_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_PCI1
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE1
ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
FT_FSL_PCI_SETUP;
}
#endif

9
board/freescale/mpc8568mds/mpc8568mds.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2007,2009 Freescale Semiconductor, Inc.
* Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*
@ -426,11 +426,6 @@ void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI1
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE1
ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
FT_FSL_PCI_SETUP;
}
#endif

7
board/freescale/mpc8569mds/mpc8569mds.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2009 Freescale Semiconductor.
* Copyright 2009-2010 Freescale Semiconductor.
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*
@ -635,9 +635,8 @@ void ft_board_setup(void *blob, bd_t *bd)
#endif
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCIE1
ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
FT_FSL_PCI_SETUP;
fdt_board_fixup_esdhc(blob, bd);
fdt_board_fixup_qe_uart(blob, bd);
fdt_board_fixup_qe_usb(blob, bd);

11
board/freescale/mpc8572ds/mpc8572ds.c
View File

@ -345,15 +345,8 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_PCIE3
ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
#endif
#ifdef CONFIG_PCIE2
ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
#endif
#ifdef CONFIG_PCIE1
ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
#endif
FT_FSL_PCI_SETUP;
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif

12
board/freescale/mpc8610hpcd/mpc8610hpcd.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2007,2009 Freescale Semiconductor, Inc.
* Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -309,15 +309,7 @@ ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI1
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE1
ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
#ifdef CONFIG_PCIE2
ft_fsl_pci_setup(blob, "pci2", &pcie2_hose);
#endif
FT_FSL_PCI_SETUP;
}
#endif

6
board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
View File

@ -115,10 +115,8 @@ int mpc8610diu_init_show_bmp(cmd_tbl_t *cmdtp,
{
unsigned int addr;
if (argc < 2) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 2)
return cmd_usage(cmdtp);
if (!strncmp(argv[1],"init",4)) {
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)

18
board/freescale/mpc8641hpcn/law.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
* Copyright 2008,2010 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -32,14 +32,14 @@
*
* 0x0000_0000 0x7fff_ffff DDR 2G
* if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
* 0x8000_0000 0x9fff_ffff PCIE1 MEM 512M
* 0xa000_0000 0xbfff_ffff PCIE2 MEM 512M
* else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
* 0x8000_0000 0x9fff_ffff RapidIO 512M
* endif
* (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT)
* 0xffc0_0000 0xffc0_ffff PCI1 IO 64K
* 0xffc1_0000 0xffc1_ffff PCI2 IO 64K
* 0xffc0_0000 0xffc0_ffff PCIE1 IO 64K
* 0xffc1_0000 0xffc1_ffff PCIE2 IO 64K
* 0xffe0_0000 0xffef_ffff CCSRBAR 1M
* 0xffdf_0000 0xffe0_0000 PIXIS, CF 64K
* 0xef80_0000 0xefff_ffff FLASH (boot bank) 8M
@ -54,10 +54,10 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
#endif
#ifdef CONFIG_PCI
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
#elif defined(CONFIG_RIO)
SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
#endif

61
board/freescale/mpc8641hpcn/mpc8641hpcn.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2006, 2007 Freescale Semiconductor.
* Copyright 2006, 2007, 2010 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -129,21 +129,21 @@ fixed_sdram(void)
#if defined(CONFIG_PCI)
static struct pci_controller pci1_hose;
static struct pci_controller pcie1_hose;
#endif /* CONFIG_PCI */
#ifdef CONFIG_PCI2
static struct pci_controller pci2_hose;
#endif /* CONFIG_PCI2 */
#ifdef CONFIG_PCIE2
static struct pci_controller pcie2_hose;
#endif /* CONFIG_PCIE2 */
int first_free_busno = 0;
void pci_init_board(void)
{
#ifdef CONFIG_PCI1
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
struct pci_controller *hose = &pci1_hose;
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
struct pci_controller *hose = &pcie1_hose;
struct pci_region *r = hose->regions;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
@ -169,16 +169,16 @@ void pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
CONFIG_SYS_PCIE1_MEM_BUS,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BUS,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
CONFIG_SYS_PCIE1_IO_BUS,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
@ -195,8 +195,8 @@ void pci_init_board(void)
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
*/
in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_VIRT
+ CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000)));
in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
+ CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
} else {
puts("PCI-EXPRESS 1: Disabled\n");
@ -204,26 +204,26 @@ void pci_init_board(void)
}
#else
puts("PCI-EXPRESS1: Disabled\n");
#endif /* CONFIG_PCI1 */
#endif /* CONFIG_PCIE1 */
#ifdef CONFIG_PCI2
#ifdef CONFIG_PCIE2
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
struct pci_controller *hose = &pci2_hose;
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
struct pci_controller *hose = &pcie2_hose;
struct pci_region *r = hose->regions;
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI2_MEM_BUS,
CONFIG_SYS_PCI2_MEM_PHYS,
CONFIG_SYS_PCI2_MEM_SIZE,
CONFIG_SYS_PCIE2_MEM_BUS,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCI2_IO_BUS,
CONFIG_SYS_PCI2_IO_PHYS,
CONFIG_SYS_PCI2_IO_SIZE,
CONFIG_SYS_PCIE2_IO_BUS,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
@ -238,7 +238,7 @@ void pci_init_board(void)
}
#else
puts("PCI-EXPRESS 2: Disabled\n");
#endif /* CONFIG_PCI2 */
#endif /* CONFIG_PCIE2 */
}
@ -253,12 +253,7 @@ ft_board_setup(void *blob, bd_t *bd)
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI1
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCI2
ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
#endif
FT_FSL_PCI_SETUP;
/*
* Warn if it looks like the device tree doesn't match u-boot.

18
board/freescale/p1022ds/p1022ds.c
View File

@ -322,23 +322,7 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_PCIE1
ft_fsl_pci_setup(blob, "pci0", &pcie1_hose);
#else
ft_fsl_pci_setup(blob, "pci0", NULL);
#endif
#ifdef CONFIG_PCIE2
ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
#else
ft_fsl_pci_setup(blob, "pci1", NULL);
#endif
#ifdef CONFIG_PCIE3
ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
#else
ft_fsl_pci_setup(blob, "pci2", NULL);
#endif
FT_FSL_PCI_SETUP;
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);

15
board/freescale/p1_p2_rdb/pci.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2009 Freescale Semiconductor, Inc.
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -100,16 +100,5 @@ void pci_init_board(void)
void ft_pci_board_setup(void *blob)
{
/* According to h/w manual, PCIE2 is at lower address(0x9000)
* than PCIE1(0xa000).
* Hence PCIE2 is made to occupy the pci1 position in dts to
* keep the addresses sorted there.
* Generally the case with all FSL SOCs.
*/
#ifdef CONFIG_PCIE2
ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
#endif
#ifdef CONFIG_PCIE1
ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
#endif
FT_FSL_PCI_SETUP;
}

13
board/freescale/p2020ds/p2020ds.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2007-2009 Freescale Semiconductor, Inc.
* Copyright 2007-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -366,15 +366,8 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_PCIE3
ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
#endif
#ifdef CONFIG_PCIE2
ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
#endif
#ifdef CONFIG_PCIE1
ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
#endif
FT_FSL_PCI_SETUP;
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif

44
board/gth/Makefile
View File

@ -1,44 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o ee_access.o pcmcia.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

18
board/gth/README
View File

@ -1,18 +0,0 @@
Written by Thomas.Lange@corelatus.com 010805
To make a system for gth that actually works ;-)
the variable TBASE needs to be set to 0,1 or 2
depending on location where image is supposed to
be started from.
E.g. make TBASE=1
0: Start from RAM, base 0
1: Start from flash_base + 0x10070
2: Start from flash_base + 0x30070
When using 1 or 2, the image is supposed to be launched
from miniboot that boots the first U-Boot image found in
flash.
For miniboot code, description, see www.opensource.se

40
board/gth/config.mk
View File

@ -1,40 +0,0 @@
#
# (C) Copyright 2000, 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
ifeq ($(TBASE),0)
TEXT_BASE = 0
else
ifeq ($(TBASE),1)
TEXT_BASE = 0x80010070
else
ifeq ($(TBASE),2)
TEXT_BASE = 0x80030070
else
## Only to make ordinary make work
TEXT_BASE = 0x90000000
endif
endif
endif
OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data

335
board/gth/ee_access.c
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@ -1,335 +0,0 @@
/* Module for handling DALLAS DS2438, smart battery monitor
Chip can store up to 40 bytes of user data in EEPROM,
perform temp, voltage and current measurements.
Chip also contains a unique serial number.
Always read/write LSb first
For documentaion, see data sheet for DS2438, 2438.pdf
By Thomas.Lange@corelatus.com 001025 */
#include <common.h>
#include <config.h>
#include <mpc8xx.h>
#include <../board/gth/ee_dev.h>
/* We dont have kernel functions */
#define printk printf
#define KERN_DEBUG
#define KERN_ERR
#define EIO 1
static int Debug = 0;
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
/*
* lookup table ripped from DS app note 17, understanding and using
* cyclic redundancy checks...
*/
static u8 crc_lookup[256] = {
0, 94, 188, 226, 97, 63, 221, 131,
194, 156, 126, 32, 163, 253, 31, 65,
157, 195, 33, 127, 252, 162, 64, 30,
95, 1, 227, 189, 62, 96, 130, 220,
35, 125, 159, 193, 66, 28, 254, 160,
225, 191, 93, 3, 128, 222, 60, 98,
190, 224, 2, 92, 223, 129, 99, 61,
124, 34, 192, 158, 29, 67, 161, 255,
70, 24, 250, 164, 39, 121, 155, 197,
132, 218, 56, 102, 229, 187, 89, 7,
219, 133, 103, 57, 186, 228, 6, 88,
25, 71, 165, 251, 120, 38, 196, 154,
101, 59, 217, 135, 4, 90, 184, 230,
167, 249, 27, 69, 198, 152, 122, 36,
248, 166, 68, 26, 153, 199, 37, 123,
58, 100, 134, 216, 91, 5, 231, 185,
140, 210, 48, 110, 237, 179, 81, 15,
78, 16, 242, 172, 47, 113, 147, 205,
17, 79, 173, 243, 112, 46, 204, 146,
211, 141, 111, 49, 178, 236, 14, 80,
175, 241, 19, 77, 206, 144, 114, 44,
109, 51, 209, 143, 12, 82, 176, 238,
50, 108, 142, 208, 83, 13, 239, 177,
240, 174, 76, 18, 145, 207, 45, 115,
202, 148, 118, 40, 171, 245, 23, 73,
8, 86, 180, 234, 105, 55, 213, 139,
87, 9, 235, 181, 54, 104, 138, 212,
149, 203, 41, 119, 244, 170, 72, 22,
233, 183, 85, 11, 136, 214, 52, 106,
43, 117, 151, 201, 74, 20, 246, 168,
116, 42, 200, 150, 21, 75, 169, 247,
182, 232, 10, 84, 215, 137, 107, 53
};
static u8 make_new_crc( u8 Old_crc, u8 New_value ){
/* Compute a new checksum with new byte, using previous checksum as input
See DS app note 17, understanding and using cyclic redundancy checks...
Also see DS2438, page 11 */
return( crc_lookup[Old_crc ^ New_value ]);
}
int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){
/* Check if the checksum for this buffer is correct */
u8 Curr_crc=0;
int i;
u8 *Curr_byte = Buffer;
for(i=0;i<Len;i++){
Curr_crc = make_new_crc( Curr_crc, *Curr_byte);
Curr_byte++;
}
E_DEBUG("Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
if(Curr_crc == Crc){
/* Good */
return(TRUE);
}
printk(KERN_ERR"EE checksum error, Calculated CRC = 0x%x, read = 0x%x\n",
Curr_crc, Crc);
return(FALSE);
}
static void
set_idle(void){
/* Send idle and keep start time
Continous 1 is idle */
WRITE_PORT(1);
}
static int
do_reset(void){
/* Release reset and verify that chip responds with presence pulse */
int Retries = 0;
while(Retries<5){
udelay(RESET_LOW_TIME);
/* Send reset */
WRITE_PORT(0);
udelay(RESET_LOW_TIME);
/* Release reset */
WRITE_PORT(1);
/* Wait for EEPROM to drive output */
udelay(PRESENCE_TIMEOUT);
if(!READ_PORT){
/* Ok, EEPROM is driving a 0 */
E_DEBUG("Presence detected\n");
if(Retries){
E_DEBUG("Retries %d\n",Retries);
}
/* Make sure chip releases pin */
udelay(PRESENCE_LOW_TIME);
return 0;
}
Retries++;
}
printk(KERN_ERR"EEPROM did not respond when releasing reset\n");
/* Make sure chip releases pin */
udelay(PRESENCE_LOW_TIME);
/* Set to idle again */
set_idle();
return(-EIO);
}
static u8
read_byte(void){
/* Read a single byte from EEPROM
Read LSb first */
int i;
int Value;
u8 Result=0;
#ifndef CONFIG_SYS_IMMR
u32 Flags;
#endif
E_DEBUG("Reading byte\n");
for(i=0;i<8;i++){
/* Small delay between pulses */
udelay(1);
#ifndef CONFIG_SYS_IMMR
/* Disable irq */
save_flags(Flags);
cli();
#endif
/* Pull down pin short time to start read
See page 26 in data sheet */
WRITE_PORT(0);
udelay(READ_LOW);
WRITE_PORT(1);
/* Wait for chip to drive pin */
udelay(READ_TIMEOUT);
Value = READ_PORT;
if(Value)
Value=1;
#ifndef CONFIG_SYS_IMMR
/* Enable irq */
restore_flags(Flags);
#endif
/* Wait for chip to release pin */
udelay(TOTAL_READ_LOW-READ_TIMEOUT);
/* LSb first */
Result|=Value<<i;
}
E_DEBUG("Read byte 0x%x\n",Result);
return(Result);
}
static void
write_byte(u8 Byte){
/* Write a single byte to EEPROM
Write LSb first */
int i;
int Value;
#ifndef CONFIG_SYS_IMMR
u32 Flags;
#endif
E_DEBUG("Writing byte 0x%x\n",Byte);
for(i=0;i<8;i++){
/* Small delay between pulses */
udelay(1);
Value = Byte&1;
#ifndef CONFIG_SYS_IMMR
/* Disable irq */
save_flags(Flags);
cli();
#endif
/* Pull down pin short time for a 1, long time for a 0
See page 26 in data sheet */
WRITE_PORT(0);
if(Value){
/* Write a 1 */
udelay(WRITE_1_LOW);
}
else{
/* Write a 0 */
udelay(WRITE_0_LOW);
}
WRITE_PORT(1);
#ifndef CONFIG_SYS_IMMR
/* Enable irq */
restore_flags(Flags);
#endif
if(Value)
/* Wait for chip to read the 1 */
udelay(TOTAL_WRITE_LOW-WRITE_1_LOW);
Byte>>=1;
}
}
int ee_do_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ){
/* Execute this command string, including
giving reset and setting to idle after command
if Rx_len is set, we read out data from EEPROM */
int i;
E_DEBUG("Command, Tx_len %d, Rx_len %d\n", Tx_len, Rx_len );
if(do_reset()){
/* Failed! */
return(-EIO);
}
if(Send_skip)
/* Always send SKIP_ROM first to tell chip we are sending a command,
except when we read out rom data for chip */
write_byte(SKIP_ROM);
/* Always have Tx data */
for(i=0;i<Tx_len;i++){
write_byte(Tx[i]);
}
if(Rx_len){
for(i=0;i<Rx_len;i++){
Rx[i]=read_byte();
}
}
set_idle();
E_DEBUG("Command done\n");
return(0);
}
int ee_init_data(void){
int i;
u8 Tx[10];
int tmp;
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
while(0){
tmp = 1-tmp;
if(tmp)
immap->im_ioport.iop_padat &= ~PA_FRONT_LED;
else
immap->im_ioport.iop_padat |= PA_FRONT_LED;
udelay(1);
}
/* Set port to open drain to be able to read data from
port without setting it to input */
PORT_B_PAR &= ~PB_EEPROM;
PORT_B_ODR |= PB_EEPROM;
SET_PORT_B_OUTPUT(PB_EEPROM);
/* Set idle mode */
set_idle();
/* Copy all User EEPROM data to scratchpad */
for(i=0;i<USER_PAGES;i++){
Tx[0]=RECALL_MEMORY;
Tx[1]=EE_USER_PAGE_0+i;
if(ee_do_command(Tx,2,NULL,0,TRUE)) return(-EIO);
}
/* Make sure chip doesnt store measurements in NVRAM */
Tx[0]=WRITE_SCRATCHPAD;
Tx[1]=0; /* Page */
Tx[2]=9;
if(ee_do_command(Tx,3,NULL,0,TRUE)) return(-EIO);
Tx[0]=COPY_SCRATCHPAD;
if(ee_do_command(Tx,2,NULL,0,TRUE)) return(-EIO);
/* FIXME check status bit instead
Could take 10 ms to store in EEPROM */
for(i=0;i<10;i++){
udelay(1000);
}
return(0);
}

16
board/gth/ee_access.h
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@ -1,16 +0,0 @@
/* By Thomas.Lange@Corelatus.com 001025
Definitions for EEPROM/VOLT METER DS2438 */
#ifndef INCeeaccessh
#define INCeeaccessh
int ee_do_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip );
int ee_init_data(void);
int ee_crc_ok( u8 *Buffer, int Len, u8 Crc );
#ifndef TRUE
#define TRUE 1
#endif
#endif /* INCeeaccessh */

85
board/gth/ee_dev.h
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/* By Thomas.Lange@Corelatus.com 001025
$Revision: 1.6 $
Definitions for EEPROM/VOLT METER DS2438
Copyright (C) 2000-2001 Corelatus AB */
#ifndef INCeedevh
#define INCeedevh
#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args)
#define PORT_B_PAR ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar
#define PORT_B_ODR ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr
#define PORT_B_DIR ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir
#define PORT_B_DAT ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat
#define SET_PORT_B_INPUT(Mask) PORT_B_DIR &= ~(Mask)
#define SET_PORT_B_OUTPUT(Mask) PORT_B_DIR |= Mask
#define WRITE_PORT_B(Mask,Value) { \
if (Value) PORT_B_DAT |= Mask; \
else PORT_B_DAT &= ~(Mask); \
}
#define WRITE_PORT(Value) WRITE_PORT_B(PB_EEPROM,Value)
#define READ_PORT (PORT_B_DAT&PB_EEPROM)
/* 64 bytes chip */
#define EE_CHIP_SIZE 64
/* We use this resistor for measuring the current drain on 3.3V */
#define CURRENT_RESISTOR 0.022
/* microsecs
Pull line down at least this long for reset pulse */
#define RESET_LOW_TIME 490
/* Read presence pulse after we release reset pulse */
#define PRESENCE_TIMEOUT 100
#define PRESENCE_LOW_TIME 200
#define WRITE_0_LOW 80
#define WRITE_1_LOW 2
#define TOTAL_WRITE_LOW 80
#define READ_LOW 2
#define READ_TIMEOUT 10
#define TOTAL_READ_LOW 80
/*** Rom function commands ***/
#define READ_ROM 0x33
#define MATCH_ROM 0x55
#define SKIP_ROM 0xCC
#define SEARCH_ROM 0xF0
/*** Memory_command_function ***/
#define WRITE_SCRATCHPAD 0x4E
#define READ_SCRATCHPAD 0xBE
#define COPY_SCRATCHPAD 0x48
#define RECALL_MEMORY 0xB8
#define CONVERT_TEMP 0x44
#define CONVERT_VOLTAGE 0xB4
/* Chip is divided in 8 pages, 8 bytes each */
#define EE_PAGE_SIZE 8
/* All chip data we want are in page 0 */
/* Bytes in page 0 */
#define EE_P0_STATUS 0
#define EE_P0_TEMP_LSB 1
#define EE_P0_TEMP_MSB 2
#define EE_P0_VOLT_LSB 3
#define EE_P0_VOLT_MSB 4
#define EE_P0_CURRENT_LSB 5
#define EE_P0_CURRENT_MSB 6
/* 40 byte user data is located at page 3-7 */
#define EE_USER_PAGE_0 3
#define USER_PAGES 5
#endif /* INCeedevh */

649
board/gth/flash.c
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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc8xx.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
static void flash_get_offsets (ulong base, flash_info_t *info);
/*-----------------------------------------------------------------------
* Protection Flags:
*/
#define FLAG_PROTECT_SET 0x01
#define FLAG_PROTECT_CLEAR 0x02
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
unsigned long size_b0, size_b1;
int i;
/*printf("faking");*/
return(0x1fffff);
/* Init: no FLASHes known */
for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
{
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN)
{
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
}
#if 0
if (FLASH_BASE1_PRELIM != 0x0) {
size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
if (size_b1 > size_b0) {
printf ("## ERROR: Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
size_b1, size_b1<<20,size_b0, size_b0<<20);
flash_info[0].flash_id = FLASH_UNKNOWN;
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[0].sector_count = -1;
flash_info[1].sector_count = -1;
flash_info[0].size = 0;
flash_info[1].size = 0;
return (0);
}
} else {
#endif
size_b1 = 0;
/* Remap FLASH according to real size */
memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
/* Re-do sizing to get full correct info */
size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
if (size_b1)
{
/* memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; */
/* Re-do sizing to get full correct info */
size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
&flash_info[1]);
flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
&flash_info[1]);
#endif
}
else
{
/* memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
FIXME memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; */
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[1].sector_count = -1;
}
flash_info[0].size = size_b0;
flash_info[1].size = size_b1;
return (size_b0 + size_b1);
}
static void flash_get_offsets (ulong base, flash_info_t *info)
{
int i;
/* set up sector start adress table */
if (info->flash_id & FLASH_BTYPE)
{
/* set sector offsets for bottom boot block type */
for (i = 0; i < info->sector_count; i++)
{
info->start[i] = base + (i * 0x00040000);
}
}
else
{
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
for (; i >= 0; i--)
{
info->start[i] = base + i * 0x00040000;
}
}
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD: printf ("AMD "); break;
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
#if 0
case FLASH_AM040B:
printf ("AM29F040B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM040T:
printf ("AM29F040T (4 Mbit, top boot sect)\n");
break;
#endif
case FLASH_AM400B:
printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400T:
printf ("AM29LV400T (4 Mbit, top boot sector)\n");
break;
case FLASH_AM800B:
printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
break;
case FLASH_AM800T:
printf ("AM29LV800T (8 Mbit, top boot sector)\n");
break;
case FLASH_AM160B:
printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
break;
case FLASH_AM160T:
printf ("AM29LV160T (16 Mbit, top boot sector)\n");
break;
case FLASH_AM320B:
printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
break;
case FLASH_AM320T:
printf ("AM29LV320T (32 Mbit, top boot sector)\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20,
info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i)
{
if ((i % 5) == 0)
{
printf ("\n ");
}
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
return;
}
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
{
short i;
#if 0
ulong base = (ulong)addr;
#endif
ulong value;
/* Write auto select command: read Manufacturer ID */
#if 0
addr[0x0555] = 0x00AA00AA;
addr[0x02AA] = 0x00550055;
addr[0x0555] = 0x00900090;
#else
addr[0x0555] = 0xAAAAAAAA;
addr[0x02AA] = 0x55555555;
addr[0x0555] = 0x90909090;
#endif
value = addr[0];
switch (value)
{
case AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
break;
}
value = addr[1]; /* device ID */
switch (value)
{
#if 0
case AMD_ID_F040B:
info->flash_id += FLASH_AM040B;
info->sector_count = 8;
info->size = 0x00200000;
break; /* => 2 MB */
#endif
case AMD_ID_LV400T:
info->flash_id += FLASH_AM400T;
info->sector_count = 11;
info->size = 0x00100000;
break; /* => 1 MB */
case AMD_ID_LV400B:
info->flash_id += FLASH_AM400B;
info->sector_count = 11;
info->size = 0x00100000;
break; /* => 1 MB */
case AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00200000;
break; /* => 2 MB */
case AMD_ID_LV800B:
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00200000;
break; /* => 2 MB */
case AMD_ID_LV160T:
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00400000;
break; /* => 4 MB */
case AMD_ID_LV160B:
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00400000;
break; /* => 4 MB */
#if 0 /* enable when device IDs are available */
case AMD_ID_LV320T:
info->flash_id += FLASH_AM320T;
info->sector_count = 67;
info->size = 0x00800000;
break; /* => 8 MB */
case AMD_ID_LV320B:
info->flash_id += FLASH_AM320B;
info->sector_count = 67;
info->size = 0x00800000;
break; /* => 8 MB */
#endif
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
#if 0
/* set up sector start adress table */
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00008000;
info->start[2] = base + 0x0000C000;
info->start[3] = base + 0x00010000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00020000) - 0x00060000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00008000;
info->start[i--] = base + info->size - 0x0000C000;
info->start[i--] = base + info->size - 0x00010000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00020000;
}
}
#else
flash_get_offsets ((ulong)addr, &flash_info[0]);
#endif
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++)
{
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr = (volatile unsigned long *)(info->start[i]);
info->protect[i] = addr[2] & 1;
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN)
{
addr = (volatile unsigned long *)info->start[0];
#if 0
*addr = 0x00F000F0; /* reset bank */
#else
*addr = 0xF0F0F0F0; /* reset bank */
#endif
}
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
vu_long *addr = (vu_long*)(info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if ((info->flash_id == FLASH_UNKNOWN) ||
(info->flash_id > FLASH_AMD_COMP)) {
printf ("Can't erase unknown flash type - aborted\n");
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
#if 0
addr[0x0555] = 0x00AA00AA;
addr[0x02AA] = 0x00550055;
addr[0x0555] = 0x00800080;
addr[0x0555] = 0x00AA00AA;
addr[0x02AA] = 0x00550055;
#else
addr[0x0555] = 0xAAAAAAAA;
addr[0x02AA] = 0x55555555;
addr[0x0555] = 0x80808080;
addr[0x0555] = 0xAAAAAAAA;
addr[0x02AA] = 0x55555555;
#endif
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (vu_long*)(info->start[sect]);
#if 0
addr[0] = 0x00300030;
#else
addr[0] = 0x30303030;
#endif
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer (0);
last = start;
addr = (vu_long*)(info->start[l_sect]);
#if 0
while ((addr[0] & 0x00800080) != 0x00800080)
#else
while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF)
#endif
{
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
DONE:
/* reset to read mode */
addr = (volatile unsigned long *)info->start[0];
#if 0
addr[0] = 0x00F000F0; /* reset bank */
#else
addr[0] = 0xF0F0F0F0; /* reset bank */
#endif
printf (" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
for (; i<4 && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i=0; i<4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
return (write_word(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
vu_long *addr = (vu_long*)(info->start[0]);
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*((vu_long *)dest) & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
#if 0
addr[0x0555] = 0x00AA00AA;
addr[0x02AA] = 0x00550055;
addr[0x0555] = 0x00A000A0;
#else
addr[0x0555] = 0xAAAAAAAA;
addr[0x02AA] = 0x55555555;
addr[0x0555] = 0xA0A0A0A0;
#endif
*((vu_long *)dest) = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer (0);
#if 0
while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080))
#else
while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080))
#endif
{
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return (1);
}
}
return (0);
}
/*-----------------------------------------------------------------------
*/

595
board/gth/gth.c
View File

@ -1,595 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Adapted from FADS and other board config files to GTH by thomas@corelatus.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <config.h>
#include <watchdog.h>
#include <mpc8xx.h>
#include "ee_access.h"
#include "ee_dev.h"
#ifdef CONFIG_BDM
#undef printf
#define printf(a,...) /* nothing */
#endif
int checkboard (void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
int Id = 0;
int Rev = 0;
u32 Pbdat;
puts ("Board: ");
/* Turn on leds and setup for reading rev and id */
#define PB_OUTS (PB_BLUE_LED|PB_ID_GND)
#define PB_INS (PB_ID_0|PB_ID_1|PB_ID_2|PB_ID_3|PB_REV_1|PB_REV_0)
immap->im_cpm.cp_pbpar &= ~(PB_OUTS | PB_INS);
immap->im_cpm.cp_pbdir &= ~PB_INS;
immap->im_cpm.cp_pbdir |= PB_OUTS;
immap->im_cpm.cp_pbodr |= PB_OUTS;
immap->im_cpm.cp_pbdat &= ~PB_OUTS;
/* Hold 100 Mbit in reset until fpga is loaded */
immap->im_ioport.iop_pcpar &= ~PC_ENET100_RESET;
immap->im_ioport.iop_pcdir |= PC_ENET100_RESET;
immap->im_ioport.iop_pcso &= ~PC_ENET100_RESET;
immap->im_ioport.iop_pcdat &= ~PC_ENET100_RESET;
/* Turn on front led to show that we are alive */
immap->im_ioport.iop_papar &= ~PA_FRONT_LED;
immap->im_ioport.iop_padir |= PA_FRONT_LED;
immap->im_ioport.iop_paodr |= PA_FRONT_LED;
immap->im_ioport.iop_padat &= ~PA_FRONT_LED;
Pbdat = immap->im_cpm.cp_pbdat;
if (!(Pbdat & PB_ID_0))
Id += 1;
if (!(Pbdat & PB_ID_1))
Id += 2;
if (!(Pbdat & PB_ID_2))
Id += 4;
if (!(Pbdat & PB_ID_3))
Id += 8;
if (Pbdat & PB_REV_0)
Rev += 1;
if (Pbdat & PB_REV_1)
Rev += 2;
/* Turn ID off since we dont need it anymore */
immap->im_cpm.cp_pbdat |= PB_ID_GND;
printf ("GTH board, rev %d, id=0x%01x\n", Rev, Id);
return 0;
}
#define _NOT_USED_ 0xffffffff
const uint sdram_table[] = {
/* Single read, offset 0 */
0x0f3dfc04, 0x0eefbc04, 0x01bf7c04, 0x0feafc00,
0x1fb5fc45, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* Burst read, Offset 0x8, 4 reads */
0x0f3dfc04, 0x0eefbc04, 0x00bf7c04, 0x00ffec00,
0x00fffc00, 0x01eafc00, 0x1fb5fc00, 0xfffffc45,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* Not used part of burst read is used for MRS, Offset 0x14 */
0xefeabc34, 0x1fb57c34, 0xfffffc05, _NOT_USED_,
/* _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, */
/* Single write, Offset 0x18 */
0x0f3dfc04, 0x0eebbc00, 0x01a27c04, 0x1fb5fc45,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* Burst write, Offset 0x20. 4 writes */
0x0f3dfc04, 0x0eebbc00, 0x00b77c00, 0x00fffc00,
0x00fffc00, 0x01eafc04, 0x1fb5fc45, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* Not used part of burst write is used for precharge, Offset 0x2C */
0x0ff5fc04, 0xfffffc05, _NOT_USED_, _NOT_USED_,
/* _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, */
/* Period timer service. Offset 0x30. Refresh. Wait at least 70 ns after refresh command */
0x1ffd7c04, 0xfffffc04, 0xfffffc04, 0xfffffc05,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* Exception, Offset 0x3C */
0xfffffc04, 0xfffffc05, _NOT_USED_, _NOT_USED_
};
const uint fpga_table[] = {
/* Single read, offset 0 */
0x0cffec04, 0x00ffec04, 0x00ffec04, 0x00ffec04,
0x00fffc04, 0x00fffc00, 0x00ffec04, 0xffffec05,
/* Burst read, Offset 0x8 */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* Single write, Offset 0x18 */
0x0cffec04, 0x00ffec04, 0x00ffec04, 0x00ffec04,
0x00fffc04, 0x00fffc00, 0x00ffec04, 0xffffec05,
/* Burst write, Offset 0x20. */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* Period timer service. Offset 0x30. */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* Exception, Offset 0x3C */
0xfffffc04, 0xfffffc05, _NOT_USED_, _NOT_USED_
};
int _initsdram (uint base, uint * noMbytes)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *mc = &immap->im_memctl;
volatile u32 *memptr;
mc->memc_mptpr = MPTPR_PTP_DIV16; /* (16-17) */
/* SDRAM in UPMA
GPL_0 is connected instead of A19 to SDRAM.
According to table 16-17, AMx should be 001, i.e. type 1
and GPL_0 should hold address A10 when multiplexing */
mc->memc_mamr = (0x2E << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_AMA_TYPE_1 | MAMR_G0CLA_A10 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X; /* (16-13) */
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
/* Perform init of sdram ( Datasheet Page 9 )
Precharge */
mc->memc_mcr = 0x8000212C; /* run upm a at 0x2C (16-15) */
/* Run 2 refresh cycles */
mc->memc_mcr = 0x80002130; /* run upm a at 0x30 (16-15) */
mc->memc_mcr = 0x80002130; /* run upm a at 0x30 (16-15) */
/* Set Mode register */
mc->memc_mar = 0x00000088; /* set mode register (address) to 0x022 (16-17) */
/* Lower 2 bits are not connected to chip */
mc->memc_mcr = 0x80002114; /* run upm a at 0x14 (16-15) */
/* CS1, base 0x0000000 - 64 Mbyte, use UPM A */
mc->memc_or1 = 0xfc000000 | OR_CSNT_SAM;
mc->memc_br1 = BR_MS_UPMA | BR_V; /* SDRAM base always 0 */
/* Test if we really have 64 MB SDRAM */
memptr = (u32 *) 0;
*memptr = 0;
memptr = (u32 *) 0x2000000; /* First u32 in upper 32 MB */
*memptr = 0x12345678;
memptr = (u32 *) 0;
if (*memptr == 0x12345678) {
/* Wrapped, only have 32 MB */
mc->memc_or1 = 0xfe000000 | OR_CSNT_SAM;
*noMbytes = 32;
} else {
/* 64 MB */
*noMbytes = 64;
}
/* Setup FPGA in UPMB */
upmconfig (UPMB, (uint *) fpga_table,
sizeof (fpga_table) / sizeof (uint));
/* Enable UPWAITB */
mc->memc_mbmr = MBMR_GPL_B4DIS; /* (16-13) */
/* CS2, base FPGA_2_BASE - 4 MByte, use UPM B 32 Bit */
mc->memc_or2 = 0xffc00000 | OR_BI;
mc->memc_br2 = FPGA_2_BASE | BR_MS_UPMB | BR_V;
/* CS3, base FPGA_3_BASE - 4 MByte, use UPM B 16 bit */
mc->memc_or3 = 0xffc00000 | OR_BI;
mc->memc_br3 = FPGA_3_BASE | BR_MS_UPMB | BR_V | BR_PS_16;
return 0;
}
/* ------------------------------------------------------------------------- */
void _sdramdisable (void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
memctl->memc_br1 = 0x00000000;
/* maybe we should turn off upmb here or something */
}
/* ------------------------------------------------------------------------- */
int initsdram (uint base, uint * noMbytes)
{
*noMbytes = 32;
#ifdef CONFIG_START_IN_RAM
/* SDRAM is already setup. Dont touch it */
return 0;
#else
if (!_initsdram (base, noMbytes)) {
return 0;
} else {
_sdramdisable ();
return -1;
}
#endif
}
phys_size_t initdram (int board_type)
{
u32 *i;
u32 j;
u32 k;
/* GTH only have SDRAM */
uint sdramsz;
if (!initsdram (0x00000000, &sdramsz)) {
printf ("(%u MB SDRAM) ", sdramsz);
} else {
/********************************
*SDRAM ERROR, HALT PROCESSOR
*********************************/
printf ("SDRAM ERROR\n");
while (1);
}
#ifndef CONFIG_START_IN_RAM
#define U32_S ((sdramsz<<18)-1)
#if 1
/* Do a simple memory test */
for (i = (u32 *) 0, j = 0; (u32) i < U32_S; i += 2, j += 2) {
*i = j + (j << 17);
*(i + 1) = ~(j + (j << 18));
}
WATCHDOG_RESET ();
printf (".");
for (i = (u32 *) 0, j = 0; (u32) i < U32_S; i += 2, j += 2) {
k = *i;
if (k != (j + (j << 17))) {
printf ("Mem test error, i=0x%x, 0x%x\n, 0x%x", (u32) i, j, k);
while (1);
}
k = *(i + 1);
if (k != ~(j + (j << 18))) {
printf ("Mem test error(+1), i=0x%x, 0x%x\n, 0x%x",
(u32) i + 1, j, k);
while (1);
}
}
#endif
WATCHDOG_RESET ();
/* Clear memory */
for (i = (u32 *) 0; (u32) i < U32_S; i++) {
*i = 0;
}
#endif /* !start in ram */
WATCHDOG_RESET ();
return (sdramsz << 20);
}
#define POWER_OFFSET 0xF0000
#define SW_WATCHDOG_REASON 13
#define BOOTDATA_OFFSET 0xF8000
#define MAX_ATTEMPTS 5
#define FAILSAFE_BOOT 1
#define SYSTEM_BOOT 2
#define WRITE_FLASH16(a, d) \
do \
{ \
*((volatile u16 *) (a)) = (d);\
} while(0)
static void write_bootdata (volatile u16 * addr, u8 System, u8 Count)
{
u16 data;
volatile u16 *flash = (u16 *) (CONFIG_SYS_FLASH_BASE);
if ((System != FAILSAFE_BOOT) & (System != SYSTEM_BOOT)) {
printf ("Invalid system data %u, setting failsafe\n", System);
System = FAILSAFE_BOOT;
}
if ((Count < 1) | (Count > MAX_ATTEMPTS)) {
printf ("Invalid boot count %u, setting 1\n", Count);
Count = 1;
}
if (System == FAILSAFE_BOOT) {
printf ("Setting failsafe boot in flash\n");
} else {
printf ("Setting system boot in flash\n");
}
printf ("Boot attempt %d\n", Count);
data = (System << 8) | Count;
/* AMD 16 bit */
WRITE_FLASH16 (&flash[0x555], 0xAAAA);
WRITE_FLASH16 (&flash[0x2AA], 0x5555);
WRITE_FLASH16 (&flash[0x555], 0xA0A0);
WRITE_FLASH16 (addr, data);
}
static void maybe_update_restart_reason (volatile u32 * addr32)
{
/* Update addr if sw wd restart */
volatile u16 *flash = (u16 *) (CONFIG_SYS_FLASH_BASE);
volatile u16 *addr_16 = (u16 *) addr32;
u32 rsr;
/* Dont reset register now */
rsr = ((volatile immap_t *) CONFIG_SYS_IMMR)->im_clkrst.car_rsr;
rsr >>= 24;
if (rsr & 0x10) {
/* Was really a sw wd restart, update reason */
printf ("Last restart by software watchdog\n");
/* AMD 16 bit */
WRITE_FLASH16 (&flash[0x555], 0xAAAA);
WRITE_FLASH16 (&flash[0x2AA], 0x5555);
WRITE_FLASH16 (&flash[0x555], 0xA0A0);
WRITE_FLASH16 (addr_16, 0);
udelay (1000);
WATCHDOG_RESET ();
/* AMD 16 bit */
WRITE_FLASH16 (&flash[0x555], 0xAAAA);
WRITE_FLASH16 (&flash[0x2AA], 0x5555);
WRITE_FLASH16 (&flash[0x555], 0xA0A0);
WRITE_FLASH16 (addr_16 + 1, SW_WATCHDOG_REASON);
}
}
static void check_restart_reason (void)
{
/* Update restart reason if sw watchdog was
triggered */
int i;
volatile u32 *raddr;
raddr = (u32 *) (CONFIG_SYS_FLASH_BASE + POWER_OFFSET);
if (*raddr == 0xFFFFFFFF) {
/* Nothing written */
maybe_update_restart_reason (raddr);
} else {
/* Search for latest written reason */
i = 0;
while ((*(raddr + 2) != 0xFFFFFFFF) & (i < 2000)) {
raddr += 2;
i++;
}
if (i >= 2000) {
/* Whoa, dont write any more */
printf ("*** No free restart reason found ***\n");
} else {
/* Check if written */
if (*raddr == 0) {
/* Erased by kernel, no new reason written */
maybe_update_restart_reason (raddr + 2);
}
}
}
}
static void check_boot_tries (void)
{
/* Count the number of boot attemps
switch system if too many */
int i;
volatile u16 *addr;
volatile u16 data;
int failsafe = 1;
u8 system;
u8 count;
addr = (u16 *) (CONFIG_SYS_FLASH_BASE + BOOTDATA_OFFSET);
if (*addr == 0xFFFF) {
printf ("*** No bootdata exists. ***\n");
write_bootdata (addr, FAILSAFE_BOOT, 1);
} else {
/* Search for latest written bootdata */
i = 0;
while ((*(addr + 1) != 0xFFFF) & (i < 8000)) {
addr++;
i++;
}
if (i >= 8000) {
/* Whoa, dont write any more */
printf ("*** No bootdata found. Not updating flash***\n");
} else {
/* See how many times we have tried to boot real system */
data = *addr;
system = data >> 8;
count = data & 0xFF;
if ((system != SYSTEM_BOOT) & (system != FAILSAFE_BOOT)) {
printf ("*** Wrong system %d\n", system);
system = FAILSAFE_BOOT;
count = 1;
} else {
switch (count) {
case 0:
case 1:
case 2:
case 3:
case 4:
/* Try same system again if needed */
count++;
break;
case 5:
/* Switch system and reset tries */
count = 1;
system = 3 - system;
printf ("***Too many boot attempts, switching system***\n");
break;
default:
/* Switch system, start over and hope it works */
printf ("***Unexpected data on addr 0x%x, %u***\n",
(u32) addr, data);
count = 1;
system = 3 - system;
}
}
write_bootdata (addr + 1, system, count);
if (system == SYSTEM_BOOT) {
failsafe = 0;
}
}
}
if (failsafe) {
printf ("Booting failsafe system\n");
setenv ("bootargs", "panic=1 root=/dev/hda7");
setenv ("bootcmd", "disk 100000 0:5;bootm 100000");
} else {
printf ("Using normal system\n");
setenv ("bootargs", "panic=1 root=/dev/hda4");
setenv ("bootcmd", "disk 100000 0:2;bootm 100000");
}
}
int misc_init_r (void)
{
u8 Rx[80];
u8 Tx[5];
int page;
int read = 0;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
/* Kill fpga */
immap->im_ioport.iop_papar &= ~(PA_FL_CONFIG | PA_FL_CE);
immap->im_ioport.iop_padir |= (PA_FL_CONFIG | PA_FL_CE);
immap->im_ioport.iop_paodr &= ~(PA_FL_CONFIG | PA_FL_CE);
/* Enable fpga, active low */
immap->im_ioport.iop_padat &= ~PA_FL_CE;
/* Start configuration */
immap->im_ioport.iop_padat &= ~PA_FL_CONFIG;
udelay (2);
immap->im_ioport.iop_padat |= (PA_FL_CONFIG | PA_FL_CE);
/* Check if we need to boot failsafe system */
check_boot_tries ();
/* Check if we need to update restart reason */
check_restart_reason ();
if (ee_init_data ()) {
printf ("EEPROM init failed\n");
return (0);
}
/* Read the pages where ethernet address is stored */
for (page = EE_USER_PAGE_0; page <= EE_USER_PAGE_0 + 2; page++) {
/* Copy from nvram to scratchpad */
Tx[0] = RECALL_MEMORY;
Tx[1] = page;
if (ee_do_command (Tx, 2, NULL, 0, TRUE)) {
printf ("EE user page %d recall failed\n", page);
return (0);
}
Tx[0] = READ_SCRATCHPAD;
if (ee_do_command (Tx, 2, Rx + read, 9, TRUE)) {
printf ("EE user page %d read failed\n", page);
return (0);
}
/* Crc in 9:th byte */
if (!ee_crc_ok (Rx + read, 8, *(Rx + read + 8))) {
printf ("EE read failed, page %d. CRC error\n", page);
return (0);
}
read += 8;
}
/* Add eos after eth addr */
Rx[17] = 0;
printf ("Ethernet addr read from eeprom: %s\n\n", Rx);
if ((Rx[2] != ':') |
(Rx[5] != ':') |
(Rx[8] != ':') | (Rx[11] != ':') | (Rx[14] != ':')) {
printf ("*** ethernet addr invalid, using default ***\n");
} else {
setenv ("ethaddr", (char *)Rx);
}
return (0);
}

93
board/gth/pcmcia.c
View File

@ -1,93 +0,0 @@
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
#undef CONFIG_PCMCIA
#if defined(CONFIG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#ifdef CONFIG_PCMCIA
#define PCMCIA_BOARD_MSG "GTH COMPACT FLASH"
int pcmcia_voltage_set (int slot, int vcc, int vpp)
{ /* Do nothing */
return 0;
}
int pcmcia_hardware_enable (int slot)
{
volatile immap_t *immap;
volatile cpm8xx_t *cp;
volatile pcmconf8xx_t *pcmp;
volatile sysconf8xx_t *sysp;
uint reg, mask;
debug ("hardware_enable: GTH Slot %c\n", 'A' + slot);
immap = (immap_t *) CONFIG_SYS_IMMR;
sysp = (sysconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_siu_conf));
pcmp = (pcmconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_pcmcia));
cp = (cpm8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_cpm));
/* clear interrupt state, and disable interrupts */
pcmp->pcmc_pscr = PCMCIA_MASK (_slot_);
pcmp->pcmc_per &= ~PCMCIA_MASK (_slot_);
/*
* Disable interrupts, DMA, and PCMCIA buffers
* (isolate the interface) and assert RESET signal
*/
debug ("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX (_slot_) = reg;
udelay (500);
/*
* Make sure there is a card in the slot,
* then configure the interface.
*/
udelay (10000);
debug ("[%d] %s: PIPR(%p)=0x%x\n",
__LINE__, __FUNCTION__,
&(pcmp->pcmc_pipr), pcmp->pcmc_pipr);
if (pcmp->pcmc_pipr & 0x98000000) {
printf (" No Card found\n");
return (1);
}
mask = PCMCIA_VS1 (slot) | PCMCIA_VS2 (slot);
reg = pcmp->pcmc_pipr;
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
reg,
(reg & PCMCIA_VS1 (slot)) ? "n" : "ff",
(reg & PCMCIA_VS2 (slot)) ? "n" : "ff");
debug ("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX (_slot_);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
PCMCIA_PGCRX (_slot_) = reg;
udelay (250000); /* some cards need >150 ms to come up :-( */
debug ("# hardware_enable done\n");
return 0;
}
#if defined(CONFIG_CMD_PCMCIA)
int pcmcia_hardware_disable(int slot)
{
return 0; /* No hardware to disable */
}
#endif
#endif /* CONFIG_PCMCIA */

127
board/gth/u-boot.lds
View File

@ -1,127 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
arch/powerpc/cpu/mpc8xx/start.o(.text)
*(.text)
common/env_embedded.o(.text)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
}

6
board/hymod/bsp.c
View File

@ -272,8 +272,7 @@ do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
break;
}
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
U_BOOT_CMD(
fpga, 6, 1, do_fpga,
@ -324,8 +323,7 @@ do_eecl (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
/* fall through ... */
default:
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
memset (data, 0, HYMOD_EEPROM_SIZE);

18
board/inka4x0/inkadiag.c
View File

@ -168,8 +168,7 @@ static int do_inkadiag_io(cmd_tbl_t *cmdtp, int flag, int argc,
printf("exit code: 0x%X\n", val);
return 0;
default:
cmd_usage(cmdtp);
break;
return cmd_usage(cmdtp);
}
return -1;
@ -244,10 +243,8 @@ static int do_inkadiag_serial(cmd_tbl_t *cmdtp, int flag, int argc,
int combrd, baudrate, i, j, len;
int address;
if (argc < 5) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 5)
return cmd_usage(cmdtp);
argc--;
argv++;
@ -394,10 +391,8 @@ static int do_inkadiag_buzzer(cmd_tbl_t *cmdtp, int flag, int argc,
unsigned int period, freq;
int prev, i;
if (argc != 3) {
cmd_usage(cmdtp);
return 1;
}
if (argc != 3)
return cmd_usage(cmdtp);
argc--;
argv++;
@ -474,8 +469,7 @@ static int do_inkadiag(cmd_tbl_t *cmdtp, int flag, int argc,
return c->cmd(c, flag, argc, argv);
} else {
/* Unrecognized command */
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
}

9
board/keymile/km_arm/km_arm.c
View File

@ -186,10 +186,8 @@ int board_init(void)
int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u32 tmp;
if (argc < 2) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 2)
return cmd_usage(cmdtp);
if ((strcmp(argv[1], "off") == 0)) {
printf("SPI FLASH disabled, NAND enabled\n");
@ -214,8 +212,7 @@ int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
tmp = readl(KW_GPIO0_BASE);
writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE);
} else {
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
return 0;

6
board/lwmon/lwmon.c
View File

@ -845,8 +845,7 @@ int do_pic (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
default:
break;
}
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
U_BOOT_CMD(
pic, 4, 1, do_pic,
@ -975,8 +974,7 @@ int do_lsb (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
default:
break;
}
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
U_BOOT_CMD(

17
board/lwmon5/lwmon5.c
View File

@ -306,20 +306,15 @@ void hw_watchdog_reset(void)
int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
if (argc < 2) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 2)
return cmd_usage(cmdtp);
if ((strcmp(argv[1], "on") == 0)) {
if ((strcmp(argv[1], "on") == 0))
gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1);
} else if ((strcmp(argv[1], "off") == 0)) {
else if ((strcmp(argv[1], "off") == 0))
gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0);
} else {
cmd_usage(cmdtp);
return 1;
}
else
return cmd_usage(cmdtp);
return 0;
}

3
board/mpl/common/common_util.c
View File

@ -528,8 +528,7 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
#endif
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}

3
board/pcippc2/pcippc2.c
View File

@ -232,8 +232,7 @@ int do_wd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
default:
break;
}
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
U_BOOT_CMD(

5
board/pcs440ep/pcs440ep.c
View File

@ -616,9 +616,8 @@ int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
int rcode = -1;
if (argc < 2) {
usage:
cmd_usage(cmdtp);
return 1;
usage:
return cmd_usage(cmdtp);
}
if (argc >= 3) {

6
board/pdm360ng/pdm360ng.c
View File

@ -635,10 +635,8 @@ static int set_lcd_brightness(char *brightness)
static int cmd_lcd_brightness(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
if (argc < 2) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 2)
return cmd_usage(cmdtp);
return set_lcd_brightness(argv[1]);
}

27
board/pn62/cmd_pn62.c
View File

@ -36,20 +36,20 @@ extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
/*
* Command led: controls the various LEDs 0..11 on the PN62 card.
*/
int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
int do_led(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
{
unsigned int number, function;
unsigned int number, function;
if (argc != 3) {
cmd_usage(cmdtp);
return 1;
}
number = simple_strtoul(argv[1], NULL, 10);
if (number > PN62_LED_MAX)
return 1;
function = simple_strtoul(argv[2], NULL, 16);
set_led (number, function);
return 0;
if (argc != 3)
return cmd_usage(cmdtp);
number = simple_strtoul(argv[1], NULL, 10);
if (number > PN62_LED_MAX)
return 1;
function = simple_strtoul(argv[2], NULL, 16);
set_led(number, function);
return 0;
}
U_BOOT_CMD(
led , 3, 1, do_led,
@ -83,8 +83,7 @@ int do_loadpci (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
addr = simple_strtoul(argv[1], NULL, 16);
break;
default:
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
printf ("## Ready for image download ...\n");

6
board/prodrive/pdnb3/pdnb3.c
View File

@ -214,10 +214,8 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong addr;
if (argc < 2) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 2)
return cmd_usage(cmdtp);
addr = simple_strtoul(argv[1], NULL, 16);

12
board/renesas/sh7785lcr/rtl8169_mac.c
View File

@ -304,10 +304,8 @@ int do_set_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
unsigned char mac[6];
char *s, *e;
if (argc != 2) {
cmd_usage(cmdtp);
return 1;
}
if (argc != 2)
return cmd_usage(cmdtp);
s = argv[1];
@ -330,10 +328,8 @@ U_BOOT_CMD(
int do_print_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
if (argc != 1) {
cmd_usage(cmdtp);
return 1;
}
if (argc != 1)
return cmd_usage(cmdtp);
mac_read();

9
board/renesas/sh7785lcr/selfcheck.c
View File

@ -112,10 +112,8 @@ int do_hw_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char *cmd;
if (argc != 2) {
cmd_usage(cmdtp);
return 1;
}
if (argc != 2)
return cmd_usage(cmdtp);
cmd = argv[1];
switch (cmd[0]) {
@ -150,8 +148,7 @@ int do_hw_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
test_net();
break;
default:
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
return 0;

8
board/sbc8548/sbc8548.c
View File

@ -398,11 +398,9 @@ int last_stage_init(void)
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI1
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE1
ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#ifdef CONFIG_FSL_PCI_INIT
FT_FSL_PCI_SETUP;
#endif
}
#endif

16
board/sbc8641d/law.c
View File

@ -32,11 +32,11 @@
*
* 0x0000_0000 DDR 256M
* 0x1000_0000 DDR2 256M
* 0x8000_0000 PCI1 MEM 512M
* 0xa000_0000 PCI2 MEM 512M
* 0x8000_0000 PCIE1 MEM 512M
* 0xa000_0000 PCIE2 MEM 512M
* 0xc000_0000 RapidIO 512M
* 0xe200_0000 PCI1 IO 16M
* 0xe300_0000 PCI2 IO 16M
* 0xe200_0000 PCIE1 IO 16M
* 0xe300_0000 PCIE2 IO 16M
* 0xf800_0000 CCSRBAR 2M
* 0xfe00_0000 FLASH (boot bank) 32M
*
@ -49,11 +49,11 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
#endif
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
};

55
board/sbc8641d/sbc8641d.c
View File

@ -191,16 +191,16 @@ static struct pci_config_table pci_fsl86xxads_config_table[] = {
};
#endif
static struct pci_controller pci1_hose = {
static struct pci_controller pcie1_hose = {
#ifndef CONFIG_PCI_PNP
config_table:pci_mpc86xxcts_config_table
#endif
};
#endif /* CONFIG_PCI */
#ifdef CONFIG_PCI2
static struct pci_controller pci2_hose;
#endif /* CONFIG_PCI2 */
#ifdef CONFIG_PCIE2
static struct pci_controller pcie2_hose;
#endif /* CONFIG_PCIE2 */
int first_free_busno = 0;
@ -212,10 +212,10 @@ void pci_init_board(void)
uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
>> MPC8641_PORDEVSR_IO_SEL_SHIFT;
#ifdef CONFIG_PCI1
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
struct pci_controller *hose = &pci1_hose;
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
struct pci_controller *hose = &pcie1_hose;
struct pci_region *r = hose->regions;
#ifdef DEBUG
uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
@ -236,16 +236,16 @@ void pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
CONFIG_SYS_PCIE1_MEM_BUS,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BUS,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
CONFIG_SYS_PCIE1_IO_BUS,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
@ -264,26 +264,26 @@ void pci_init_board(void)
}
#else
puts("PCI-EXPRESS1: Disabled\n");
#endif /* CONFIG_PCI1 */
#endif /* CONFIG_PCIE1 */
#ifdef CONFIG_PCI2
#ifdef CONFIG_PCIE2
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
struct pci_controller *hose = &pci2_hose;
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
struct pci_controller *hose = &pcie2_hose;
struct pci_region *r = hose->regions;
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI2_MEM_BUS,
CONFIG_SYS_PCI2_MEM_PHYS,
CONFIG_SYS_PCI2_MEM_SIZE,
CONFIG_SYS_PCIE2_MEM_BUS,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCI2_IO_BUS,
CONFIG_SYS_PCI2_IO_PHYS,
CONFIG_SYS_PCI2_IO_SIZE,
CONFIG_SYS_PCIE2_IO_BUS,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
@ -298,7 +298,7 @@ void pci_init_board(void)
}
#else
puts("PCI-EXPRESS 2: Disabled\n");
#endif /* CONFIG_PCI2 */
#endif /* CONFIG_PCIE2 */
}
@ -308,12 +308,7 @@ void ft_board_setup (void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI1
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCI2
ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
#endif
FT_FSL_PCI_SETUP;
}
#endif

3
board/siemens/common/fpga.c
View File

@ -286,8 +286,7 @@ int do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
failure:
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
U_BOOT_CMD(

3
board/siemens/pcu_e/pcu_e.c
View File

@ -399,8 +399,7 @@ int do_puma (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
default:
break;
}
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
U_BOOT_CMD (puma, 4, 1, do_puma,

9
board/spear/common/spr_misc.c
View File

@ -215,10 +215,8 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
char *s, *e;
char i2c_mac[20];
if ((argc > 3) || (argc < 2)) {
cmd_usage(cmdtp);
return 1;
}
if ((argc > 3) || (argc < 2))
return cmd_usage(cmdtp);
if ((!strcmp(argv[1], "cpufreq")) || (!strcmp(argv[1], "ddrfreq"))) {
@ -286,8 +284,7 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
U_BOOT_CMD(chip_config, 3, 1, do_chip_config,

16
board/t3corp/chip_config.c
View File

@ -27,12 +27,26 @@
struct ppc4xx_config ppc4xx_config_val[] = {
{
"600", "CPU: 600 PLB: 200 OPB: 100 EBC: 100",
"600-67", "CPU: 600 PLB: 200 OPB: 67 EBC: 67",
{
0x86, 0x80, 0xce, 0x1f, 0x7d, 0x80, 0x00, 0xe0,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
"600-100", "CPU: 600 PLB: 200 OPB: 100 EBC: 100",
{
0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
"667", "CPU: 667 PLB: 166 OPB: 83 EBC: 83",
{
0x06, 0x80, 0xbb, 0x14, 0x99, 0x82, 0x00, 0xa0,
0x40, 0x88, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
"800", "CPU: 800 PLB: 200 OPB: 100 EBC: 100",
{

8
board/t3corp/init.S
View File

@ -81,11 +81,13 @@ tlbtab:
tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xc, AC_RW | SA_IG)
/* TLB-entry for FPGA(s) */
tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_1M, CONFIG_SYS_FPGA1_BASE, 4,
tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_16M, CONFIG_SYS_FPGA1_BASE, 4,
AC_RW | SA_IG)
tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_1M, CONFIG_SYS_FPGA2_BASE, 4,
tlbentry(CONFIG_SYS_FPGA1_BASE + (16 << 20), SZ_16M,
CONFIG_SYS_FPGA1_BASE + (16 << 20), 4, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_16M, CONFIG_SYS_FPGA2_BASE, 4,
AC_RW | SA_IG)
tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_1M, CONFIG_SYS_FPGA3_BASE, 4,
tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_16M, CONFIG_SYS_FPGA3_BASE, 4,
AC_RW | SA_IG)
/* TLB-entry for OCM */

2
board/t3corp/t3corp.c
View File

@ -45,7 +45,7 @@ int board_early_init_f(void)
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
mtdcr(UIC1PR, 0x7fffffff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */

18
board/tqc/tqm5200/cmd_stk52xx.c
View File

@ -327,8 +327,7 @@ static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
switch (argc) {
case 0:
case 1:
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
case 2:
if (strncmp(argv[1],"saw",3) == 0) {
printf ("Play sawtooth\n");
@ -342,8 +341,7 @@ static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return rcode;
}
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
case 3:
if (strncmp(argv[1],"saw",3) == 0) {
duration = simple_strtoul(argv[2], NULL, 10);
@ -358,8 +356,7 @@ static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
LEFT_RIGHT);
return rcode;
}
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
case 4:
if (strncmp(argv[1],"saw",3) == 0) {
duration = simple_strtoul(argv[2], NULL, 10);
@ -382,8 +379,7 @@ static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
pcm1772_write_reg((uchar)reg, (uchar)val);
return 0;
}
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
case 5:
if (strncmp(argv[1],"saw",3) == 0) {
duration = simple_strtoul(argv[2], NULL, 10);
@ -412,8 +408,7 @@ static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
channel);
return rcode;
}
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
printf ("Usage:\nsound cmd [arg1] [arg2] ...\n");
return 1;
@ -513,8 +508,7 @@ static int cmd_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
channel = LEFT_RIGHT;
break;
default:
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
if ((tmp = getenv ("volume")) != NULL) {

7
board/tqc/tqm85xx/tqm85xx.c
View File

@ -687,12 +687,7 @@ void ft_board_setup (void *blob, bd_t *bd)
{
ft_cpu_setup (blob, bd);
#ifdef CONFIG_PCI1
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE1
ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
FT_FSL_PCI_SETUP;
}
#endif /* CONFIG_OF_BOARD_SETUP */

67
board/trab/cmd_trab.c
View File

@ -167,10 +167,8 @@ int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
int i;
int cycle_status;
if (argc > 1) {
cmd_usage(cmdtp);
return 1;
}
if (argc > 1)
return cmd_usage(cmdtp);
led_init ();
global_vars_init ();
@ -270,14 +268,11 @@ int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int i, dip;
if (argc > 1) {
cmd_usage(cmdtp);
return 1;
}
if (argc > 1)
return cmd_usage(cmdtp);
if ((dip = read_dip ()) == -1) {
if ((dip = read_dip ()) == -1)
return 1;
}
for (i = 0; i < 4; i++) {
if ((dip & (1 << i)) == 0)
@ -303,14 +298,11 @@ int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int vcc5v;
if (argc > 1) {
cmd_usage(cmdtp);
return 1;
}
if (argc > 1)
return cmd_usage(cmdtp);
if ((vcc5v = read_vcc5v ()) == -1) {
if ((vcc5v = read_vcc5v ()) == -1)
return (1);
}
printf ("%d", (vcc5v / 1000));
printf (".%d", (vcc5v % 1000) / 100);
@ -331,10 +323,8 @@ int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int contact_temp;
if (argc > 1) {
cmd_usage(cmdtp);
return 1;
}
if (argc > 1)
return cmd_usage(cmdtp);
tsc2000_spi_init ();
@ -354,36 +344,32 @@ U_BOOT_CMD(
int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
if (argc > 1) {
cmd_usage(cmdtp);
return 1;
}
if (argc > 1)
return cmd_usage(cmdtp);
if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_STATUS, 1,
(unsigned char*) &status, 1)) {
(unsigned char*) &status, 1))
return (1);
}
if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_PASS_CYCLES, 1,
(unsigned char*) &pass_cycles, 2)) {
(unsigned char*) &pass_cycles, 2))
return (1);
}
if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_CYCLE,
1, (unsigned char*) &first_error_cycle, 2)) {
1, (unsigned char*) &first_error_cycle, 2))
return (1);
}
if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NUM,
1, (unsigned char*) &first_error_num, 1)) {
1, (unsigned char*) &first_error_num, 1))
return (1);
}
if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NAME,
1, (unsigned char*)first_error_name,
sizeof (first_error_name))) {
sizeof (first_error_name)))
return (1);
}
if (read_max_cycles () != 0) {
if (read_max_cycles () != 0)
return (1);
}
printf ("max_cycles = %d\n", max_cycles);
printf ("status = %d\n", status);
@ -850,14 +836,11 @@ int do_temp_log (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
struct rtc_time tm;
#endif
if (argc > 2) {
cmd_usage(cmdtp);
return 1;
}
if (argc > 2)
return cmd_usage(cmdtp);
if (argc > 1) {
if (argc > 1)
delay = simple_strtoul(argv[1], NULL, 10);
}
tsc2000_spi_init ();
while (1) {

25
board/trizepsiv/eeprom.c
View File

@ -42,36 +42,29 @@ static int do_read_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *
static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
int offset,value;
if (argc < 4) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 4)
return cmd_usage(cmdtp);
offset=simple_strtoul(argv[2],NULL,16);
value=simple_strtoul(argv[3],NULL,16);
if (offset > 0x40) {
printf("Wrong offset : 0x%x\n",offset);
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
dm9000_write_srom_word(offset, value);
return (0);
}
int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
if (argc < 2) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 2)
return cmd_usage(cmdtp);
if (strcmp (argv[1],"read") == 0) {
if (strcmp (argv[1],"read") == 0)
return (do_read_dm9000_eeprom(cmdtp,flag,argc,argv));
} else if (strcmp (argv[1],"write") == 0) {
else if (strcmp (argv[1],"write") == 0)
return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv));
} else {
cmd_usage(cmdtp);
return 1;
}
else
return cmd_usage(cmdtp);
}
U_BOOT_CMD(

6
board/w7o/cmd_vpd.c
View File

@ -38,10 +38,8 @@ int do_vpd (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
uchar dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
/* Validate usage */
if (argc > 2) {
cmd_usage(cmdtp);
return 1;
}
if (argc > 2)
return cmd_usage(cmdtp);
/* Passed in EEPROM address */
if (argc == 2)

14
board/xes/common/fsl_8xxx_pci.c
View File

@ -398,18 +398,6 @@ void pci_init_board(void)
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_pci_setup(void *blob, bd_t *bd)
{
/* TODO - make node name (eg pci0) dynamic */
#ifdef CONFIG_PCI1
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE1
ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
#endif
#ifdef CONFIG_PCIE2
ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
#endif
#ifdef CONFIG_PCIE3
ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
#endif
FT_FSL_PCI_SETUP;
}
#endif /* CONFIG_OF_BOARD_SETUP */

1
boards.cfg
View File

@ -143,7 +143,6 @@ EP88x powerpc mpc8xx ep88x
ETX094 powerpc mpc8xx etx094
FLAGADM powerpc mpc8xx flagadm
GENIETV powerpc mpc8xx genietv
GTH powerpc mpc8xx gth
hermes powerpc mpc8xx
IP860 powerpc mpc8xx ip860
LANTEC powerpc mpc8xx lantec

12
common/cmd_bedbug.c
View File

@ -84,10 +84,8 @@ int do_bedbug_dis (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
addr = dis_last_addr;
len = dis_last_len;
if (argc < 2) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 2)
return cmd_usage(cmdtp);
if ((flag & CMD_FLAG_REPEAT) == 0) {
/* New command */
@ -125,10 +123,8 @@ int do_bedbug_asm (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
/* -------------------------------------------------- */
int rcode = 0;
if (argc < 2) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 2)
return cmd_usage(cmdtp);
printf ("\nEnter '.' when done\n");
mem_addr = simple_strtoul (argv[1], NULL, 16);

14
common/cmd_bmp.c
View File

@ -102,8 +102,7 @@ static int do_bmp_info(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[
addr = simple_strtoul(argv[1], NULL, 16);
break;
default:
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
return (bmp_info(addr));
@ -127,8 +126,7 @@ static int do_bmp_display(cmd_tbl_t * cmdtp, int flag, int argc, char * const ar
y = simple_strtoul(argv[3], NULL, 10);
break;
default:
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
return (bmp_display(addr, x, y));
@ -159,12 +157,10 @@ static int do_bmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
c = find_cmd_tbl(argv[0], &cmd_bmp_sub[0], ARRAY_SIZE(cmd_bmp_sub));
if (c) {
if (c)
return c->cmd(cmdtp, flag, argc, argv);
} else {
cmd_usage(cmdtp);
return 1;
}
else
return cmd_usage(cmdtp);
}
U_BOOT_CMD(

6
common/cmd_boot.c
View File

@ -40,10 +40,8 @@ int do_go (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
ulong addr, rc;
int rcode = 0;
if (argc < 2) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 2)
return cmd_usage(cmdtp);
addr = simple_strtoul(argv[1], NULL, 16);

11
common/cmd_bootm.c
View File

@ -491,17 +491,14 @@ int do_bootm_subcommand (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv
argv++;
return bootm_start(cmdtp, flag, argc, argv);
}
}
/* Unrecognized command */
else {
cmd_usage(cmdtp);
return 1;
} else {
/* Unrecognized command */
return cmd_usage(cmdtp);
}
if (images.state >= state) {
printf ("Trying to execute a command out of order\n");
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
images.state |= state;

14
common/cmd_cache.c
View File

@ -34,10 +34,6 @@ int do_icache ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
switch (argc) {
case 2: /* on / off */
switch (on_off(argv[1])) {
#if 0 /* prevented by varargs handling; FALLTROUGH is harmless, too */
default: cmd_usage(cmdtp);
return;
#endif
case 0: icache_disable();
break;
case 1: icache_enable ();
@ -49,8 +45,7 @@ int do_icache ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
icache_status() ? "ON" : "OFF");
return 0;
default:
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
return 0;
}
@ -60,10 +55,6 @@ int do_dcache ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
switch (argc) {
case 2: /* on / off */
switch (on_off(argv[1])) {
#if 0 /* prevented by varargs handling; FALLTROUGH is harmless, too */
default: cmd_usage(cmdtp);
return;
#endif
case 0: dcache_disable();
break;
case 1: dcache_enable ();
@ -75,8 +66,7 @@ int do_dcache ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
dcache_status() ? "ON" : "OFF");
return 0;
default:
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
return 0;

24
common/cmd_dcr.c
View File

@ -44,10 +44,8 @@ int do_getdcr ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] )
unsigned long get_dcr (unsigned short);
/* Validate arguments */
if (argc < 2) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 2)
return cmd_usage(cmdtp);
/* Get a DCR */
dcrn = (unsigned short) simple_strtoul (argv[1], NULL, 16);
@ -73,10 +71,8 @@ int do_setdcr (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
extern char console_buffer[];
/* Validate arguments */
if (argc < 2) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 2)
return cmd_usage(cmdtp);
/* Set a DCR */
dcrn = (unsigned short) simple_strtoul (argv[1], NULL, 16);
@ -120,10 +116,8 @@ int do_getidcr (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
char buf[80];
/* Validate arguments */
if (argc < 3) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 3)
return cmd_usage(cmdtp);
/* Find out whether ther is '.' (dot) symbol in the first parameter. */
strncpy (buf, argv[1], sizeof(buf)-1);
@ -176,10 +170,8 @@ int do_setidcr (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
char buf[80];
/* Validate arguments */
if (argc < 4) {
cmd_usage(cmdtp);
return 1;
}
if (argc < 4)
return cmd_usage(cmdtp);
/* Find out whether ther is '.' (dot) symbol in the first parameter. */
strncpy (buf, argv[1], sizeof(buf)-1);

3
common/cmd_df.c
View File

@ -27,8 +27,7 @@ static int do_df(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
}
usage:
cmd_usage(cmdtp);
return 1;
return cmd_usage(cmdtp);
}
U_BOOT_CMD(

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