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x86: baytrail: pci region 3 is not always mapped to end of ram 

Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFFFFFF
and additional SDRAM is mapped from 0x100000000 and up.  There is a
physical memory hole from 0x80000000 to 0xFFFFFFFF for other uses.
Because of this, PCI region 3 should only try to use up to the amount of
SDRAM or 0x80000000, which ever is less.

Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Andrew Bradford 2015-06-03 12:37:39 -04:00 committed by Simon Glass
parent 5c564226fc
commit afbbd413a3
1 changed files with 1 additions and 1 deletions
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2
arch/x86/cpu/baytrail/pci.c
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@ -39,7 +39,7 @@ void board_pci_setup_hose(struct pci_controller *hose)
pci_set_region(hose->regions + 3,
0,
0,
gd->ram_size,
gd->ram_size < 0x80000000 ? gd->ram_size : 0x80000000,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 4;