dm: spi: zynq_spi: Convert to driver model
This converts the zynq spi driver to use the driver model. Minimal functional changes like using meaningful name on structure members wrt mainlined dm spi drivers. - input_hz -> frequency - req_hz -> freq - base -> regs Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
This commit is contained in:
Jagan Teki
parent
5d69df3541
commit
b1c82da266
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@ -1,5 +1,6 @@
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/*
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* (C) Copyright 2013 Inc.
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* (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
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*
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* Xilinx Zynq PS SPI controller driver (master mode only)
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*
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@ -8,6 +9,8 @@
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#include <config.h>
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/io.h>
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@ -44,180 +47,141 @@ struct zynq_spi_regs {
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u32 rxdr; /* 0x20 */
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};
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/* zynq spi slave */
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struct zynq_spi_slave {
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struct spi_slave slave;
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struct zynq_spi_regs *base;
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u8 mode;
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u8 fifo_depth;
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/* zynq spi platform data */
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struct zynq_spi_platdata {
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struct zynq_spi_regs *regs;
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u32 frequency; /* input frequency */
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u32 speed_hz;
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u32 input_hz;
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u32 req_hz;
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};
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static inline struct zynq_spi_slave *to_zynq_spi_slave(struct spi_slave *slave)
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{
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return container_of(slave, struct zynq_spi_slave, slave);
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}
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/* zynq spi priv */
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struct zynq_spi_priv {
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struct zynq_spi_regs *regs;
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u8 mode;
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u8 fifo_depth;
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u32 freq; /* required frequency */
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};
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static inline struct zynq_spi_regs *get_zynq_spi_base(int dev)
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static inline struct zynq_spi_regs *get_zynq_spi_regs(struct udevice *bus)
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{
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if (dev)
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if (bus->seq)
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return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR1;
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else
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return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR0;
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}
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static void zynq_spi_init_hw(struct zynq_spi_slave *zslave)
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static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
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{
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struct zynq_spi_platdata *plat = bus->platdata;
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plat->regs = get_zynq_spi_regs(bus);
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plat->frequency = 166666700;
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plat->speed_hz = plat->frequency / 2;
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return 0;
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}
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static void zynq_spi_init_hw(struct zynq_spi_priv *priv)
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{
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struct zynq_spi_regs *regs = priv->regs;
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u32 confr;
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/* Disable SPI */
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writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr);
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writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
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/* Disable Interrupts */
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writel(ZYNQ_SPI_IXR_ALL_MASK, &zslave->base->idr);
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writel(ZYNQ_SPI_IXR_ALL_MASK, ®s->idr);
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/* Clear RX FIFO */
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while (readl(&zslave->base->isr) &
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while (readl(®s->isr) &
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ZYNQ_SPI_IXR_RXNEMPTY_MASK)
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readl(&zslave->base->rxdr);
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readl(®s->rxdr);
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/* Clear Interrupts */
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writel(ZYNQ_SPI_IXR_ALL_MASK, &zslave->base->isr);
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writel(ZYNQ_SPI_IXR_ALL_MASK, ®s->isr);
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/* Manual slave select and Auto start */
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confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |
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ZYNQ_SPI_CR_MSTREN_MASK;
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confr &= ~ZYNQ_SPI_CR_MSA_MASK;
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writel(confr, &zslave->base->cr);
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writel(confr, ®s->cr);
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/* Enable SPI */
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writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr);
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writel(ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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static int zynq_spi_probe(struct udevice *bus)
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{
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/* 2 bus with 3 chipselect */
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return bus < 2 && cs < 3;
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struct zynq_spi_platdata *plat = dev_get_platdata(bus);
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struct zynq_spi_priv *priv = dev_get_priv(bus);
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priv->regs = plat->regs;
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priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
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/* init the zynq spi hw */
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zynq_spi_init_hw(priv);
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return 0;
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}
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void spi_cs_activate(struct spi_slave *slave)
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static void spi_cs_activate(struct udevice *dev, uint cs)
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{
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struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
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struct udevice *bus = dev->parent;
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struct zynq_spi_priv *priv = dev_get_priv(bus);
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struct zynq_spi_regs *regs = priv->regs;
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u32 cr;
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debug("spi_cs_activate: 0x%08x\n", (u32)slave);
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clrbits_le32(&zslave->base->cr, ZYNQ_SPI_CR_CS_MASK);
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cr = readl(&zslave->base->cr);
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clrbits_le32(®s->cr, ZYNQ_SPI_CR_CS_MASK);
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cr = readl(®s->cr);
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/*
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* CS cal logic: CS[13:10]
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* xxx0 - cs0
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* xx01 - cs1
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* x011 - cs2
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*/
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cr |= (~(0x1 << slave->cs) << 10) & ZYNQ_SPI_CR_CS_MASK;
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writel(cr, &zslave->base->cr);
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cr |= (~(0x1 << cs) << 10) & ZYNQ_SPI_CR_CS_MASK;
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writel(cr, ®s->cr);
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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static void spi_cs_deactivate(struct udevice *dev)
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{
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struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
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struct udevice *bus = dev->parent;
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struct zynq_spi_priv *priv = dev_get_priv(bus);
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struct zynq_spi_regs *regs = priv->regs;
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debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
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setbits_le32(&zslave->base->cr, ZYNQ_SPI_CR_CS_MASK);
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setbits_le32(®s->cr, ZYNQ_SPI_CR_CS_MASK);
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}
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void spi_init()
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static int zynq_spi_claim_bus(struct udevice *dev)
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{
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/* nothing to do */
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}
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struct udevice *bus = dev->parent;
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struct zynq_spi_priv *priv = dev_get_priv(bus);
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struct zynq_spi_regs *regs = priv->regs;
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct zynq_spi_slave *zslave;
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if (!spi_cs_is_valid(bus, cs))
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return NULL;
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zslave = spi_alloc_slave(struct zynq_spi_slave, bus, cs);
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if (!zslave) {
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printf("SPI_error: Fail to allocate zynq_spi_slave\n");
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return NULL;
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}
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zslave->base = get_zynq_spi_base(bus);
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zslave->mode = mode;
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zslave->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
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zslave->input_hz = 166666700;
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zslave->speed_hz = zslave->input_hz / 2;
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zslave->req_hz = max_hz;
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/* init the zynq spi hw */
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zynq_spi_init_hw(zslave);
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return &zslave->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
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debug("spi_free_slave: 0x%08x\n", (u32)slave);
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free(zslave);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
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u32 confr = 0;
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u8 baud_rate_val = 0;
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writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr);
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/* Set the SPI Clock phase and polarities */
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confr = readl(&zslave->base->cr);
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confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);
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if (zslave->mode & SPI_CPHA)
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confr |= ZYNQ_SPI_CR_CPHA_MASK;
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if (zslave->mode & SPI_CPOL)
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confr |= ZYNQ_SPI_CR_CPOL_MASK;
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/* Set the clock frequency */
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if (zslave->req_hz == 0) {
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/* Set baudrate x8, if the req_hz is 0 */
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baud_rate_val = 0x2;
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} else if (zslave->speed_hz != zslave->req_hz) {
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while ((baud_rate_val < 8) &&
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((zslave->input_hz /
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(2 << baud_rate_val)) > zslave->req_hz))
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baud_rate_val++;
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zslave->speed_hz = zslave->req_hz / (2 << baud_rate_val);
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}
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confr &= ~ZYNQ_SPI_CR_BRD_MASK;
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confr |= (baud_rate_val << 3);
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writel(confr, &zslave->base->cr);
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writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr);
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writel(ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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static int zynq_spi_release_bus(struct udevice *dev)
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{
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struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
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struct udevice *bus = dev->parent;
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struct zynq_spi_priv *priv = dev_get_priv(bus);
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struct zynq_spi_regs *regs = priv->regs;
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debug("spi_release_bus: 0x%08x\n", (u32)slave);
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writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &zslave->base->enr);
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writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, ®s->enr);
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return 0;
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
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struct udevice *bus = dev->parent;
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struct zynq_spi_priv *priv = dev_get_priv(bus);
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struct zynq_spi_regs *regs = priv->regs;
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struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
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u32 len = bitlen / 8;
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u32 tx_len = len, rx_len = len, tx_tvl;
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const u8 *tx_buf = dout;
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@ -225,7 +189,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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u32 ts, status;
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debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
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slave->bus, slave->cs, bitlen, len, flags);
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bus->seq, slave_plat->cs, bitlen, len, flags);
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if (bitlen % 8) {
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debug("spi_xfer: Non byte aligned SPI transfer\n");
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@ -233,45 +197,126 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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}
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(slave);
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spi_cs_activate(dev, slave_plat->cs);
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while (rx_len > 0) {
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/* Write the data into TX FIFO - tx threshold is fifo_depth */
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tx_tvl = 0;
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while ((tx_tvl < zslave->fifo_depth) && tx_len) {
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while ((tx_tvl < priv->fifo_depth) && tx_len) {
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if (tx_buf)
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buf = *tx_buf++;
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else
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buf = 0;
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writel(buf, &zslave->base->txdr);
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writel(buf, ®s->txdr);
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tx_len--;
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tx_tvl++;
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}
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/* Check TX FIFO completion */
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ts = get_timer(0);
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status = readl(&zslave->base->isr);
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status = readl(®s->isr);
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while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
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if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) {
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printf("spi_xfer: Timeout! TX FIFO not full\n");
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return -1;
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}
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status = readl(&zslave->base->isr);
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status = readl(®s->isr);
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}
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/* Read the data from RX FIFO */
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status = readl(&zslave->base->isr);
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status = readl(®s->isr);
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while (status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) {
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buf = readl(&zslave->base->rxdr);
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buf = readl(®s->rxdr);
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if (rx_buf)
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*rx_buf++ = buf;
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status = readl(&zslave->base->isr);
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status = readl(®s->isr);
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rx_len--;
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}
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}
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if (flags & SPI_XFER_END)
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spi_cs_deactivate(slave);
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spi_cs_deactivate(dev);
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return 0;
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}
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static int zynq_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct zynq_spi_platdata *plat = bus->platdata;
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struct zynq_spi_priv *priv = dev_get_priv(bus);
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struct zynq_spi_regs *regs = priv->regs;
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uint32_t confr;
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u8 baud_rate_val = 0;
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if (speed > plat->frequency)
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speed = plat->frequency;
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/* Set the clock frequency */
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confr = readl(®s->cr);
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if (speed == 0) {
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/* Set baudrate x8, if the freq is 0 */
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baud_rate_val = 0x2;
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} else if (plat->speed_hz != speed) {
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while ((baud_rate_val < 8) &&
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((plat->frequency /
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(2 << baud_rate_val)) > speed))
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baud_rate_val++;
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plat->speed_hz = speed / (2 << baud_rate_val);
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}
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confr &= ~ZYNQ_SPI_CR_BRD_MASK;
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confr |= (baud_rate_val << 3);
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writel(confr, ®s->cr);
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priv->freq = speed;
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debug("zynq_spi_set_speed: regs=%p, mode=%d\n", priv->regs, priv->freq);
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return 0;
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}
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static int zynq_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct zynq_spi_priv *priv = dev_get_priv(bus);
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struct zynq_spi_regs *regs = priv->regs;
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uint32_t confr;
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/* Set the SPI Clock phase and polarities */
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confr = readl(®s->cr);
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confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);
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if (priv->mode & SPI_CPHA)
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confr |= ZYNQ_SPI_CR_CPHA_MASK;
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if (priv->mode & SPI_CPOL)
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confr |= ZYNQ_SPI_CR_CPOL_MASK;
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writel(confr, ®s->cr);
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priv->mode = mode;
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debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode);
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return 0;
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}
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static const struct dm_spi_ops zynq_spi_ops = {
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.claim_bus = zynq_spi_claim_bus,
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.release_bus = zynq_spi_release_bus,
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.xfer = zynq_spi_xfer,
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.set_speed = zynq_spi_set_speed,
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.set_mode = zynq_spi_set_mode,
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};
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static const struct udevice_id zynq_spi_ids[] = {
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{ .compatible = "xlnx,zynq-spi" },
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{ }
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};
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U_BOOT_DRIVER(zynq_spi) = {
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.name = "zynq_spi",
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.id = UCLASS_SPI,
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.of_match = zynq_spi_ids,
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.ops = &zynq_spi_ops,
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.ofdata_to_platdata = zynq_spi_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct zynq_spi_platdata),
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.priv_auto_alloc_size = sizeof(struct zynq_spi_priv),
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.probe = zynq_spi_probe,
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};
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