Fix flash driver for TRAB board (must use Unlock Bypass Reset command
to exit Unlock Bypass Mode); adjust timings for flash, SRAM and CPLD
This commit is contained in:
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5bb226e821
commit
b4757cee52
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@ -2,6 +2,10 @@
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Changes since U-Boot 1.0.0:
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Changes since U-Boot 1.0.0:
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======================================================================
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======================================================================
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* Fix flash driver for TRAB board (must use Unlock Bypass Reset
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command to exit Unlock Bypass Mode); adjust timings for flash, SRAM
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and CPLD
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* Use "-fPIC" instead of "-mrelocatable" to prevent problems with
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* Use "-fPIC" instead of "-mrelocatable" to prevent problems with
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recent tools
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recent tools
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@ -39,7 +39,10 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
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#define CMD_PROGRAM 0x00A000A0
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#define CMD_PROGRAM 0x00A000A0
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#define CMD_UNLOCK_BYPASS 0x00200020
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#define CMD_UNLOCK_BYPASS 0x00200020
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#define CMD_READ_MANF_ID 0x00900090
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#define CMD_READ_MANF_ID 0x00900090
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#define CMD_UNLOCK_BYPASS_RES1 0x00900090
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#define CMD_UNLOCK_BYPASS_RES2 0x00000000
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#define MEM_FLASH_ADDR (*(volatile u32 *)CFG_FLASH_BASE)
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#define MEM_FLASH_ADDR1 (*(volatile u32 *)(CFG_FLASH_BASE + (0x00000555 << 2)))
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#define MEM_FLASH_ADDR1 (*(volatile u32 *)(CFG_FLASH_BASE + (0x00000555 << 2)))
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#define MEM_FLASH_ADDR2 (*(volatile u32 *)(CFG_FLASH_BASE + (0x000002AA << 2)))
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#define MEM_FLASH_ADDR2 (*(volatile u32 *)(CFG_FLASH_BASE + (0x000002AA << 2)))
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@ -331,9 +334,6 @@ volatile static int write_word (flash_info_t * info, ulong dest,
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#endif
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#endif
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iflag = disable_interrupts ();
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iflag = disable_interrupts ();
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MEM_FLASH_ADDR1 = CMD_UNLOCK1;
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MEM_FLASH_ADDR2 = CMD_UNLOCK2;
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MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
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*addr = CMD_PROGRAM;
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*addr = CMD_PROGRAM;
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*addr = data;
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*addr = data;
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@ -402,6 +402,10 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
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int l;
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int l;
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int i, rc;
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int i, rc;
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MEM_FLASH_ADDR1 = CMD_UNLOCK1;
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MEM_FLASH_ADDR2 = CMD_UNLOCK2;
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MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
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wp = (addr & ~3); /* get lower word aligned address */
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wp = (addr & ~3); /* get lower word aligned address */
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/*
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/*
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@ -422,7 +426,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
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}
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}
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if ((rc = write_word (info, wp, data)) != 0) {
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if ((rc = write_word (info, wp, data)) != 0) {
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return (rc);
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goto Done;
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}
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}
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wp += 4;
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wp += 4;
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}
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}
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@ -441,7 +445,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
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}
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}
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if ((rc = write_word (info, wp, data)) != 0) {
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if ((rc = write_word (info, wp, data)) != 0) {
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return (rc);
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goto Done;
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}
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}
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src += 4;
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src += 4;
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wp += 4;
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wp += 4;
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@ -449,7 +453,8 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
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}
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}
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if (cnt == 0) {
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if (cnt == 0) {
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return ERR_OK;
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rc = ERR_OK;
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goto Done;
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}
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}
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/*
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/*
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@ -464,7 +469,14 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
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data = (data >> 8) | (*(uchar *) cp << 24);
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data = (data >> 8) | (*(uchar *) cp << 24);
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}
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}
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return write_word (info, wp, data);
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rc = write_word (info, wp, data);
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Done:
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MEM_FLASH_ADDR = CMD_UNLOCK_BYPASS_RES1;
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MEM_FLASH_ADDR = CMD_UNLOCK_BYPASS_RES2;
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return (rc);
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}
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}
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/*-----------------------------------------------------------------------
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/*-----------------------------------------------------------------------
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@ -48,29 +48,29 @@
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#define BWSCON 0x14000000
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#define BWSCON 0x14000000
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/* Bank0 */
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/* Bank0 */
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#define B0_Tacs 0x3 /* 4 clk */
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#define B0_Tacs 0x1 /* 1 clk */
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#define B0_Tcos 0x3 /* 4 clk */
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#define B0_Tcos 0x1 /* 1 clk */
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#define B0_Tacc 0x7 /* 14 clk */
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#define B0_Tacc 0x5 /* 8 clk */
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#define B0_Tcoh 0x0 /* 0 clk */
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#define B0_Tcoh 0x1 /* 1 clk */
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#define B0_Tah 0x0 /* 0 clk */
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#define B0_Tah 0x1 /* 1 clk */
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#define B0_Tacp 0x0
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#define B0_Tacp 0x0
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#define B0_PMC 0x0 /* normal */
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#define B0_PMC 0x0 /* normal */
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/* Bank1 - SRAM */
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/* Bank1 - SRAM */
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#define B1_Tacs 0x0 /* 0 clk */
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#define B1_Tacs 0x1 /* 1 clk */
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#define B1_Tcos 0x0 /* 0 clk */
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#define B1_Tcos 0x1 /* 1 clk */
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#define B1_Tacc 0x7 /* 14 clk */
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#define B1_Tacc 0x5 /* 8 clk */
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#define B1_Tcoh 0x0 /* 0 clk */
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#define B1_Tcoh 0x1 /* 1 clk */
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#define B1_Tah 0x0 /* 0 clk */
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#define B1_Tah 0x1 /* 1 clk */
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#define B1_Tacp 0x0
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#define B1_Tacp 0x0
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#define B1_PMC 0x0 /* normal */
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#define B1_PMC 0x0 /* normal */
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/* Bank2 - CPLD */
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/* Bank2 - CPLD */
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#define B2_Tacs 0x0 /* 0 clk */
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#define B2_Tacs 0x1 /* 1 clk */
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#define B2_Tcos 0x4 /* 4 clk */
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#define B2_Tcos 0x1 /* 1 clk */
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#define B2_Tacc 0x7 /* 14 clk */
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#define B2_Tacc 0x5 /* 8 clk */
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#define B2_Tcoh 0x4 /* 4 clk */
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#define B2_Tcoh 0x1 /* 1 clk */
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#define B2_Tah 0x0 /* 0 clk */
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#define B2_Tah 0x1 /* 1 clk */
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#define B2_Tacp 0x0
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#define B2_Tacp 0x0
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#define B2_PMC 0x0 /* normal */
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#define B2_PMC 0x0 /* normal */
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