Merge branch 'master' of git://git.denx.de/u-boot-x86
This commit is contained in:
commit
b57129dbda
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@ -24,6 +24,7 @@
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#include <dm.h>
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#include <dm.h>
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#include <errno.h>
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#include <errno.h>
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#include <malloc.h>
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#include <malloc.h>
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#include <syscon.h>
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#include <asm/control_regs.h>
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#include <asm/control_regs.h>
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#include <asm/coreboot_tables.h>
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#include <asm/coreboot_tables.h>
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#include <asm/cpu.h>
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#include <asm/cpu.h>
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@ -751,6 +752,10 @@ int cpu_init_r(void)
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uclass_first_device(UCLASS_PCH, &dev);
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uclass_first_device(UCLASS_PCH, &dev);
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uclass_first_device(UCLASS_LPC, &dev);
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uclass_first_device(UCLASS_LPC, &dev);
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/* Set up pin control if available */
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ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
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debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
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return 0;
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return 0;
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}
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}
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@ -65,6 +65,26 @@
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};
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};
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};
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};
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pch_pinctrl {
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compatible = "intel,x86-pinctrl";
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reg = <0 0>;
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/*
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* As of today, the latest version FSP (gold4) for BayTrail
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* misses the PAD configuration of the SD controller's Card
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* Detect signal. The default PAD value for the CD pin sets
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* the pin to work in GPIO mode, which causes card detect
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* status cannot be reflected by the Present State register
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* in the SD controller (bit 16 & bit 18 are always zero).
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*
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* Configure this pin to function 1 (SD controller).
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*/
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sdmmc3_cd@0 {
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pad-offset = <0x3a0>;
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mode-func = <1>;
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};
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};
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pci {
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pci {
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compatible = "pci-x86";
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compatible = "pci-x86";
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#address-cells = <3>;
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#address-cells = <3>;
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@ -213,7 +233,7 @@
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fsp,mrc-init-mmio-size = <0x800>;
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fsp,mrc-init-mmio-size = <0x800>;
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fsp,mrc-init-spd-addr1 = <0xa0>;
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fsp,mrc-init-spd-addr1 = <0xa0>;
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fsp,mrc-init-spd-addr2 = <0xa2>;
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fsp,mrc-init-spd-addr2 = <0xa2>;
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fsp,emmc-boot-mode = <2>;
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fsp,emmc-boot-mode = <1>;
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fsp,enable-sdio;
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fsp,enable-sdio;
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fsp,enable-sdcard;
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fsp,enable-sdcard;
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fsp,enable-hsuart1;
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fsp,enable-hsuart1;
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@ -30,6 +30,22 @@
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pch_pinctrl {
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pch_pinctrl {
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compatible = "intel,x86-pinctrl";
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compatible = "intel,x86-pinctrl";
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reg = <0 0>;
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/*
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* As of today, the latest version FSP (gold4) for BayTrail
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* misses the PAD configuration of the SD controller's Card
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* Detect signal. The default PAD value for the CD pin sets
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* the pin to work in GPIO mode, which causes card detect
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* status cannot be reflected by the Present State register
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* in the SD controller (bit 16 & bit 18 are always zero).
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*
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* Configure this pin to function 1 (SD controller).
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*/
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sdmmc3_cd@0 {
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pad-offset = <0x3a0>;
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mode-func = <1>;
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};
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};
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};
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chosen {
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chosen {
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@ -217,7 +233,7 @@
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fsp,mrc-init-mmio-size = <0x800>;
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fsp,mrc-init-mmio-size = <0x800>;
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fsp,mrc-init-spd-addr1 = <0xa0>;
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fsp,mrc-init-spd-addr1 = <0xa0>;
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fsp,mrc-init-spd-addr2 = <0xa2>;
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fsp,mrc-init-spd-addr2 = <0xa2>;
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fsp,emmc-boot-mode = <2>;
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fsp,emmc-boot-mode = <1>;
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fsp,enable-sdio;
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fsp,enable-sdio;
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fsp,enable-sdcard;
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fsp,enable-sdcard;
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fsp,enable-hsuart1;
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fsp,enable-hsuart1;
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@ -29,6 +29,7 @@
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pch_pinctrl {
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pch_pinctrl {
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compatible = "intel,x86-pinctrl";
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compatible = "intel,x86-pinctrl";
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reg = <0 0>;
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/* GPIO E0 */
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/* GPIO E0 */
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soc_gpio_s5_0@0 {
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soc_gpio_s5_0@0 {
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@ -72,6 +73,21 @@
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output-value = <1>;
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output-value = <1>;
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direction = <PIN_OUTPUT>;
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direction = <PIN_OUTPUT>;
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};
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};
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/*
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* As of today, the latest version FSP (gold4) for BayTrail
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* misses the PAD configuration of the SD controller's Card
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* Detect signal. The default PAD value for the CD pin sets
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* the pin to work in GPIO mode, which causes card detect
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* status cannot be reflected by the Present State register
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* in the SD controller (bit 16 & bit 18 are always zero).
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*
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* Configure this pin to function 1 (SD controller).
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*/
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sdmmc3_cd@0 {
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pad-offset = <0x3a0>;
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mode-func = <1>;
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};
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};
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};
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chosen {
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chosen {
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@ -246,7 +262,7 @@
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fsp,mrc-init-mmio-size = <0x800>;
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fsp,mrc-init-mmio-size = <0x800>;
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fsp,mrc-init-spd-addr1 = <0xa0>;
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fsp,mrc-init-spd-addr1 = <0xa0>;
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fsp,mrc-init-spd-addr2 = <0xa2>;
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fsp,mrc-init-spd-addr2 = <0xa2>;
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fsp,emmc-boot-mode = <2>;
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fsp,emmc-boot-mode = <1>;
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fsp,enable-sdio;
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fsp,enable-sdio;
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fsp,enable-sdcard;
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fsp,enable-sdcard;
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fsp,enable-hsuart1;
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fsp,enable-hsuart1;
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@ -183,20 +183,20 @@ static int acpi_create_madt_lapic(struct acpi_madt_lapic *lapic,
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int acpi_create_madt_lapics(u32 current)
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int acpi_create_madt_lapics(u32 current)
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{
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{
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struct udevice *dev;
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struct udevice *dev;
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int length = 0;
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int total_length = 0;
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for (uclass_find_first_device(UCLASS_CPU, &dev);
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for (uclass_find_first_device(UCLASS_CPU, &dev);
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dev;
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dev;
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uclass_find_next_device(&dev)) {
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uclass_find_next_device(&dev)) {
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struct cpu_platdata *plat = dev_get_parent_platdata(dev);
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struct cpu_platdata *plat = dev_get_parent_platdata(dev);
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int length = acpi_create_madt_lapic(
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length += acpi_create_madt_lapic(
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(struct acpi_madt_lapic *)current,
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(struct acpi_madt_lapic *)current,
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plat->cpu_id, plat->cpu_id);
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plat->cpu_id, plat->cpu_id);
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current += length;
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current += length;
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total_length += length;
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}
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}
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return length;
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return total_length;
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}
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}
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int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
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int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
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@ -24,6 +24,8 @@ CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_OF_CONTROL=y
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CONFIG_OF_CONTROL=y
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CONFIG_REGMAP=y
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CONFIG_SYSCON=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_MACRONIX=y
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@ -28,6 +28,8 @@ CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_OF_CONTROL=y
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CONFIG_OF_CONTROL=y
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CONFIG_REGMAP=y
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CONFIG_SYSCON=y
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CONFIG_CPU=y
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CONFIG_CPU=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_SPI_FLASH_GIGADEVICE=y
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@ -9,7 +9,7 @@ The PINCTRL master node requires the following properties:
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Pin nodes must be children of the pinctrl master node and can
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Pin nodes must be children of the pinctrl master node and can
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contain the following properties:
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contain the following properties:
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- pad-offset - (required) offset in the IOBASE for the pin to configure
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- pad-offset - (required) offset in the IOBASE for the pin to configure
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- gpio-offset - (required) 2 cells
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- gpio-offset - (required only when 'mode-gpio' is set) 2 cells
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- offset in the GPIOBASE for the pin to configure
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- offset in the GPIOBASE for the pin to configure
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- the bit shift in this register (4 = bit 4)
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- the bit shift in this register (4 = bit 4)
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- mode-gpio - (optional) standalone property to force the pin into GPIO mode
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- mode-gpio - (optional) standalone property to force the pin into GPIO mode
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@ -18,16 +18,16 @@ contain the following properties:
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in case of 'mode-gpio' property set:
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in case of 'mode-gpio' property set:
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- output-value - (optional) this set the default output value of the GPIO
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- output-value - (optional) this set the default output value of the GPIO
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- direction - (optional) this set the direction of the gpio
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- direction - (optional) this set the direction of the gpio
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- pull-str - (optional) this set the pull strength of the pin
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- pull-strength - (optional) this set the pull strength of the pin
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- pull-assign - (optional) this set the pull assignement (up/down) of the pin
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- pull-assign - (optional) this set the pull assignement (up/down) of the pin
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- invert - (optional) this input pin is inverted
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- invert - (optional) this input pin is inverted
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Example:
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Example:
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pin_usb_host_en0@0 {
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pin_usb_host_en0@0 {
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gpio-offset = <0x80 8>;
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gpio-offset = <0x80 8>;
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pad-offset = <0x260>;
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pad-offset = <0x260>;
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mode-gpio;
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mode-gpio;
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output-value = <1>;
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output-value = <1>;
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direction = <PIN_OUTPUT>;
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direction = <PIN_OUTPUT>;
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};
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};
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@ -9,7 +9,6 @@
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#include <fdtdec.h>
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#include <fdtdec.h>
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#include <pch.h>
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#include <pch.h>
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#include <pci.h>
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#include <pci.h>
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#include <syscon.h>
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#include <asm/cpu.h>
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#include <asm/cpu.h>
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#include <asm/gpio.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/io.h>
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@ -119,12 +118,6 @@ static int broadwell_gpio_probe(struct udevice *dev)
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struct broadwell_bank_platdata *plat = dev_get_platdata(dev);
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struct broadwell_bank_platdata *plat = dev_get_platdata(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct broadwell_bank_priv *priv = dev_get_priv(dev);
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struct broadwell_bank_priv *priv = dev_get_priv(dev);
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struct udevice *pinctrl;
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int ret;
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/* Set up pin control if available */
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ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
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debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret);
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uc_priv->gpio_count = GPIO_PER_BANK;
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uc_priv->gpio_count = GPIO_PER_BANK;
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uc_priv->bank_name = plat->bank_name;
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uc_priv->bank_name = plat->bank_name;
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@ -32,7 +32,6 @@
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#include <fdtdec.h>
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#include <fdtdec.h>
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#include <pch.h>
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#include <pch.h>
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#include <pci.h>
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#include <pci.h>
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#include <syscon.h>
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#include <asm/cpu.h>
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#include <asm/cpu.h>
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#include <asm/gpio.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/io.h>
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@ -113,10 +112,6 @@ static int ich6_gpio_probe(struct udevice *dev)
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struct ich6_bank_platdata *plat = dev_get_platdata(dev);
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struct ich6_bank_platdata *plat = dev_get_platdata(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct ich6_bank_priv *bank = dev_get_priv(dev);
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struct ich6_bank_priv *bank = dev_get_priv(dev);
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struct udevice *pinctrl;
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/* Set up pin control if available */
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syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
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uc_priv->gpio_count = GPIO_PER_BANK;
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uc_priv->gpio_count = GPIO_PER_BANK;
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uc_priv->bank_name = plat->bank_name;
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uc_priv->bank_name = plat->bank_name;
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||||||
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